Related issue: #10
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What this PR does / why we need it?

Migrates and optimizes the _layer_norm_fwd_1pass_kernel operator from the open-source state-spaces/mamba repo to run efficiently on Ascend NPU (Atlas 800T A2/A3, verified on 910C).

The operator implements a fused LayerNorm/RMSNorm forward pass with optional SiLU gating (z * sigmoid(z)), supporting norm_before_gate and grouped normalization (ngroups).

Key NPU optimizations over the original per-row GPU kernel:

1. 1D physical core grid (num_core,) + in-kernel task dispatch (tl.range(core_id, task_num, num_core)), replacing the original 2D (M, ngroups) grid.
2. Multi-token batching: each task handles BT rows, BT computed dynamically from UB capacity (_compute_bt).
3. 2D block reduction: rows are organized into a [BT, BLOCK_N] tile and reduced in a single tl.sum(axis=1), eliminating the per-row scalar loop (main perf lever).
4. int32 index/offset arithmetic to avoid int64 scalar degradation.
5. Weight/bias loaded once per task and broadcast across rows; adaptive num_warps/num_stages by hidden size.

Does this PR introduce any user-facing change?

Yes — adds a new public Triton operator API:

from mindspeed_ops.api.triton.layer_norm_fwd_1pass import layer_norm_fwd_1pass

layer_norm_fwd_1pass(x, weight, bias=None, z=None, eps=1e-5,
                     norm_before_gate=True, is_rms_norm=False, ngroups=1)
# Returns: (y, mean, rstd)

New files (7):

How was this patch tested?

1. UT 精度测试 (147 passed)

• Shapes: (2,64), (4,128), (8,256), (16,512), (32,1024), (64,2048)
• Dtypes: fp32, bf16, fp16
• Configs: LN/RMS × has_z/no_z × norm_before_gate T/F（8种组合）+ ngroups=2
• Baseline: CPU golden (float32 compute)
• Thresholds: fp32 ratio=1e-4/atol=1e-5, bf16 1e-2/5e-3, fp16 1e-3/5e-4

2. ATK 精度测试 (23/23 passed)

• 用例数: 23（多 shape × 3 dtype 混合）
• 精度基准: single_bm（Triton vs CPU golden）
• 最大绝对误差: fp32 ≤ 3.6e-7, fp16 ≤ 2.4e-4, bf16 ≤ 2.0e-3

3. ATK 性能测试 (23 cases, Triton vs torch_npu)

• 平均加速比: ~10.7x
• 最高加速比: 18.23x

4. 优化前后对比 (msprof kernel 级, fp16, 910C)

对比原始 Triton 实现（per-row grid=(M,) 基线）：

• 平均加速比: ~4.95x
• 12/12 用例均达标

5. 竞品性能对比（910C vs A100）

算子分类: VV 类算子，Memory Bound（msprof 显示 aivector compute usage < 20%，瓶颈在 HBM 搬运）

折算方法（按任务书公式）:

• 硬件带宽比: NPU/A100 = 1800/2039 = 0.88
• A100 耗时 = NPU 基线耗时 × 0.88（同一 kernel，A100 带宽更高所以更快）
• 达标线: VV 类 Memory Bound = 0.88 × 0.9 = 0.8x
• 达标条件: A100 耗时 / NPU 优化耗时 >= 0.8（即 NPU 优化后最多比 A100 慢 25%）

• 达标用例: 8/8（全部达标）
• 平均性能比: 0.94x（要求 >= 0.8x）
• 结论: 优化后 NPU 性能达到 A100 竞品要求

Constraints / Limitations

1. Not supported on arch35（raises NotImplementedError）
2. BLOCK_N = next_power_of_2(N); very large N may hit UB overflow
3. Inputs forced contiguous(); internal compute in float32, output keeps input dtype