| 文件 | 最后提交记录 | 最后更新时间 |
|---|---|---|
[BOLT] Extend Inliner to work on functions with Pointer Authentication (#162458) The inliner uses DirectSP to check if a function has instructions that modify the SP. Exceptions are stack Push and Pop instructions. We can also allow pointer signing and authenticating instructions. The inliner removes the Return instructions from the inlined functions. If it is a fused pointer-authentication-and-return (e.g. RETAA), we have to generate a new authentication instruction. | 8 个月前 | |
[BOLT][AArch64][instr] Consider targeting ARM64 CPUs without LSE support (#158738) stadd is only available in recent arm64 CPUs that have LSE support (like Cortex-A73 and Cortex-A75) and is not available on old arm64 CPUs (like Cortex-A53 and Cortex-A55). Devices could have a mixture of these two kinds of CPUs, for which we need to provide an option for BOLT to generate instrumentation sequence that emulates what stadd would do. The implementation puts counter increment into an injected helper function so we don't need to update CFG in the function that is being instrumented and instrumentation induced binary size increase will be smaller. | 10 个月前 | |
[BOLT][AArch64] Add more heuristics on epilogue determination (#167077) Add more heuristics to check if a basic block is an AArch64 epilogue. We assume instructions that load from stack or adjust stack pointer as valid epilogue code sequence if and only if they immediately precede the branch instruction that ends the basic block. | 8 个月前 | |
[BOLT] Add BOLT_TARGETS_TO_BUILD Adds BOLT_TARGETS_TO_BUILD, which defaults to the intersection of X86;AArch64 and LLVM_TARGETS_TO_BUILD, but allows configuration to alter that -- for instance omitting one of those two targets even if llvm supports both. Reviewed By: rafauler Differential Revision: https://reviews.llvm.org/D148847 | 3 年前 |