| 文件 | 最后提交记录 | 最后更新时间 |
|---|---|---|
[BOLT][RISCV] Handle CIE's produced by GNU as (#69578) On RISC-V, GNU as produces the following initial instruction in CIE's: DW_CFA_def_cfa_register: r2 While I believe it is technically illegal to use this instruction without first using a DW_CFA_def_cfa (since the offset is undefined), both readelf and llvm-dwarfdump accept this and implicitly set the offset to 0. In BOLT, however, this triggers an assert (in CFISnapshot::advanceTo) as it (correctly) believes the offset is not set. This patch fixes this by setting the offset to 0 whenever executing DW_CFA_def_cfa_register while the offset is undefined. Note that this is probably the simplest workaround but it has a downside: while emitting CFI start, we check if the initial instructions are contained within MCAsmInfo::getInitialFrameState and omit them if they are. This will not be true for GNU CIE's (since they differ from LLVM's) which causes an unnecessary DW_CFA_def_cfa_register to be emitted. While technically correct, it would probably be better to replace the GNU CIE with the one used by LLVM to avoid this situation. This would solve the problem this patch solves while also preventing unnecessary CFI instructions. However, this is a bit trickier to implement correctly so I propose to keep this for a later time. Note on testing: the test creates a simple function with three basic blocks and forces the CFI state of the last one to be different from the others using an arbitrary CFI instruction. Then, --reorder-blocks=reverse is used to force CFISnapshot::advanceTo to be called. This causes an assert on the current main branch. | 2 年前 | |
[BOLT][test] Replace /dev/null with temp file (#73485) NFC processing time script identifies tests by output filename. When /dev/null is used as output filename, we're unable to tell the source test, and the reports are unhelpful. Replace /dev/null/ with %t.null which resolves the issue. | 2 年前 | |
[BOLT] Correctly print preferred disassembly for annotated instructions (#120564) This patch makes sure that BinaryContext::printInstruction prints the preferred disassembly. Preferred disassembly only gets printed when there are no annotations on the MCInst. Therefore, this patch temporarily removes the annotations before printing it. A few examples of before and after on AArch64 instructions are as follows: BEFORE AFTER (preferred disassembly) ret x30 ret orr x30, xzr, x0 mov x30, x0 hint #29 autiasp hint #12 autia1716 Clearly, the preferred disassembly is easier for developers to read, and is the disassembly that tools should be printing. This patch is motivated as part of future work on the llvm-bolt-binary-analysis tool, making sure that the reports it prints do use preferred disassembly. This patch was cherry-picked from https://github.com/kbeyls/llvm-project/tree/bolt-gadget-scanner-prototype. In this current patch, this only affects existing RISCV test cases. This patch also does improve test cases in future patches that will introduce a binary analysis for llvm-bolt-binary-analysis that checks for correct application of pac-ret (pointer authentication on return addresses). | 1 年前 | |
[BOLT][RISCV] Handle CIE's produced by GNU as (#69578) On RISC-V, GNU as produces the following initial instruction in CIE's: DW_CFA_def_cfa_register: r2 While I believe it is technically illegal to use this instruction without first using a DW_CFA_def_cfa (since the offset is undefined), both readelf and llvm-dwarfdump accept this and implicitly set the offset to 0. In BOLT, however, this triggers an assert (in CFISnapshot::advanceTo) as it (correctly) believes the offset is not set. This patch fixes this by setting the offset to 0 whenever executing DW_CFA_def_cfa_register while the offset is undefined. Note that this is probably the simplest workaround but it has a downside: while emitting CFI start, we check if the initial instructions are contained within MCAsmInfo::getInitialFrameState and omit them if they are. This will not be true for GNU CIE's (since they differ from LLVM's) which causes an unnecessary DW_CFA_def_cfa_register to be emitted. While technically correct, it would probably be better to replace the GNU CIE with the one used by LLVM to avoid this situation. This would solve the problem this patch solves while also preventing unnecessary CFI instructions. However, this is a bit trickier to implement correctly so I propose to keep this for a later time. Note on testing: the test creates a simple function with three basic blocks and forces the CFI state of the last one to be different from the others using an arbitrary CFI instruction. Then, --reorder-blocks=reverse is used to force CFISnapshot::advanceTo to be called. This causes an assert on the current main branch. | 2 年前 | |
[BOLT,RISCV] Remove empty name special case from #68977 The special case is unneeded after #89693. Pull Request: https://github.com/llvm/llvm-project/pull/90004 | 2 年前 | |
[BOLT][RISCV] Set minimum function alignment to 2 for RVC (#69837) In #67707, the minimum function alignment on RISC-V was set to 4. When RVC (compressed instructions) is enabled, the minimum alignment can be reduced to 2. This patch implements this by delegating the choice of minimum alignment to a new MCPlusBuilder::getMinFunctionAlignment function. This way, the target-dependent code in BinaryFunction is minimized. | 2 年前 | |
[BOLT][RISCV] Use target features from object file (#69836) We used to hard-code target features for RISC-V. However, most features (with the exception of relax) are stored in the object file. This patch extracts those features to ensure BOLT's output doesn't use any features not present in the input file. | 2 年前 | |
[BOLT][RISCV] Add support for linker relaxation Calls on RISC-V are typically compiled to auipc/jalr pairs to allow a maximum target range (32-bit pc-relative). In order to optimize calls to near targets, linker relaxation may replace those pairs with, for example, single jal instructions. To allow BOLT to freely reassign function addresses in relaxed binaries, this patch proposes the following approach: - Expand all relaxed calls back to auipc/jalr; - Rely on JITLink to relax those back to shorter forms where possible. This is implemented by detecting all possible call instructions and replacing them with PseudoCALL (or PseudoTAIL) instructions. The RISC-V backend then expands those and adds the necessary relocations for relaxation. Since BOLT generally ignores pseudo instruction, this patch makes MCPlusBuilder::isPseudo virtual so that RISCVMCPlusBuilder can override it to exclude PseudoCALL and PseudoTAIL. To ensure JITLink knows about the correct section addresses while relaxing, reassignment of addresses has been moved to a post-allocation pass. Note that this is probably the time it had to be done in the first place since in notifyResolved (where it was done before), all symbols are supposed to be resolved already. Depends on D159082 Reviewed By: maksfb Differential Revision: https://reviews.llvm.org/D159089 | 2 年前 | |
[BOLT][test] Replace /dev/null with temp file (#73485) NFC processing time script identifies tests by output filename. When /dev/null is used as output filename, we're unable to tell the source test, and the reports are unhelpful. Replace /dev/null/ with %t.null which resolves the issue. | 2 年前 | |
[BOLT][RISCV] Recognize mapping syms with encoded ISA (#68964) RISC-V supports mapping syms for code that encode the exact ISA for which the code is valid. They have the form $x<ISA> where <ISA> is the textual encoding of an ISA specification. BOLT currently doesn't recognize these mapping symbols causing many binaries compiled with newer versions of GCC (which emits them) to not be properly processed. This patch makes sure BOLT recognizes them as code markers. Note that LLVM does not emit these kinds of mapping symbols yet so the test is based on a binary produced by GCC. | 2 年前 | |
[BOLT][RISCV] Recognize mapping symbols The RISC-V psABI [1] defines them similarly to AArch64. [1] https://github.com/riscv-non-isa/riscv-elf-psabi-doc/blob/master/riscv-elf.adoc#mapping-symbol Reviewed By: yota9, Amir Differential Revision: https://reviews.llvm.org/D153277 | 3 年前 | |
[BOLT] Add minimal RISC-V 64-bit support Just enough features are implemented to process a simple "hello world" executable and produce something that still runs (including libc calls). This was mainly a matter of implementing support for various relocations. Currently, the following are handled: - R_RISCV_JAL - R_RISCV_CALL - R_RISCV_CALL_PLT - R_RISCV_BRANCH - R_RISCV_RVC_BRANCH - R_RISCV_RVC_JUMP - R_RISCV_GOT_HI20 - R_RISCV_PCREL_HI20 - R_RISCV_PCREL_LO12_I - R_RISCV_RELAX - R_RISCV_NONE Executables linked with linker relaxation will probably fail to be processed. BOLT relocates .text to a high address while leaving .plt at its original (low) address. This causes PC-relative PLT calls that were relaxed to a JAL to not fit their offset in an I-immediate anymore. This is something that will be addressed in a later patch. Changes to the BOLT core are relatively minor. Two things were tricky to implement and needed slightly larger changes. I'll explain those below. The R_RISCV_CALL(_PLT) relocation is put on the first instruction of a AUIPC/JALR pair, the second does not get any relocation (unlike other PCREL pairs). This causes issues with the combinations of the way BOLT processes binaries and the RISC-V MC-layer handles relocations: - BOLT reassembles instructions one by one and since the JALR doesn't have a relocation, it simply gets copied without modification; - Even though the MC-layer handles R_RISCV_CALL properly (adjusts both the AUIPC and the JALR), it assumes the immediates of both instructions are 0 (to be able to or-in a new value). This will most likely not be the case for the JALR that got copied over. To handle this difficulty without resorting to RISC-V-specific hacks in the BOLT core, a new binary pass was added that searches for AUIPC/JALR pairs and zeroes-out the immediate of the JALR. A second difficulty was supporting ABS symbols. As far as I can tell, ABS symbols were not handled at all, causing __global_pointer$ to break. RewriteInstance::analyzeRelocation was updated to handle these generically. Tests are provided for all supported relocations. Note that in order to test the correct handling of PLT entries, an ELF file produced by GCC had to be used. While I tried to strip the YAML representation, it's still quite large. Any suggestions on how to improve this would be appreciated. Reviewed By: rafauler Differential Revision: https://reviews.llvm.org/D145687 | 3 年前 | |
[BOLT] Correctly print preferred disassembly for annotated instructions (#120564) This patch makes sure that BinaryContext::printInstruction prints the preferred disassembly. Preferred disassembly only gets printed when there are no annotations on the MCInst. Therefore, this patch temporarily removes the annotations before printing it. A few examples of before and after on AArch64 instructions are as follows: BEFORE AFTER (preferred disassembly) ret x30 ret orr x30, xzr, x0 mov x30, x0 hint #29 autiasp hint #12 autia1716 Clearly, the preferred disassembly is easier for developers to read, and is the disassembly that tools should be printing. This patch is motivated as part of future work on the llvm-bolt-binary-analysis tool, making sure that the reports it prints do use preferred disassembly. This patch was cherry-picked from https://github.com/kbeyls/llvm-project/tree/bolt-gadget-scanner-prototype. In this current patch, this only affects existing RISCV test cases. This patch also does improve test cases in future patches that will introduce a binary analysis for llvm-bolt-binary-analysis that checks for correct application of pac-ret (pointer authentication on return addresses). | 1 年前 | |
[BOLT][RISCV] Implement R_RISCV_64 (#67558) Relocation for 64-bit absolute values. | 2 年前 | |
[BOLT][test] Replace /dev/null with temp file (#73485) NFC processing time script identifies tests by output filename. When /dev/null is used as output filename, we're unable to tell the source test, and the reports are unhelpful. Replace /dev/null/ with %t.null which resolves the issue. | 2 年前 | |
[BOLT][test] Replace /dev/null with temp file (#73485) NFC processing time script identifies tests by output filename. When /dev/null is used as output filename, we're unable to tell the source test, and the reports are unhelpful. Replace /dev/null/ with %t.null which resolves the issue. | 2 年前 | |
[BOLT] Correctly print preferred disassembly for annotated instructions (#120564) This patch makes sure that BinaryContext::printInstruction prints the preferred disassembly. Preferred disassembly only gets printed when there are no annotations on the MCInst. Therefore, this patch temporarily removes the annotations before printing it. A few examples of before and after on AArch64 instructions are as follows: BEFORE AFTER (preferred disassembly) ret x30 ret orr x30, xzr, x0 mov x30, x0 hint #29 autiasp hint #12 autia1716 Clearly, the preferred disassembly is easier for developers to read, and is the disassembly that tools should be printing. This patch is motivated as part of future work on the llvm-bolt-binary-analysis tool, making sure that the reports it prints do use preferred disassembly. This patch was cherry-picked from https://github.com/kbeyls/llvm-project/tree/bolt-gadget-scanner-prototype. In this current patch, this only affects existing RISCV test cases. This patch also does improve test cases in future patches that will introduce a binary analysis for llvm-bolt-binary-analysis that checks for correct application of pac-ret (pointer authentication on return addresses). | 1 年前 | |
[BOLT][test] Replace /dev/null with temp file (#73485) NFC processing time script identifies tests by output filename. When /dev/null is used as output filename, we're unable to tell the source test, and the reports are unhelpful. Replace /dev/null/ with %t.null which resolves the issue. | 2 年前 | |
[BOLT][test] Replace /dev/null with temp file (#73485) NFC processing time script identifies tests by output filename. When /dev/null is used as output filename, we're unable to tell the source test, and the reports are unhelpful. Replace /dev/null/ with %t.null which resolves the issue. | 2 年前 | |
[BOLT] Correctly print preferred disassembly for annotated instructions (#120564) This patch makes sure that BinaryContext::printInstruction prints the preferred disassembly. Preferred disassembly only gets printed when there are no annotations on the MCInst. Therefore, this patch temporarily removes the annotations before printing it. A few examples of before and after on AArch64 instructions are as follows: BEFORE AFTER (preferred disassembly) ret x30 ret orr x30, xzr, x0 mov x30, x0 hint #29 autiasp hint #12 autia1716 Clearly, the preferred disassembly is easier for developers to read, and is the disassembly that tools should be printing. This patch is motivated as part of future work on the llvm-bolt-binary-analysis tool, making sure that the reports it prints do use preferred disassembly. This patch was cherry-picked from https://github.com/kbeyls/llvm-project/tree/bolt-gadget-scanner-prototype. In this current patch, this only affects existing RISCV test cases. This patch also does improve test cases in future patches that will introduce a binary analysis for llvm-bolt-binary-analysis that checks for correct application of pac-ret (pointer authentication on return addresses). | 1 年前 | |
[BOLT,test] Add --image-base to tests that use --section-start When using -no-pie without a SECTIONS command, the linker uses the target's default image base. If -Ttext= or --section-start specifies an output section address below this base, the result is likely unintended. LLD will give a diagnostic (#140187) and may change the behavior in the future. It's good to set an explicit image base to avoid relying on its current behavior. BOLT doesn't seem to care whether a PT_PHDR segment is present. Pull Request: https://github.com/llvm/llvm-project/pull/140570 | 1 年前 | |
RISCV: Remove shouldForceRelocation and unneeded relocations Follow-up to #140494 shouldForceRelocation is conservative and produces redundant relocations. For example, RISCVAsmBackend::ForceRelocs (introduced to support mixed relax/norelax code) leads to redundant relocations in the following example adapted from #77436 .option norelax j label // For assembly input, RISCVAsmParser::ParseInstruction sets ForceRelocs (https://reviews.llvm.org/D46423). // For direct object emission, RISCVELFStreamer sets ForceRelocs (#77436) .option relax call foo // linker-relaxable .option norelax j label // redundant relocation due to ForceRelocs .option relax label: Root problem: The isSymbolRefDifferenceFullyResolvedImpl condition in MCAssembler::evaluateFixup does not check whether two locations are separated by a fragment whose size can be indeterminate due to linker instruction (e.g. MCDataFragment with relaxation, or MCAlignFragment due to indeterminate start offst). This patch * Updates the fragment walk code in attemptToFoldSymbolOffsetDifference to treat MCRelaxableFragment (for --riscv-asm-relax-branches) as fixed size after finishLayout. * Adds a condition in addReloc to complement isSymbolRefDifferenceFullyResolvedImpl. * Removes the no longer needed shouldForceRelocation. This fragment walk code path handles nicely handles mixed relax/norelax case from https://discourse.llvm.org/t/possible-problem-related-to-subtarget-usage/75283 and allows us to remove MCSubtargetInfo argument (#73721) as a follow-up. This fragment walk code should be avoided in the absence of linker-relaxable fragments within the current section. Adjust two bolt/test/RISCV tests (#141310) Pull Request: https://github.com/llvm/llvm-project/pull/140692 | 1 年前 | |
[BOLT][test] Replace /dev/null with temp file (#73485) NFC processing time script identifies tests by output filename. When /dev/null is used as output filename, we're unable to tell the source test, and the reports are unhelpful. Replace /dev/null/ with %t.null which resolves the issue. | 2 年前 | |
[BOLT][test] Replace /dev/null with temp file (#73485) NFC processing time script identifies tests by output filename. When /dev/null is used as output filename, we're unable to tell the source test, and the reports are unhelpful. Replace /dev/null/ with %t.null which resolves the issue. | 2 年前 | |
[BOLT][test] Replace /dev/null with temp file (#73485) NFC processing time script identifies tests by output filename. When /dev/null is used as output filename, we're unable to tell the source test, and the reports are unhelpful. Replace /dev/null/ with %t.null which resolves the issue. | 2 年前 | |
[BOLT][test] Replace /dev/null with temp file (#73485) NFC processing time script identifies tests by output filename. When /dev/null is used as output filename, we're unable to tell the source test, and the reports are unhelpful. Replace /dev/null/ with %t.null which resolves the issue. | 2 年前 | |
[RISCV] Support printing immediate of RISCV MCInst in hexadecimal format (#74053) Enable the llvm-objdump to disassemble the immediate of RISCV instruction in hexadecimal format with --print-imm-hex flag. | 2 年前 | |
RISCV: Remove shouldForceRelocation and unneeded relocations Follow-up to #140494 shouldForceRelocation is conservative and produces redundant relocations. For example, RISCVAsmBackend::ForceRelocs (introduced to support mixed relax/norelax code) leads to redundant relocations in the following example adapted from #77436 .option norelax j label // For assembly input, RISCVAsmParser::ParseInstruction sets ForceRelocs (https://reviews.llvm.org/D46423). // For direct object emission, RISCVELFStreamer sets ForceRelocs (#77436) .option relax call foo // linker-relaxable .option norelax j label // redundant relocation due to ForceRelocs .option relax label: Root problem: The isSymbolRefDifferenceFullyResolvedImpl condition in MCAssembler::evaluateFixup does not check whether two locations are separated by a fragment whose size can be indeterminate due to linker instruction (e.g. MCDataFragment with relaxation, or MCAlignFragment due to indeterminate start offst). This patch * Updates the fragment walk code in attemptToFoldSymbolOffsetDifference to treat MCRelaxableFragment (for --riscv-asm-relax-branches) as fixed size after finishLayout. * Adds a condition in addReloc to complement isSymbolRefDifferenceFullyResolvedImpl. * Removes the no longer needed shouldForceRelocation. This fragment walk code path handles nicely handles mixed relax/norelax case from https://discourse.llvm.org/t/possible-problem-related-to-subtarget-usage/75283 and allows us to remove MCSubtargetInfo argument (#73721) as a follow-up. This fragment walk code should be avoided in the absence of linker-relaxable fragments within the current section. Adjust two bolt/test/RISCV tests (#141310) Pull Request: https://github.com/llvm/llvm-project/pull/140692 | 1 年前 | |
[RISCV] Support printing immediate of RISCV MCInst in hexadecimal format (#74053) Enable the llvm-objdump to disassemble the immediate of RISCV instruction in hexadecimal format with --print-imm-hex flag. | 2 年前 | |
[BOLT] Validate secondary entry point (#135731) Some functions have their sizes as zero in input binary's symbol table, like those compiled by assembler. When figuring out function sizes, we may create label symbol if it doesn't point to any constant island. However, before function size is known, marker symbol can not be correctly associated to a function and therefore all such checks would fail and we could end up adding a code label pointing to constant island as secondary entry point and later mistakenly marking the function as not simple. Querying the global marker symbol array has big throughput overhead. Instead we can run an extra check when post processing entry points to identify such label symbols that actually point to constant islands. | 1 年前 |
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