| 文件 | 最后提交记录 | 最后更新时间 |
|---|---|---|
[mlir][amdgpu] Add lowerings for ScaledExtPacked816 (#168123) * Adds lowerings for amdgpy.scaled_ext_packed816 * updates verifiers | 8 个月前 | |
| 10 个月前 | ||
[mlir][amdgpu] Align Chipset with TargetParser (#107720) Update the Chipset struct to follow the IsaVersion definition from llvm's TargetParser. This is a follow up to https://github.com/llvm/llvm-project/pull/106169#discussion_r1733955012. * Add the stepping version. Note: This may break downstream code that compares against the minor version directly. * Use comparisons with full Chipset version where possible. Note that we can't use the code in TargetParser directly because the chipset utility is outside of mlir/Target that re-exports llvm's target library. | 1 年前 | |
[mlir][amdgpu] Remove shared memory optimization pass (#88225) This implementation has a number of issues and ultimately does not work on gfx9. * It does not reduce bank conflicts with wide memory accesses. * It does not correctly account for when LDS bank conflicts occur on amdgpu. * The implementation is too fragile to be used on real-world code. For example, the code bails out on any memref.subview in the root op, even when the subview is not a user of any of the memref.alloc ops. I do not see how these can be easily fixed, therefore I think it's better to delete this code. | 2 年前 |
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| 8 个月前 | ||
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| 2 年前 |