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[AArch64][SME] Improve codegen for aarch64.sme.cnts* when not in streaming mode (#154761) Builtins for reading the streaming vector length are canonicalised to use the aarch64.sme.cntsd intrinisic and a multiply, i.e. - cntsb -> cntsd * 8 - cntsh -> cntsd * 4 - cntsw -> cntsd * 2 This patch also removes the LLVM intrinsics for cnts[b,h,w], and adds patterns to improve codegen when cntsd is multiplied by a constant. | 10 个月前 | |
[MLIR] Apply clang-tidy fixes for llvm-qualified-auto in TileAllocation.cpp (NFC) | 9 个月前 | |
[mlir][ArmSME] Switch to an attribute-based tile allocation scheme (#73253) This reworks the ArmSME dialect to use attributes for tile allocation. This has a number of advantages and corrects some issues with the previous approach: * Tile allocation can now be done ASAP (i.e. immediately after -convert-vector-to-arm-sme) * SSA form for control flow is now supported (e.g.scf.for loops that yield tiles) * ArmSME ops can be converted to intrinsics very late (i.e. after lowering to control flow) * Tests are simplified by removing constants and casts * Avoids correctness issues with representing LLVM immargs as MLIR values - The tile ID on the SME intrinsics is an immarg (so is required to be a compile-time constant), immargs should be mapped to MLIR attributes (this is already the case for intrinsics in the LLVM dialect) - Using MLIR values for immargs can lead to invalid LLVM IR being generated (and passes such as -cse making incorrect optimizations) As part of this patch we bid farewell to the following operations: mlir arm_sme.get_tile_id : i32 arm_sme.cast_tile_to_vector : i32 to vector<[4]x[4]xi32> arm_sme.cast_vector_to_tile : vector<[4]x[4]xi32> to i32 These are now replaced with: mlir // Allocates a new tile with (indeterminate) state: arm_sme.get_tile : vector<[4]x[4]xi32> // A placeholder operation for lowering ArmSME ops to intrinsics: arm_sme.materialize_ssa_tile : vector<[4]x[4]xi32> The new tile allocation works by operations implementing the ArmSMETileOpInterface. This interface says that an operation needs to be assigned a tile ID, and may conditionally allocate a new SME tile. Operations allocate a new tile by implementing... c++ std::optional<arm_sme::ArmSMETileType> getAllocatedTileType() ...and returning what type of tile the op allocates (ZAB, ZAH, etc). Operations that don't allocate a tile return std::nullopt (which is the default behaviour). Currently the following ops are defined as allocating: mlir arm_sme.get_tile arm_sme.zero arm_sme.tile_load arm_sme.outerproduct // (if no accumulator is specified) Allocating operations become the roots for the tile allocation pass, which currently just (naively) assigns all transitive uses of a root operation the same tile ID. However, this is enough to handle current use cases. Once tile IDs have been allocated subsequent rewrites can forward the tile IDs to any newly created operations. | 2 年前 |
| 文件 | 最后提交记录 | 最后更新时间 |
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| 10 个月前 | ||
| 9 个月前 | ||
| 2 年前 |