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GGitHub[mlir] Construct SmallVector with initial values (NFC) (#169239)

67391fc0创建于 2025年11月24日历史提交

文件	最后提交记录	最后更新时间
CMakeLists.txt	[mlir][xegpu] Add OptimizeBlockLoads pass. (#165483) This pass rewrites certain xegpu CreateNd and LoadNd operations that feeds into vector.transpose to more optimal form to improve performance. Specifically, low precision (bitwidth < 32) LoadNd ops that feeds into transpose ops are rewritten to i32 loads with a valid transpose layout such that later passes can use the load with transpose HW feature to accelerate such load ops. **Update:** Pass is renamed to OptimizeBlockLoads because later we plan to add the array length optimization into this pass as well. This will break down a larger load (like 32x32xf16) into more DPAS-favorable array length loads (32x16xf16 with array length = 2). Both these optmizations require rewriting CreateNd and LoadNd and it makes sense to have a common pass for both.	9 个月前
XeGPUBlocking.cpp	[MLIR][XeGPU] Remove leading unit dims from vector ops before unrolling (#165030) This PR uses the upstream populateCastAwayVectorLeadingOneDimPatterns to remove leading unit dims from vector ops and then do the unrolling/blocking	9 个月前
XeGPUFoldAliasOps.cpp	[mlir] Remove unused includes (NFC) (#150266) These are identified by misc-include-cleaner. I've filtered out those that break builds. Also, I'm staying away from llvm-config.h, config.h, and Compiler.h, which likely cause platform- or compiler-specific build failures.	1 年前
XeGPUOptimizeBlockLoads.cpp	[mlir][xegpu] Add OptimizeBlockLoads pass. (#165483) This pass rewrites certain xegpu CreateNd and LoadNd operations that feeds into vector.transpose to more optimal form to improve performance. Specifically, low precision (bitwidth < 32) LoadNd ops that feeds into transpose ops are rewritten to i32 loads with a valid transpose layout such that later passes can use the load with transpose HW feature to accelerate such load ops. **Update:** Pass is renamed to OptimizeBlockLoads because later we plan to add the array length optimization into this pass as well. This will break down a larger load (like 32x32xf16) into more DPAS-favorable array length loads (32x16xf16 with array length = 2). Both these optmizations require rewriting CreateNd and LoadNd and it makes sense to have a common pass for both.	9 个月前
XeGPUPropagateLayout.cpp	[MLIR][XeGPU] Disable block count usage in layout propagation (#168504)	8 个月前
XeGPUSubgroupDistribute.cpp	[mlir] Construct SmallVector with initial values (NFC) (#169239) Identified with llvm-use-ranges.	8 个月前
XeGPUUnroll.cpp	[mlir][XeGPU] Use DistributeLayoutAttr instead of LayoutAttr for load gather/scatter ops (#167850) The PR changes the layout attribute type for xegpu::LoadGatherOp/StoreScatterOp from LayoutAttr to DistributeLayoutAttr to also support xegpu.slice layouts. Initially we [wanted to restrict slice layouts](https://github.com/llvm/llvm-project/pull/163414#discussion_r2478978798) from the attribute, but now it turns out there are actually valid use cases for that: mlir gpu.func @distribute_load_slice_attr() { %2 = memref.alloca() {alignment = 1024} : memref<4096xf32> %offset = arith.constant {layout_result_0 = #xegpu.layout<sg_layout = [8], sg_data = [32], inst_data = [16]> } dense<0> : vector<256xindex> %mask = arith.constant {layout_result_0 = #xegpu.layout<sg_layout = [8], sg_data = [32], inst_data = [16]> } dense<1> : vector<256xi1> %3 = xegpu.load %2[%offset], %mask <{chunk_size = 1, layout = #xegpu.slice<#xegpu.layout<sg_layout = [8, 8], sg_data = [32, 32], inst_data = [8, 16]>, dims = [0]>>} { layout_result_0 = #xegpu.slice<#xegpu.layout<sg_layout = [8, 8], sg_data = [32, 32], inst_data = [8, 16]>, dims = [0]> } : memref<4096xf32>, vector<256xindex>, vector<256xi1> -> vector<256xf32> %4 = vector.broadcast %3 {layout_result_0 = #xegpu.layout<sg_layout = [8, 8], sg_data = [32, 32], inst_data = [8, 16]>} : vector<256xf32> to vector<256x256xf32> gpu.return } Signed-off-by: dchigarev <dmitry.chigarev@intel.com>	8 个月前
XeGPUVectorLinearize.cpp	[mlir][XeGPU][Transform] Add vectorlinearize transform pass. (#158084) Use upstream patterns to create a vectorlinearize pass needed for lowering to XeVM. Linearizes n-D vectors to 1-D vectors. This is needed because, vector-to-llvm does not linearize all the vectors.	10 个月前
XeGPUWgToSgDistribute.cpp	[MLIR] [XeGPU] Fix dropSgLayoutAndData & dropInstData in SliceAttr (#168618)	8 个月前