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Reland: [MLIR][Transforms] Fix Mem2Reg removal order to respect dominance (#68877) This commit fixes a bug in the Mem2Reg operation erasure order. Replacing the use-def based topological order with a dominance-based weak order ensures that no operation is removed before all its uses have been replaced. The order relation uses the topological order of blocks and block internal ordering to determine a deterministic operation order. Additionally, the reliance on the DenseMap key order was eliminated by switching to a MapVector, that gives a deterministic iteration order. Example: %ptr = alloca ... ... %val0 = %load %ptr ... // LOAD0 store %val0 %ptr ... %val1 = load %ptr ... // LOAD1 ` When promoting the slot backing %ptr, it can happen that the LOAD0 was cleaned before LOAD1. This results in all uses of LOAD0 being replaced by its reaching definition, before LOAD1's result is replaced by LOAD0's result. The subsequent erasure of LOAD0 can thus not succeed, as it has remaining usages. | 2 年前 | |
[mlir][NFC] Use getDefiningOp<OpTy>() instead of dyn_cast<OpTy>(getDefiningOp()) (#150428) This PR uses val.getDefiningOp<OpTy>() to replace dyn_cast<OpTy>(val.getDefiningOp()) , dyn_cast_or_null<OpTy>(val.getDefiningOp()) and dyn_cast_if_present<OpTy>(val.getDefiningOp()). | 1 年前 |
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| 2 年前 | ||
| 1 年前 |