| 文件 | 最后提交记录 | 最后更新时间 |
|---|---|---|
[mlir][ROCDL] Add fp4 and fp6 conversion intrinsics, fix fp8 immargs (#140801) This PR adds support for the scaled conversion intrinsics for fp4 and fp6 types so that they can be targetted by a future amdgpu dialect op or used directly. Additionally, this patch refactors the copy-paste-heavy fp8 versions of these scaled conversion intrinsics with tablegen foreach loops, and fixes the fact that certain immargs weren't being stored as attributes. Note that some of the MLIR-level tests for those scaled fp8 intrinsics had incorrect return types, which have been fixed. (Note that while the operations have a known return type, the IR format still prints that type for clarity). | 1 年前 | |
[mlir][ROCDL] Add fp4 and fp6 conversion intrinsics, fix fp8 immargs (#140801) This PR adds support for the scaled conversion intrinsics for fp4 and fp6 types so that they can be targetted by a future amdgpu dialect op or used directly. Additionally, this patch refactors the copy-paste-heavy fp8 versions of these scaled conversion intrinsics with tablegen foreach loops, and fixes the fact that certain immargs weren't being stored as attributes. Note that some of the MLIR-level tests for those scaled fp8 intrinsics had incorrect return types, which have been fixed. (Note that while the operations have a known return type, the IR format still prints that type for clarity). | 1 年前 | |
[mlir][amdgpu] Add lowerings for ScaledExtPacked816 (#168123) * Adds lowerings for amdgpy.scaled_ext_packed816 * updates verifiers | 9 个月前 | |
[mlir][amdgpu] Add lowerings for ScaledExtPacked816 (#168123) * Adds lowerings for amdgpy.scaled_ext_packed816 * updates verifiers | 9 个月前 | |
[mlir][AMDGPU] Implement AMDGPU DPP operation in MLIR. (#89233) Defined AMDGPU DPP operation in mlir to represent semantics. Introduced a new enumeration attribute for different permutations and allowed for different types of arguments. Implemented constant attribute handling for ROCDL::DPPMovOp operation. The operation now correctly accepts constant attributes for dppCtrl, rowMask, bankMask, boundCtrl, and passes them to the corresponding LLVM intrinsic. | 1 年前 | |
[AMDGPU] [MLIR] Add 96 and 128 bit GatherToLDS for gfx950 (#147496) This PR adds 96 and 128 gather_to_lds support for gfx950. Updating lowering, verifier and tests. | 1 年前 | |
[mlir][amdgpu] Properly handle mismatching memref ranks in amdgpu.gather_to_lds (#149407) This op doesn't have any rank or indices restrictions on src/dst memrefs, but was using SameVariadicOperandSize which was causing issues. Also fix some other issues while we at it. | 1 年前 | |
[mlir][amdgpu] Add rocdl.s.waitcnt wrapper (#149670) The main motivations is to pass vmcnt/expcnt/lgkmcnt values directly (similar to the asm format) and delegate architecture-dependent bitpacking to the amdgpu->rocdl lowering. --------- Signed-off-by: Ivan Butygin <ivan.butygin@gmail.com> | 1 年前 | |
[mlir][amdgpu] Update scaled_mfma assembly format with intrinsic shape (#165044) Use the same format as introduced for wmma by https://github.com/llvm/llvm-project/pull/164920 and for mfma by https://github.com/llvm/llvm-project/pull/165037. | 9 个月前 | |
[mlir][amdgpu] Update mfma assembly format with intrinsic shape (#165037) Use the same format as introduced for wmma by https://github.com/llvm/llvm-project/pull/164920. Also make blocks default to 1. | 9 个月前 | |
[mlir][AMDGPU] Add scaled floating point conversion ops (#141554) implement ScaledExtPackedOp and PackedScaledTruncOp | 1 年前 | |
[mlir][AMDGPU] Add scaled floating point conversion ops (#141554) implement ScaledExtPackedOp and PackedScaledTruncOp | 1 年前 | |
[mlir][AMDGPU] Updated PermlaneSwapOp to select correct val (#157586) * as per the instruction description, updated PermlaneSwapOp to select correct val * updated corresponding lit tests Issue it resolves: the block reduction was failing otherwise as we were selecting the {0} always. --------- Signed-off-by: xintin <gaurav.verma@amd.com> | 11 个月前 | |
[mlir] AMDGPUToROCDL: lower amdgpu.swizzle_bitmode (#136223) Repack amdgpu.swizzle_bitmode arguments and lower it to rocdl.ds_swizzle. Repacking logic is follows: * sizeof(arg) < sizeof(i32): bitcast to integer and zext to i32 and then trunc and bitcast back. * sizeof(arg) == sizeof(i32): just bitcast to i32 and back if not i32 * sizeof(arg) > sizeof(i32): bitcast to vector<Nxi32>, extract individual elements and do a series of rocdl.ds_swizzle and then compose vector and bitcast back. Added repacking logic to LLVM utils so it can be used elsewhere. I'm planning to use it for gpu.shuffle later. | 1 年前 | |
[AMDGPU] [MLIR] Add 96 and 128 bit GatherToLDS for gfx950 (#147496) This PR adds 96 and 128 gather_to_lds support for gfx950. Updating lowering, verifier and tests. | 1 年前 | |
[AMDGPU] Adding AMDGPU dialect wrapper for ROCDL transpose loads. (#145395) * 1-to-1 mapping wrapper op. * Direct lowering from AMDGPU wrapper to ROCDL intrinsics. | 1 年前 | |
[mlir][ROCDL] Refactor wmma intrinsics to use attributes not operands where possible (#167041) The current implementation of the WMMA intrinsic ops as they are defined in the ROCDL tablegen is incorrect. They represent as operands what should be attributes such as clamp, opsel, signA/signB. This change performs a refactoring to bring it in line with what we expect. --------- Signed-off-by: Muzammiluddin Syed <muzasyed@amd.com> | 9 个月前 | |
[mlir][ROCDL] Refactor wmma intrinsics to use attributes not operands where possible (#167041) The current implementation of the WMMA intrinsic ops as they are defined in the ROCDL tablegen is incorrect. They represent as operands what should be attributes such as clamp, opsel, signA/signB. This change performs a refactoring to bring it in line with what we expect. --------- Signed-off-by: Muzammiluddin Syed <muzasyed@amd.com> | 9 个月前 | |
[mlir][ROCDL] Refactor wmma intrinsics to use attributes not operands where possible (#167041) The current implementation of the WMMA intrinsic ops as they are defined in the ROCDL tablegen is incorrect. They represent as operands what should be attributes such as clamp, opsel, signA/signB. This change performs a refactoring to bring it in line with what we expect. --------- Signed-off-by: Muzammiluddin Syed <muzasyed@amd.com> | 9 个月前 |
| 文件 | 最后提交记录 | 最后更新时间 |
|---|---|---|
| 1 年前 | ||
| 1 年前 | ||
| 9 个月前 | ||
| 9 个月前 | ||
| 1 年前 | ||
| 1 年前 | ||
| 1 年前 | ||
| 1 年前 | ||
| 9 个月前 | ||
| 9 个月前 | ||
| 1 年前 | ||
| 1 年前 | ||
| 11 个月前 | ||
| 1 年前 | ||
| 1 年前 | ||
| 1 年前 | ||
| 9 个月前 | ||
| 9 个月前 | ||
| 9 个月前 |