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GGitHub[mlir][ArithToAMDGPU] limit scaling truncf/extf support to gfx950 (#155431)

aa5558d1创建于 2025年9月18日历史提交

文件	最后提交记录	最后更新时间
16-bit-floats.mlir	[mlir][Vector] Remove trivial uses of vector.extractelement/vector.insertelement (1/N) (#116053) This patch removes trivial usages of vector.extractelement/vector.insertelement. These operations can be fully represented by vector.extract/vector.insert. See https://discourse.llvm.org/t/rfc-psa-remove-vector-extractelement-and-vector-insertelement-ops-in-favor-of-vector-extract-and-vector-insert-ops/71116 for more information. Further patches will remove more usages of these ops.	1 年前
8-bit-float-saturation-ocp.mlir	[MLIR][AMDGPU] Add OCP FP8 support for new hardware (#127728) (Continuing from #106160) This PR addresses remaining review comments from the original PR. Original PR Description --- Upcoming hardware (gfx12 and some future gfx9) will support the OCP 8-bit float formats for their matrix multiplication intrinsics and conversion operations, retaining existing opcodes and compiler builtins. This commit adds support for these types to the MLIR wrappers around such operations, ensuring that the OCP types aren't used to generate those builtins on hardware that doesn't expect that format and, conversely, to ensure that the pre-OCP formats aren't used on new hardware. --------- Signed-off-by: Mirza Halilcevic <mirza.halilcevic@amd.com> Co-authored-by: Paul Fuqua <pf@acm.org> Co-authored-by: Krzysztof Drewniak <Krzysztof.Drewniak@amd.com>	1 年前
8-bit-float-saturation.mlir	[AMDGPU][MLIR] Replace gfx940 and gfx941 with gfx942 in MLIR (#125836) gfx940 and gfx941 are no longer supported. This is one of a series of PRs to remove them from the code base. For SWDEV-512631	1 年前
8-bit-floats-ocp.mlir	[AMD][ROCDL] Add packed conversions fp8/bf8->bf16 and fp8/bf8->fp32 in ROCDL dialect (#131850) - Add packed conversions fp8/bf8->bf16 for gfx950 and fp8/bf8->fp32 for gfx942 in ROCDL dialect - Update amdgpu.ext_packed_fp8 lowering to use ROCDL packed fp8/bf8->f32 conversions for vector target types and ROCDL scalar fp8/bf8->fp32 for scalar target type. --------- Co-authored-by: Jungwook Park <jungwook.park@amd.com>	1 年前
8-bit-floats.mlir	[AMD][ROCDL] Add packed conversions fp8/bf8->bf16 and fp8/bf8->fp32 in ROCDL dialect (#131850) - Add packed conversions fp8/bf8->bf16 for gfx950 and fp8/bf8->fp32 for gfx942 in ROCDL dialect - Update amdgpu.ext_packed_fp8 lowering to use ROCDL packed fp8/bf8->f32 conversions for vector target types and ROCDL scalar fp8/bf8->fp32 for scalar target type. --------- Co-authored-by: Jungwook Park <jungwook.park@amd.com>	1 年前
scaling-extf.mlir	[mlir][ArithToAMDGPU] limit scaling truncf/extf support to gfx950 (#155431) The current chip guard fails to prevent scaling_extf/truncf patterns from being applied on gfx1100 which does not have scaling support. --------- Signed-off-by: Muzammiluddin Syed <muzasyed@amd.com>	10 个月前
scaling-truncf.mlir	[mlir][ArithToAMDGPU] limit scaling truncf/extf support to gfx950 (#155431) The current chip guard fails to prevent scaling_extf/truncf patterns from being applied on gfx1100 which does not have scaling support. --------- Signed-off-by: Muzammiluddin Syed <muzasyed@amd.com>	10 个月前