| 文件 | 最后提交记录 | 最后更新时间 |
|---|---|---|
[mlir][spirv] Use assemblyFormat to define atomic op assembly (#76323) see #73359 Declarative assemblyFormat ODS is more concise and requires less boilerplate than filling out CPP interfaces. Changes: * updates the Ops defined in SPIRVAtomicOps.td to use assemblyFormat. * Removes print/parse fromAtomcOps.cpp which is now generated by assemblyFormat * Adds Trait to verify that a pointer operand foo's pointee type matches operand bar's type * * Updates error message expected in tests from new Trait * Updates tests to updated format (largely using <operand> in place of "operand") | 2 年前 | |
[mlir][spirv] Handle zero-sized memrefs Make sure to check type conversion results. Add missing tests. Fix some typos in the surrounding code. Fixes: https://github.com/llvm/llvm-project/issues/64409 Reviewed By: antiagainst Differential Revision: https://reviews.llvm.org/D157166 | 2 年前 | |
[mlir][spirv] Use assemblyFormat to define atomic op assembly (#76323) see #73359 Declarative assemblyFormat ODS is more concise and requires less boilerplate than filling out CPP interfaces. Changes: * updates the Ops defined in SPIRVAtomicOps.td to use assemblyFormat. * Removes print/parse fromAtomcOps.cpp which is now generated by assemblyFormat * Adds Trait to verify that a pointer operand foo's pointee type matches operand bar's type * * Updates error message expected in tests from new Trait * Updates tests to updated format (largely using <operand> in place of "operand") | 2 年前 | |
[mlir][Transforms][NFC] Dialect Conversion: Resolve insertion point TODO (#95653) Remove a TODO in the dialect conversion code base when materializing unresolved conversions: // FIXME: Determine a suitable insertion location when there are multiple // inputs. The implementation used to select an insertion point as follows: - If the cast has exactly one operand: right after the definition of the SSA value. - Otherwise: right before the cast op. However, it is not necessary to change the insertion point. Unresolved materializations (UnrealizedConversionCastOp) are built during buildUnresolvedArgumentMaterialization or buildUnresolvedTargetMaterialization. In the former case, the op is inserted at the beginning of the block. In the latter case, only one operand is supported in the dialect conversion, and the op is inserted right after the definition of the SSA value. I.e., the UnrealizedConversionCastOp is already inserted at the right place and it is not necessary to change the insertion point for the resolved materialization op. Note: The IR change changes slightly because the unrealized_conversion_cast ops at the beginning of a block are no longer doubly-inverted (by setting the insertion to the beginning of the block when inserting the unrealized_conversion_cast and again when inserting the resolved conversion op). All affected test cases were fixed by using CHECK-DAG instead of CHECK. Also improve the quality of multiple test cases that did not check for the correct operands. Note: This commit is in preparation of decoupling the argument/source/target materialization logic of the type converter from the dialect conversion (to reduce its complexity and make that functionality usable from a new dialect conversion driver). | 2 年前 | |
[mlir][spirv]: Add Image to Vulkan Storage Class Map (#144899) Extend the "storage class" <-> "memory space" map for the Vulkan SPIR-V environment to include the Image class. 12 is chosen as the next available value in the MemRef memory space list. Signed-off-by: Jack Frankland <jack.frankland@arm.com> | 1 年前 | |
[mlir][spirv]: Add Image to Vulkan Storage Class Map (#144899) Extend the "storage class" <-> "memory space" map for the Vulkan SPIR-V environment to include the Image class. 12 is chosen as the next available value in the MemRef memory space list. Signed-off-by: Jack Frankland <jack.frankland@arm.com> | 1 年前 | |
[mlir][memref-to-spirv]: Remap Image Load Coordinates (#160495) When converting a memref.load from the image address space to a spirv.ImageFetch ensure that we correctly map the load indices to width, height and depth. The lowering currently assumes a linear image tiling, that is row-major memory layout. This allows us to support any memref layout that is a permutation of the dimensions, more complex layouts are not currently supported. Because the ordering of the dimensions in the vector passed to image fetch is the opposite to that in the memref directions a final reversal of the mapped dimensions is always required. --------- Signed-off-by: Jack Frankland <jack.frankland@arm.com> | 10 个月前 |
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