| 文件 | 最后提交记录 | 最后更新时间 |
|---|---|---|
[mlir][vector] Add scalable lowering for transfer_write(transpose) (#101353) This specifically handles the case of a transpose from a vector type like vector<8x[4]xf32> to vector<[4]x8xf32>. Such transposes occur fairly frequently when scalably vectorizing linalg.generics. There is no direct lowering for these (as types like vector<[4]x8xf32> cannot be represented in LLVM-IR). However, if the only use of the transpose is a write, then it is possible to lower the transfer_write(transpose) as a VLA loop. Example: mlir %transpose = vector.transpose %vec, [1, 0] : vector<4x[4]xf32> to vector<[4]x4xf32> vector.transfer_write %transpose, %dest[%i, %j] {in_bounds = [true, true]} : vector<[4]x4xf32>, memref<?x?xf32> Becomes: mlir %c1 = arith.constant 1 : index %c4 = arith.constant 4 : index %c0 = arith.constant 0 : index %0 = vector.extract %arg0[0] : vector<[4]xf32> from vector<4x[4]xf32> %1 = vector.extract %arg0[1] : vector<[4]xf32> from vector<4x[4]xf32> %2 = vector.extract %arg0[2] : vector<[4]xf32> from vector<4x[4]xf32> %3 = vector.extract %arg0[3] : vector<[4]xf32> from vector<4x[4]xf32> %vscale = vector.vscale %c4_vscale = arith.muli %vscale, %c4 : index scf.for %idx = %c0 to %c4_vscale step %c1 { %4 = vector.extract %0[%idx] : f32 from vector<[4]xf32> %5 = vector.extract %1[%idx] : f32 from vector<[4]xf32> %6 = vector.extract %2[%idx] : f32 from vector<[4]xf32> %7 = vector.extract %3[%idx] : f32 from vector<[4]xf32> %slice_i = affine.apply #map(%idx)[%i] %slice = vector.from_elements %4, %5, %6, %7 : vector<4xf32> vector.transfer_write %slice, %arg1[%slice_i, %j] {in_bounds = [true]} : vector<4xf32>, memref<?x?xf32> } | 1 年前 | |
[mlir][vector] add result type to vector.extract assembly format (#66499) The vector.extract assembly format currently only contains the source type, for example: %1 = vector.extract %0[1] : vector<3x7x8xf32> it's not immediately obvious if this is the source or result type. This patch improves the assembly format to make this clearer, so the above becomes: %1 = vector.extract %0[1] : vector<7x8xf32> from vector<3x7x8xf32> | 2 年前 | |
[mlir][vector] add result type to vector.extract assembly format (#66499) The vector.extract assembly format currently only contains the source type, for example: %1 = vector.extract %0[1] : vector<3x7x8xf32> it's not immediately obvious if this is the source or result type. This patch improves the assembly format to make this clearer, so the above becomes: %1 = vector.extract %0[1] : vector<7x8xf32> from vector<3x7x8xf32> | 2 年前 | |
Reland "[mlir][Vector] Re-define masking semantics in vector.transfer ops"" This relands commit 847b5f82a4a34218bf16d6f83f1b7c32df3117ba. Differential Revision: https://reviews.llvm.org/D138079 | 3 年前 | |
[mlir][vector] Folder: shape_cast(extract) -> extract (#146368) In a later PR more shape_cast ops will appear. Specifically, broadcasts that just prepend ones become shape_cast ops (i.e. volume preserving broadcasts are canonicalized to shape_casts). This PR ensures that broadcast-like shape_cast ops fold at least as well as broadcast ops. This is done by modifying patterns that target broadcast ops, to target 'broadcast-like' ops. No new patterns are added, the patterns that exist are just made to match on shape_casts where appropriate. This PR also includes minor code simplifications: use isBroadcastableTo to simplify ExtractOpFromBroadcast and simplify how broadcast dims are detected in foldExtractFromBroadcast. These are NFC. --------- Co-authored-by: Andrzej Warzyński <andrzej.warzynski@gmail.com> | 1 年前 |