| 文件 | 最后提交记录 | 最后更新时间 |
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[mlir][xegpu] Remove vector contract to dpas size restriction (#147470) Removes contraction shape check to allow representing large workgroup-level workloads in preparation for distribution. | 1 年前 | |
[MLIR][XeGPU][VectorToXeGPU] Add lowering from vector.gather/scatter to xegpu.load/store (#158024) Lowering for vector.gather/vector.scatter into xegpu.load/xegpu.store. High level steps to lower vector.gather/scatter: %0 = vector.gather %source[%off1, %off2, %off3][%indices], %mask, %pass_thru : memref<8x16x32xf32>, vector<8xindex>, vector<8xi1>, vector<8xf32> into vector<8xf32> 1. Compute strides and a memref offset for the %source memref using computeMemrefMeta func from the transfer_read/write lowering 2. Compute a linear offset like %lin_off = %base_offset + %off1 * strides#0 + %off2 * strides#1 + %off3 * strides#2 3. Combine the linear offset with %indices: %off = (broadcast %lin_off : index to vector<8xindex>) + %indices * strides#2 4. Convert memref to an i64: %flat_memref = memref.extract_aligned_pointer_as_index %source + arith.index_cast 5. Perform load/store: %vec = xegpu.load %flat_memref[%off], %mask 6. Apply selection to propagate values from the pass_thru vector: %res = arith.select %mask, %vec, %pass_thru | 11 个月前 | |
[MLIR][XeGPU][VectorToXeGPU] Lower vector.load/store/transfer_read/transfer_write to new offsets syntax (#162095) Changes the VectorToXeGPU pass to generate xegpu.load_nd/store_nd ops using new syntax with where offsets are specified at the load/store ops level. mlir // from this %desc = xegpu.create_nd_tdesc %src[%off1, %off2]: memref<8x16xf16> -> !xegpu.tensor_desc<8x16xf16> %res = xegpu.load_nd %desc : !xegpu.tensor_desc<8x16xf16> -> vector<8x16xf16> // to this %desc = xegpu.create_nd_tdesc %src: memref<8x16xf16> -> !xegpu.tensor_desc<8x16xf16> %res = xegpu.load_nd %desc[%off1, %off2] : !xegpu.tensor_desc<8x16xf16> -> vector<8x16xf16> In order to support cases with dimension reduction at the create_nd_tdesc level (e.g. memref<8x8x16xf16> -> tensor_desc<8x16xf16> it was decided to insert a memref.subview that collapses the source shape to 2d, for example: mlir // input: %0 = vector.load %source[%off0, %off1, %off2] : memref<8x16x32xf32>, vector<8x16xf32> // --vector-to-xegpu (old) %tdesc = xegpu.create_nd_tdesc %source[%off0, %off1, %off2] : memref<8x16x32xf32> -> tdesc<8x32xf32> %vec = xegpu.load_nd %tdesc // --vector-to-xegpu (new) %collapsed = memref.subview %source[%off0, 0, 0] [1, 16, 32] [1, 1, 1] : memref<8x16x32xf32> -> memref<16x32xf32, strided<[32, 1], offset: ?>> %tdesc = xegpu.create_nd_tdesc %collapsed : memref<16x32xf32, ...> -> tdesc<8x32xf32> %vec = xegpu.load_nd %tdesc[%off1, %off2] <details><summary>Why we need to change that?</summary> mlir // reduce dim and apply all 3 offsets at load_nd %desc = xegpu.create_nd_tdesc %source : memref<8x16x32xf32> -> !xegpu.tensor_desc<16x32xf32> // error: xegpu.load_nd len(offsets) != desc.rank %res = xegpu.load_nd %desc[%off, %off, %off] : !xegpu.tensor_desc<16x32xf32> -> vector<8x16xf32> </details> --------- Signed-off-by: dchigarev <dmitry.chigarev@intel.com> | 9 个月前 | |
[MLIR][XeGPU][VectorToXeGPU] Add lowering from vector.gather/scatter to xegpu.load/store (#158024) Lowering for vector.gather/vector.scatter into xegpu.load/xegpu.store. High level steps to lower vector.gather/scatter: %0 = vector.gather %source[%off1, %off2, %off3][%indices], %mask, %pass_thru : memref<8x16x32xf32>, vector<8xindex>, vector<8xi1>, vector<8xf32> into vector<8xf32> 1. Compute strides and a memref offset for the %source memref using computeMemrefMeta func from the transfer_read/write lowering 2. Compute a linear offset like %lin_off = %base_offset + %off1 * strides#0 + %off2 * strides#1 + %off3 * strides#2 3. Combine the linear offset with %indices: %off = (broadcast %lin_off : index to vector<8xindex>) + %indices * strides#2 4. Convert memref to an i64: %flat_memref = memref.extract_aligned_pointer_as_index %source + arith.index_cast 5. Perform load/store: %vec = xegpu.load %flat_memref[%off], %mask 6. Apply selection to propagate values from the pass_thru vector: %res = arith.select %mask, %vec, %pass_thru | 11 个月前 | |
[MLIR][XeGPU][VectorToXeGPU] Lower vector.load/store/transfer_read/transfer_write to new offsets syntax (#162095) Changes the VectorToXeGPU pass to generate xegpu.load_nd/store_nd ops using new syntax with where offsets are specified at the load/store ops level. mlir // from this %desc = xegpu.create_nd_tdesc %src[%off1, %off2]: memref<8x16xf16> -> !xegpu.tensor_desc<8x16xf16> %res = xegpu.load_nd %desc : !xegpu.tensor_desc<8x16xf16> -> vector<8x16xf16> // to this %desc = xegpu.create_nd_tdesc %src: memref<8x16xf16> -> !xegpu.tensor_desc<8x16xf16> %res = xegpu.load_nd %desc[%off1, %off2] : !xegpu.tensor_desc<8x16xf16> -> vector<8x16xf16> In order to support cases with dimension reduction at the create_nd_tdesc level (e.g. memref<8x8x16xf16> -> tensor_desc<8x16xf16> it was decided to insert a memref.subview that collapses the source shape to 2d, for example: mlir // input: %0 = vector.load %source[%off0, %off1, %off2] : memref<8x16x32xf32>, vector<8x16xf32> // --vector-to-xegpu (old) %tdesc = xegpu.create_nd_tdesc %source[%off0, %off1, %off2] : memref<8x16x32xf32> -> tdesc<8x32xf32> %vec = xegpu.load_nd %tdesc // --vector-to-xegpu (new) %collapsed = memref.subview %source[%off0, 0, 0] [1, 16, 32] [1, 1, 1] : memref<8x16x32xf32> -> memref<16x32xf32, strided<[32, 1], offset: ?>> %tdesc = xegpu.create_nd_tdesc %collapsed : memref<16x32xf32, ...> -> tdesc<8x32xf32> %vec = xegpu.load_nd %tdesc[%off1, %off2] <details><summary>Why we need to change that?</summary> mlir // reduce dim and apply all 3 offsets at load_nd %desc = xegpu.create_nd_tdesc %source : memref<8x16x32xf32> -> !xegpu.tensor_desc<16x32xf32> // error: xegpu.load_nd len(offsets) != desc.rank %res = xegpu.load_nd %desc[%off, %off, %off] : !xegpu.tensor_desc<16x32xf32> -> vector<8x16xf32> </details> --------- Signed-off-by: dchigarev <dmitry.chigarev@intel.com> | 9 个月前 | |
[mlir][XeGPU][VectorToXeGPU] Use 'xegpu.load' to lower 1D 'vector.transfer_read' for PVC & BMG (#168910) The PR changes the TransferReadLowering to always use xegpu.load (and not xegpu.load_nd) for 1D cases as it has more developed interface (e.g. layouts capabilites). Signed-off-by: dchigarev <dmitry.chigarev@intel.com> | 9 个月前 | |
[MLIR][XeGPU][VectorToXeGPU] Lower vector.load/store/transfer_read/transfer_write to new offsets syntax (#162095) Changes the VectorToXeGPU pass to generate xegpu.load_nd/store_nd ops using new syntax with where offsets are specified at the load/store ops level. mlir // from this %desc = xegpu.create_nd_tdesc %src[%off1, %off2]: memref<8x16xf16> -> !xegpu.tensor_desc<8x16xf16> %res = xegpu.load_nd %desc : !xegpu.tensor_desc<8x16xf16> -> vector<8x16xf16> // to this %desc = xegpu.create_nd_tdesc %src: memref<8x16xf16> -> !xegpu.tensor_desc<8x16xf16> %res = xegpu.load_nd %desc[%off1, %off2] : !xegpu.tensor_desc<8x16xf16> -> vector<8x16xf16> In order to support cases with dimension reduction at the create_nd_tdesc level (e.g. memref<8x8x16xf16> -> tensor_desc<8x16xf16> it was decided to insert a memref.subview that collapses the source shape to 2d, for example: mlir // input: %0 = vector.load %source[%off0, %off1, %off2] : memref<8x16x32xf32>, vector<8x16xf32> // --vector-to-xegpu (old) %tdesc = xegpu.create_nd_tdesc %source[%off0, %off1, %off2] : memref<8x16x32xf32> -> tdesc<8x32xf32> %vec = xegpu.load_nd %tdesc // --vector-to-xegpu (new) %collapsed = memref.subview %source[%off0, 0, 0] [1, 16, 32] [1, 1, 1] : memref<8x16x32xf32> -> memref<16x32xf32, strided<[32, 1], offset: ?>> %tdesc = xegpu.create_nd_tdesc %collapsed : memref<16x32xf32, ...> -> tdesc<8x32xf32> %vec = xegpu.load_nd %tdesc[%off1, %off2] <details><summary>Why we need to change that?</summary> mlir // reduce dim and apply all 3 offsets at load_nd %desc = xegpu.create_nd_tdesc %source : memref<8x16x32xf32> -> !xegpu.tensor_desc<16x32xf32> // error: xegpu.load_nd len(offsets) != desc.rank %res = xegpu.load_nd %desc[%off, %off, %off] : !xegpu.tensor_desc<16x32xf32> -> vector<8x16xf32> </details> --------- Signed-off-by: dchigarev <dmitry.chigarev@intel.com> | 9 个月前 |
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