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[mlir][nvgpu] Allow TMA's last dim to be non-128B without swizzling (#81499) Allow TMA's last dimension to be non-128B when swizzling mode is not set. Test tma_load_64x8_8x128_noswizzle.mlir is failing due to the verifier. This PR will fix that | 2 年前 | |
[mlir][side effect] refactor(*): Include more precise side effects (#94213) This patch adds more precise side effects to the current ops with memory effects, allowing us to determine which OpOperand/OpResult/BlockArgument the operation reads or writes, rather than just recording the reading and writing of values. This allows for convenient use of precise side effects to achieve analysis and optimization. Related discussions: https://discourse.llvm.org/t/rfc-add-operandindex-to-sideeffect-instance/79243 | 2 年前 | |
mlir/LogicalResult: move into llvm (#97309) This patch is part of a project to move the Presburger library into LLVM. | 2 年前 | |
[mlir][VectorToGPU] Update memref stride preconditions on nvgpu.mma.sync path This change removes the requirement that the row stride be statically known when converting vector.transfer_read and vector.transfer_write to distributed SIMT operations in the nvgpu lowering path. It also adds a check to verify that the last dimension of the source memref is statically known to have stride 1 since this is assumed in the conversion logic. No other change should be required since the generated vector.load operations are never created across dimensions other than the last. The routines for checking preconditions on vector.transfer_read/write are moved to under nvgpu utilities. The change is NFC with respect to the GPU dialect lowering path. Reviewed By: ThomasRaoux Differential Revision: https://reviews.llvm.org/D155753 | 2 年前 | |
Revert "Revert "[mlir][Transform] Add support for mma.sync m16n8k16 f16 rewrite." and "[mlir][Transform] Introduce nvgpu transform extensions"" This reverts commit 6506692fe619ef8a1f7c6ea829d9a9eceb31622d. Differential Revision: https://reviews.llvm.org/D153845 | 3 年前 |
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