| 文件 | 最后提交记录 | 最后更新时间 |
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add TE0713+UMFT601X-B FT601 integration dev bitstream (timing clean) FMC LPC dev build for TE0713/TE0701 + UMFT601X-B stack. Fixed timing closure: replaced set_output_delay with set_max_delay -datapath_only to eliminate false IBUF+BUFG clock skew penalty on source-synchronous outputs. Removed erroneous set_input_delay on output-only ft601_be[*]. Added IOB packing for siwu_n, false paths for async GPIO/reset/wakeup. Strategy: Performance_ExplorePostRoutePhysOpt. Results: WNS +0.059 ns, WHS +0.121 ns, DRC 0 errors, 0 failing endpoints. Bitstream: docs/artifacts/te0713-te0701-umft601x-dev-2026-03-21.bit | 5 个月前 | |
Delete docs/assets/img/Nawfal.png | 4 个月前 | |
Add GitHub Pages docs site for antenna and simulation reports | 5 个月前 | |
Add GitHub Pages docs site for antenna and simulation reports | 5 个月前 | |
Add GitHub Pages docs site for antenna and simulation reports | 5 个月前 | |
Publish Simulation Report v2 aligned to current FPGA baseline | 5 个月前 | |
Add release notes page keyed to major bring-up commits | 5 个月前 | |
Add board-day worksheet and cross-link bring-up docs | 5 个月前 | |
add TE0713+UMFT601X-B FT601 integration dev bitstream (timing clean) FMC LPC dev build for TE0713/TE0701 + UMFT601X-B stack. Fixed timing closure: replaced set_output_delay with set_max_delay -datapath_only to eliminate false IBUF+BUFG clock skew penalty on source-synchronous outputs. Removed erroneous set_input_delay on output-only ft601_be[*]. Added IOB packing for siwu_n, false paths for async GPIO/reset/wakeup. Strategy: Performance_ExplorePostRoutePhysOpt. Results: WNS +0.059 ns, WHS +0.121 ns, DRC 0 errors, 0 failing endpoints. Bitstream: docs/artifacts/te0713-te0701-umft601x-dev-2026-03-21.bit | 5 个月前 | |
Build 25 engineering report: MTI canceller + DC notch timing PASS Build 25 results (MTI + DC notch integration): - WNS +0.132 ns, WHS +0.058 ns (all domains PASS) - 9,252 LUTs, 12,488 FFs, 17 BRAM, 142 DSP, 0.753 W - MTI cost: +694 LUTs, +2,104 FFs, 0 BRAM, 0 DSP - Bitstream: radar_system_top_build25.bit (production-safe) - 23/23 FPGA regression, 29/29 MTI checks, 3/3 real-data co-sim Updated reports.html (15-point Build 25 report), implementation-log.html (timeline entries for production fixes, CFAR, MTI), and release-notes.html (new tagged releases, gap status update). | 5 个月前 | |
docs: deprecate GUI V6, update docs for FT2232H production default - Add deprecation headers to GUI_V6.py and GUI_V6_Demo.py - Mark V6 as deprecated in GUI_versions.txt - Update README.md: replace V6 GIF reference with V65 PNG - Add FT2232H production notice banner to docs/index.html | 4 个月前 | |
add TE0713+UMFT601X-B FT601 integration dev bitstream (timing clean) FMC LPC dev build for TE0713/TE0701 + UMFT601X-B stack. Fixed timing closure: replaced set_output_delay with set_max_delay -datapath_only to eliminate false IBUF+BUFG clock skew penalty on source-synchronous outputs. Removed erroneous set_input_delay on output-only ft601_be[*]. Added IOB packing for siwu_n, false paths for async GPIO/reset/wakeup. Strategy: Performance_ExplorePostRoutePhysOpt. Results: WNS +0.059 ns, WHS +0.121 ns, DRC 0 errors, 0 failing endpoints. Bitstream: docs/artifacts/te0713-te0701-umft601x-dev-2026-03-21.bit | 5 个月前 | |
Build 25 engineering report: MTI canceller + DC notch timing PASS Build 25 results (MTI + DC notch integration): - WNS +0.132 ns, WHS +0.058 ns (all domains PASS) - 9,252 LUTs, 12,488 FFs, 17 BRAM, 142 DSP, 0.753 W - MTI cost: +694 LUTs, +2,104 FFs, 0 BRAM, 0 DSP - Bitstream: radar_system_top_build25.bit (production-safe) - 23/23 FPGA regression, 29/29 MTI checks, 3/3 real-data co-sim Updated reports.html (15-point Build 25 report), implementation-log.html (timeline entries for production fixes, CFAR, MTI), and release-notes.html (new tagged releases, gap status update). | 5 个月前 |
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