| ci(emu-performance): dedup & eta filter & disable xscc (#6488) 1. exclude already-selected ckpt from random selection to dedup 2. filter-out slow checkpoints and sort using [profiled eta from perf-trigger](https://github.com/OpenXiangShan/env-scripts/tree/main/perf_trigger/profile) 3. disable XSCC fuzz for the moment, we have known issue with some vectorized mem/str function now --------- Signed-off-by: ngc7331 <ngc7331@outlook.com> | 3 days ago |
| bump difftest & mkdir for wave/perf for local-ci script's run-mode (#1927) * bump difftest, assign empty value to OBJCACHE * local-ci: mkdir for wave/perf at run-mode | 3 years ago |
| docs(xspdb): update some xspdb docs | 5 months ago |
| docs(readme): update kunminghu architecture graph (#3910) | 1 year ago |
| feat(vector): new vector initial commit - Multi-channel decoder support decoding at most 8 vector insts and spliting them into uops - New split rules for complex vector insts like vrgather.vv - Vector continous load and store uops are executed in scala memory address uop pipeline - Add sourcecode dependency to yunsuan module - Cleaned up VLSUConstants by removing unused methods and comments to enhance readability. - Deleted the VfofBuffer class as it was deemed unnecessary for the current implementation. - Add NamedUInt import in package.scala - Fix Backend.scala port names (memWriteback→memIntWriteback, lduWriteback→memFpWriteback) - Remove VfaluType/VfpuType references (5+ wrapper files) - Add isFmac field to IssueQueueRespBundle + ground in DataPath/IssueQueue/Region - Add MFENCE instruction definition - Ground unconnected ports (vecWriteback/vstdIn/toMemExu/exceptionVec/frontend_canAccept) - Fix VecImmExtractor empty extractMap handling - Back up VIAluFix/VIMacU/VIDiv/VCVT/VIPU (pending VecFuConfig migration) | 11 days ago |
| update sbt version | 7 years ago |
| docs(Makefile): correct typos in build scripts (#5918) This is a small cleanup PR for a couple of typos in build-related files. Changes: - `envrionment` -> `environment` in `scripts/Makefile.docker` - `maunally` -> `manually` in the top-level `Makefile` No behavior change. Co-authored-by: =youzi27 <=809891392@qq.com> | 12 days ago |
| feat(vector,vialu): support vector widen and narrow instructions | 3 days ago |
| misc: update PCL information (#899) XiangShan is jointly released by ICT and PCL. | 5 years ago |
| feat(aia): support chiselAIA and align APLIC params (#6386) Port the v2 APLIC/IMSIC integration onto kunminghu-v3. Source v2 PRs: - #6091 ChiselAIA APLIC/IMSIC integration: https://github.com/OpenXiangShan/XiangShan/pull/6091 - #6304 APLIC parameters aligned with kmh-v2.dts: https://github.com/OpenXiangShan/XiangShan/pull/6304 The ChiselAIA submodule is updated to the latest main branch commit c8be865e4fa60d40831ff29e0a30d4269f5ff5b9. Rebase adaptations and the v3 API mapping are documented in the PR comment. No corresponding kunminghu-v3 PR was found. | 18 days ago |
| fix(IOPMP, COVE): integrate IOPMP register error handling (#6449) fix bugs mentioned in https://github.com/OpenXiangShan/XiangShan/issues/6373 | 7 days ago |
| feat(BOP): add student coverage learner (#6435) bump XSCache and Utility (https://github.com/OpenXiangShan/XSCache/pull/29) (https://github.com/OpenXiangShan/Utility/pull/156) | 6 days ago |
| Bump difftest to support new store event api | 11 days ago |
| Bump nemu ref in ready-to-run * NEMU commit: 513786c4c597dd628c6126144937372d6f7fc92e * NEMU configs: * riscv64-xs-ref_defconfig * riscv64-dual-xs-ref_defconfig * riscv64-xs-ref-debug_defconfig * riscv64-dual-xs-ref-debug_defconfig Including: 513786c4 ci: run PR-Agent review on self-hosted runner (#1192) f7b67482 fix(riscv64): initialize mstatus FS to Off (#1190) 39d120ce perf(simpoint): accelerate basic-block profiling (#1178) 4fe3c141 fix(matrix): handle bf16 fp32 mmacc (#1189) c00b6dd1 fix(memory): honor configured base in golden memory (#1187) 0d4a31d5 feat(monitor): support ELF image loading (#1186) be4df824 refactor(memory): remove sparse memory model (#1185) e91df35c ci: request Copilot reviews for pull requests (#1182) e139164f fix(mmu): remove misplaced PTW failure logs (#1183) | 5 days ago |
| chore: bump chisel and submodules (#6297) | 1 month ago |
| feat(BOP): add student coverage learner (#6435) bump XSCache and Utility (https://github.com/OpenXiangShan/XSCache/pull/29) (https://github.com/OpenXiangShan/Utility/pull/156) | 6 days ago |
| refactor(LatDecoder): unity the opcodes passed to LatDecoder * Support VMoveOpcodes and StuOpcodes * Support uncertain latency and change width of latency | 6 days ago |
| fix(docker): fix docker image build by moving MILL_OUTPUT_DIR to tmpfs (#4679) Signed-off-by: Jiuyue Ma <majiuyue@bosc.ac.cn> | 1 year ago |
| fix(xspdb): fix docs typo | 5 months ago |
| refactor: remove TileLink version of XiangShan (#5992) This PR completes the XiangShan cleanup after removing the legacy TileLink-based cache path and consolidating the repo around a single CHI-based config. It removes the remaining TileLink/HuanCun-specific wiring, configs, and build flow dependencies, aligns the codebase with the refactored XSCache submodule, and makes `DefaultConfig` the primary user-facing configuration while keeping `BackendV2Config` available in perf-trigger workflows. In parallel, the CI/test flow is simplified by moving the basic EMU coverage into the dedicated emu-basics workflow and removing redundant coverage from emu.yml. Concretely, this pr removes huancun submodule and its build dependencies, drops the old TL L3 parameter system from SoC/top-level configs, updates imports and package references to the new `xscache.{coupledL2, openLLC, chi, common}` hierarchy, and cleans up scripts, docs, and workflow defaults to reflect the CHI-only world. | 3 months ago |
| chore: bump chisel and submodules (#6297) | 1 month ago |
| refactor(mbtb,Tage): add VecRotate util (#5218) ... for later re-use in ICache also: - fix rotate direction, the original `(j + i) % len` is actually rotating left, `(j + len - i) % len` is right - fix tage base table `io.takenCtrs`, it needs the opposite direction of `startVAddr` to recover original order Though, the above fixes should not have changes in final verilog now, as rotating to left or right behaves the same with `len = 2` and: - add comments in mbtb & Tage for explanation of rotation - remove unused imports | 9 months ago |
| docs: add CONTRIBUTING (#6171) also refine issue template and README. Keypoints: - AI usage requirements - commit/PR title/description guidelines - branch status (including Nanhu-V5) and recommendations for using kunminghu-v2 and v3 - known issues with v3 that are not currently a priority (e.g. side-channel, vector unit) - self-modification-caused difftest faillure is not bug Signed-off-by: ngc7331 <ngc7331@outlook.com> | 2 months ago |
| docs: add CONTRIBUTING (#6171) also refine issue template and README. Keypoints: - AI usage requirements - commit/PR title/description guidelines - branch status (including Nanhu-V5) and recommendations for using kunminghu-v2 and v3 - known issues with v3 that are not currently a priority (e.g. side-channel, vector unit) - self-modification-caused difftest faillure is not bug Signed-off-by: ngc7331 <ngc7331@outlook.com> | 2 months ago |
| chore(docker): remove LC_ALL ENV (#6446) Moved to upstream Dockerfile: https://github.com/OpenXiangShan/xs-env/pull/100 ~~(waiting)~~ | 7 days ago |
| Add MulanPSL-2.0 License (#824) In this commit, we add License for XiangShan project. | 5 years ago |
| docs(Makefile): correct typos in build scripts (#5918) This is a small cleanup PR for a couple of typos in build-related files. Changes: - `envrionment` -> `environment` in `scripts/Makefile.docker` - `maunally` -> `manually` in the top-level `Makefile` No behavior change. Co-authored-by: =youzi27 <=809891392@qq.com> | 12 days ago |
| test: add example of chiseltest's unit-test and generating verilog for xs' module (#1890) * test: add example to genenrate verilog for a small module Just use Parameters from DefaultConfig(& Argparser) like XSTop/SimTop * test: add DecodeUnitTest as an example for xs' chiseltest * ctrlblock: <> usage has changed, unidirection should use := * bump huancun * makefile: mv new makefile cmd into Makefile.test | 3 years ago |
| docs: update copyright year in readme (#6194) Signed-off-by: ceba <ceba_robot@outlook.com> | 2 months ago |
| docs: update copyright year in readme (#6194) Signed-off-by: ceba <ceba_robot@outlook.com> | 2 months ago |
| feat(vector): new vector initial commit - Multi-channel decoder support decoding at most 8 vector insts and spliting them into uops - New split rules for complex vector insts like vrgather.vv - Vector continous load and store uops are executed in scala memory address uop pipeline - Add sourcecode dependency to yunsuan module - Cleaned up VLSUConstants by removing unused methods and comments to enhance readability. - Deleted the VfofBuffer class as it was deemed unnecessary for the current implementation. - Add NamedUInt import in package.scala - Fix Backend.scala port names (memWriteback→memIntWriteback, lduWriteback→memFpWriteback) - Remove VfaluType/VfpuType references (5+ wrapper files) - Add isFmac field to IssueQueueRespBundle + ground in DataPath/IssueQueue/Region - Add MFENCE instruction definition - Ground unconnected ports (vecWriteback/vstdIn/toMemExu/exceptionVec/frontend_canAccept) - Fix VecImmExtractor empty extractMap handling - Back up VIAluFix/VIMacU/VIDiv/VCVT/VIPU (pending VecFuConfig migration) | 11 days ago |
| chore(scalastyle): allow ([a-z][0-9]|perf|debug)_ prefix (#4838) | 1 year ago |
| chore(scalastyle): allow ([a-z][0-9]|perf|debug)_ prefix (#4838) | 1 year ago |