all done
---- <application exited with code 0> ----
Cache simulation results:
Core #0 \(1 thread\(s\)\)
  L1I0 .* stats:
    Hits:                    *[0-9]*[,\.]?...[,\.]?...
    Misses:                  *[0-9,\.]*
    Compulsory misses:       *[0-9,\.]*
    Invalidations:           *0
.*    Miss rate:                        [0-3][,\.]..%
  L1D0 .* stats:
    Hits:                    *[0-9]*[,\.]?...[,\.]?...
    Misses:                  *[0-9\.,]*
    Compulsory misses:       *[0-9\.,]*
    Invalidations:           *0
.*   Miss rate:                        [0-3][,\.]..%
Core #1 \(1 thread\(s\)\)
  L1I1 .* stats:
    Hits:                    *[0-9]*[,\.]?...[,\.]?...
    Misses:                  *[0-9,\.]*
    Compulsory misses:       *[0-9,\.]*
    Invalidations:           *0
.*    Miss rate:                        [0-3][,\.]..%
  L1D1 .* stats:
    Hits:                    *[0-9]*[,\.]?...[,\.]?...
    Misses:                  *[0-9]*[,\.]?...
    Compulsory misses:       *[0-9,\.]*
    Invalidations:           *0
.*   Miss rate:              *[0-9]*[,\.]..%
Core #2 \(0 thread\(s\)\)
Core #3 \(0 thread\(s\)\)
LL .* stats:
    Hits:                    *[0-9]*
    Misses:                  *[0-9]*[,\.]?...
    Compulsory misses:       *[0-9,\.]*
    Invalidations:           *0
.*    Local miss rate:        *[0-9,.]*%
    Child hits:              *[0-9,\.]*[,\.]?...[,\.]?...
    Total miss rate:                  [0-9][,\.]..%