pre-DR init
pre-DR start
pre-DR detach
pre-DR init
pre-DR start
pre-DR detach
pre-DR init
pre-DR start
pre-DR detach
pre-DR init
pre-DR start
pre-DR detach
all done
Cache simulation results:
Core #0 \([0-9] traced CPU\(s\): [#0-9, ]+\)
  L1I0 .* stats:
    Hits:                       *[0-9,\.]*
    Misses:                     *[0-9,\.]*
    Compulsory misses:          *[0-9,\.]*
    Invalidations:              *0.*
  L1D0 .* stats:
    Hits:                       *[0-9,\.]*
    Misses:                     *[0-9,\.]*
    Compulsory misses:          *[0-9,\.]*
    Invalidations:              *0.*
Core #1 \([0-9] traced CPU\(s\).*
Core #2 \([0-9] traced CPU\(s\).*
Core #3 \([0-9] traced CPU\(s\).*
LL .* stats:
    Hits:                       *[0-9,\.]*
    Misses:                     *[0-9,\.]*
    Compulsory misses:          *[0-9,\.]*
    Invalidations:              *0
.*    Local miss rate:        *[0-9,.]*%
    Child hits:                 *[0-9,\.]*
    Total miss rate:            *[0-9,\.]*%