Hello, world!
---- <application exited with code 0> ----
Cache simulation results:
Core #0 \(1 thread\(s\)\)
  L1I .* stats:
    Hits:                         *[0-9,\.]*
    Misses:                       *[0-9,\.]*
    Compulsory misses:            *[0-9,\.]*
    Parent invalidations:         *[0-9,\.]*
    Write invalidations:          *[0-9,\.]*
.*    Miss rate:                        [0-9][,\.]..%
  L1D .* stats:
    Hits:                         *[0-9,\.]*
    Misses:                       *[0-9,\.]*
    Compulsory misses:            *[0-9,\.]*
    Parent invalidations:         *[0-9,\.]*
    Write invalidations:          *[0-9,\.]*
.*   Miss rate:                        [0-9][,\.]..%
L2 .* stats:
    Hits:                         *[0-9,\.]*
    Misses:                       *[0-9,\.]*
    Compulsory misses:            *[0-9,\.]*
    Invalidations:                *[0-9,\.]*
.*   Local miss rate:        *[0-9,.]*%
    Child hits:                   *[0-9,\.]*
    Total miss rate:                  [0-3][,\.]..%
LLC .* stats:
    Hits:                         *[0-9,\.]*
    Misses:                       *[0-9,\.]*
    Compulsory misses:            *[0-9,\.]*
    Invalidations:                *0
.*   Local miss rate:         *[0-9,\.]*%
    Child hits:                   *[0-9,\.]*
    Total miss rate:          *[0-9,\.]*%
Coherence stats:.*