* Copyright (c) 2025 Huawei Technologies Co., Ltd.
* This program is free software, you can redistribute it and/or modify it under the terms and conditions of
* CANN Open Software License Agreement Version 2.0 (the "License").
* Please refer to the License for details. You may not use this file except in compliance with the License.
* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, EITHER EXPRESS OR IMPLIED,
* INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, MERCHANTABILITY, OR FITNESS FOR A PARTICULAR PURPOSE.
* See LICENSE in the root of the software repository for the full text of the License.
*
* The code snippet comes from CANN project
*
* Copyright (c) Huawei Technologies Co., Ltd. 2012-2019. All rights reserved.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef TRS_PKG_H
#define TRS_PKG_H
#include "common_pkg.h"
#define SQCQ_RTS_INFO_LENGTH 5
#define SQCQ_RESV_LENGTH 8
#define SQCQ_UMAX 0xFFFFFFFF
typedef enum tagDrvSqCqType {
DRV_NORMAL_TYPE = 0,
DRV_CALLBACK_TYPE,
DRV_LOGIC_TYPE,
DRV_SHM_TYPE,
DRV_CTRL_TYPE,
DRV_GDB_TYPE,
DRV_INVALID_TYPE
} drvSqCqType_t;
struct halSqCqInputInfo {
drvSqCqType_t type;
uint32_t tsId;
uint32_t sqeSize;
uint32_t cqeSize;
uint32_t sqeDepth;
uint32_t cqeDepth;
uint32_t grpId;
uint32_t flag;
uint32_t cqId;
uint32_t sqId;
uint32_t info[SQCQ_RTS_INFO_LENGTH];
uint32_t ext_info_len;
void *ext_info;
uint32_t res[SQCQ_RESV_LENGTH - 3];
};
struct halSqCqFreeInfo {
drvSqCqType_t type;
uint32_t tsId;
uint32_t sqId;
uint32_t cqId;
uint32_t flag;
uint32_t res[SQCQ_RESV_LENGTH];
};
typedef enum tagDrvSqCqPropType {
DRV_SQCQ_PROP_SQ_STATUS = 0x0,
DRV_SQCQ_PROP_SQ_HEAD,
DRV_SQCQ_PROP_SQ_TAIL,
DRV_SQCQ_PROP_SQ_DISABLE_TO_ENABLE,
DRV_SQCQ_PROP_SQ_CQE_STATUS,
DRV_SQCQ_PROP_SQ_REG_BASE,
DRV_SQCQ_PROP_SQ_BASE,
DRV_SQCQ_PROP_SQ_DEPTH,
DRV_SQCQ_PROP_SQ_PAUSE,
DRV_SQCQ_PROP_SQ_MEM_ATTR,
DRV_SQCQ_PROP_SQ_RESUME,
DRV_SQCQ_PROP_SQCQ_RESET,
DRV_SQCQ_PROP_CQ_DEPTH,
DRV_SQCQ_PROP_SQE_SIZE,
DRV_SQCQ_PROP_CQE_SIZE,
DRV_SQCQ_PROP_H2D_ASYNC_JETTY_INFO,
DRV_SQCQ_PROP_D2D_ASYNC_JETTY_INFO,
DRV_SQCQ_PROP_MAX
} drvSqCqPropType_t;
#define SQCQ_CONFIG_INFO_LENGTH 8
#define SQCQ_CONFIG_INFO_FLAG (SQCQ_CONFIG_INFO_LENGTH - 1)
#define SQCQ_QUERY_INFO_LENGTH 8
struct halSqCqConfigInfo {
drvSqCqType_t type;
uint32_t tsId;
uint32_t sqId;
uint32_t cqId;
drvSqCqPropType_t prop;
uint32_t value[SQCQ_CONFIG_INFO_LENGTH];
};
struct halSqCqQueryInfo {
drvSqCqType_t type;
uint32_t tsId;
uint32_t sqId;
uint32_t cqId;
drvSqCqPropType_t prop;
uint32_t value[SQCQ_QUERY_INFO_LENGTH];
};
enum res_addr_type {
RES_ADDR_TYPE_STARS_NOTIFY_RECORD,
RES_ADDR_TYPE_STARS_CNT_NOTIFY_RECORD,
RES_ADDR_TYPE_STARS_RTSQ,
RES_ADDR_TYPE_CCU_CKE,
RES_ADDR_TYPE_CCU_XN,
RES_ADDR_TYPE_STARS_CNT_NOTIFY_BIT_WR,
RES_ADDR_TYPE_STARS_CNT_NOTIFY_BIT_ADD,
RES_ADDR_TYPE_STARS_CNT_NOTIFY_BIT_CLR,
RES_ADDR_TYPE_STARS_TOPIC_CQE,
RES_ADDR_TYPE_HCCP_URMA_JETTY,
RES_ADDR_TYPE_HCCP_URMA_JFC,
RES_ADDR_TYPE_HCCP_URMA_DB,
RES_ADDR_TYPE_NDA_URMA_DB,
RES_ADDR_TYPE_MAX
};
#define TRS_RES_MAP_RSV_LEN 8
struct trs_res_map_priv {
unsigned int flag;
unsigned int local_devid;
unsigned int remote_devid;
unsigned int rsv[TRS_RES_MAP_RSV_LEN];
};
#define RES_ADDR_INFO_RSV_LEN 2
struct res_addr_info {
unsigned int id;
processType_t target_proc_type;
enum res_addr_type res_type;
unsigned int res_id;
unsigned int flag;
unsigned int rudevid;
unsigned int rsv[RES_ADDR_INFO_RSV_LEN];
};
struct halTaskSendInfo {
drvSqCqType_t type;
uint32_t tsId;
uint32_t sqId;
int32_t timeout;
uint8_t *sqe_addr;
uint32_t sqe_num;
uint32_t pos;
uint32_t res[SQCQ_RESV_LENGTH];
};
struct halReportRecvInfo {
drvSqCqType_t type;
uint32_t tsId;
uint32_t cqId;
int32_t timeout;
uint8_t *cqe_addr;
uint32_t cqe_num;
uint32_t report_cqe_num;
uint32_t stream_id;
uint32_t task_id;
uint32_t res[SQCQ_RESV_LENGTH];
};
typedef enum tagDrvIdType {
DRV_STREAM_ID = 0,
DRV_EVENT_ID,
DRV_MODEL_ID,
DRV_NOTIFY_ID,
DRV_CMO_ID,
DRV_CNT_NOTIFY_ID,
DRV_SQ_ID,
DRV_CQ_ID,
DRV_INVALID_ID,
} drvIdType_t;
#define RESOURCEID_RESV_LENGTH 8
struct halResourceIdInputInfo {
drvIdType_t type;
uint32_t tsId;
uint32_t resourceId;
uint32_t res[RESOURCEID_RESV_LENGTH];
};
struct halResourceIdOutputInfo {
uint32_t resourceId;
uint32_t res[RESOURCEID_RESV_LENGTH];
};
#endif