Problem

In CV UBFuse kernels the epilogue consumes the cube output by rows (stageM * blockShapeNAlign) while queue tensors were still sized by the flat element budget (a0a1t), and 1D flat APIs were used for mixed-dtype vector stages. When tensor row strides differ by dtype (e.g. bool rows are 32B-aligned while float rows are not), the flat interpretation reads/writes wrong addresses and the queue allocation can be smaller than the real per-stage footprint, which corrupts results (scattered mismatches) or overflows UB (aicore exception).

Fix

Keeps the three-size contract (UB allocation >= UB compute size >= valid data size):

Tiling

• basen_align aligns to 32 elements, so it is the supremum of every dtype 32B-aligned row width; cube_ub_stage_size keeps cube-dtype element semantics
• new cube_m_stage_size (max stage rows); after the solver picks STAGE_SIZE_NAME it is overwritten with STAGE_SIZE_NAME / basen_align, so rows * any-dtype-row-width never exceeds the solver per-dtype element budget
• serialize the new field for const/dynamic/DB paths

Kernel init

• stage_size unified to element count (solver budget a0a1t, falling back to cube fragment capacity for tiny stages)
• stage_size_type (rows) comes from cube_m_stage_size on all four flows: inductor const (kConstTilingData), inductor dynamic (params), non-inductor static (kConstTilingData baked by ascbc) and non-inductor dynamic (params.cv_tiling_data)
• TensorSizeAssign emits local_size = stage_size for every UB tensor, so each dtype byte size equals its solver budget exactly
• buf_cube sized by the pure C-fragment capacity
• conv2d stage_size switched to element count as well

Reg APIs

• CvApi2DParams gains valid_size / output_compute_size / input_compute_size
• Cast/Floor/Round/Trunc/Compare use the 2D form with logical {curAivM, curAivN} dims plus per-dtype physical row strides under CV UBFuse
• WhereRegApiCall::GenerateNoLoopCase emits the 2D WhereExtend form with an independent mask stride, fixing bool-mask rows (e.g. align(N,32) != float row width) that previously went through a flat 1D call

Verification

(torch.compile, forced CV fusion, Ascend950PR):

• tensor/broadcast/scalar compares, where (bool mask from GM, int8, int64, two float branches, compare->where), cast (fp16/int32), floor/round/trunc, add/mul/sub/div, max/min, unary and chained cases all match eager bit-exactly
• previously failing N=400/600 and crashing N=664 now pass
• inductor dynamic shape (params path) verified with multiple shapes
• non-inductor flows covered by code-path audit (ascbc bakes kConstTilingData, dynamic reads params.cv_tiling_data)
• UT expectations updated for the new stage_size element semantics

TF non-inductor static-flow fixes (follow-up commit 5a48b96e)

The rework broke TF static-shape kernel compilation (and exposed two latent
misalignments):

• codegen_kernel.cpp: non-inductor static Init referenced
  params.cv_tiling_data->cube_m_stage_size, but TF/GE online-compiled static
  graphs have neither INDUCTOR_CONST_TILING_DATA nor the cv_tiling_data
  Params member (is_dynamic=false), failing with
  no member named 'cv_tiling_data' in 'AutoFusionVector::Params'.
  Now reads the baked solver budget (AutofuseTilingData::STAGE_SIZE_NAME)
  and derives stage rows as stage_size_name / basen_align (conv2d-branch
  pattern).
• asc_codegen_compile.py: host tiling still used
  ub_align_value = 32 / cube_output_type_size; aligned to 32 elements to
  match the kernel-side supremum row width.

TF E2E (GE AutoFuse, --autofuse_enable_pass=matmul, Ascend950PR):
matmul+abs now compiles and runs; 128x128x128 completes with results within
half-cast precision. Note: 28-block (large-shape) MIX launches still
deadlock in the GE/fftsplus dispatch (block group 13 never scheduled) —
tracked separately, not addressed by this PR.

TF non-inductor static-flow fixes (follow-up commit 5a48b96e)

• codegen_kernel.cpp: non-inductor static Init referenced params.cv_tiling_data->cube_m_stage_size, but TF/GE online-compiled static graphs have neither INDUCTOR_CONST_TILING_DATA nor the cv_tiling_data Params member (is_dynamic=false), failing with "no member named 'cv_tiling_data' in 'AutoFusionVector::Params'". Now reads the baked solver budget (AutofuseTilingData::STAGE_SIZE_NAME) and derives stage rows as stage_size_name / basen_align (conv2d-branch pattern).
• asc_codegen_compile.py: host tiling still used ub_align_value = 32 / cube_output_type_size; aligned to 32 elements to match the kernel-side supremum row width.

TF E2E (GE AutoFuse, --autofuse_enable_pass=matmul, Ascend950PR): matmul+abs now compiles and runs; 128x128x128 completes within half-cast precision. Note: 28-block (large-shape) MIX launches still deadlock in the GE/fftsplus dispatch (block group 13 never scheduled) - tracked separately, not addressed by this PR.