fix(a2a3): give the V2C ring its own base in a bidirectional TPipe-pto-isa-AtomGit

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fix(a2a3): give the V2C ring its own base in a bidirectional TPipe #1438

puff_the_magic_dragon创建于 15 天前从puff_the_magic_dragon/pto-isa： fix/a2a3-dir-both-ring-offset 合入到 cann/pto-isa： master

fix(a2a3): give the V2C ring its own base in a bidirectional TPipe #1438

已合并

puff_the_magic_dragon创建于 15 天前

从puff_the_magic_dragon/pto-isa fix/a2a3-dir-both-ring-offset合入到cann/pto-isa master

puff_the_magic_dragon

15 天前

描述

On A2A3 both directions of a DIR_BOTH TPipe addressed the shared GM buffer as
(tileIndex % SLOT_NUM) * SLOT_SIZE + entryOffset, and entryOffset was never set for that
direction mode — so the C2V and V2C rings occupied the same slots and silently overwrote
each other's tiles once more than one tile was in flight. Wrong results, no fault, no hang.

The entryOffset mechanism already exists and is wired through all thirteen addressing sites
(Producer::setEntryOffset at TPush.hpp:96, Consumer::setEntryOffset at :316); nothing
called it, because the TPipe constructor at :470 had an empty body.

This sets the V2C ring base there for is_both — the consumer under __DAV_CUBE__, the
producer under __DAV_VEC__ — giving the layout the TPUSH/TPOP design note specifies: C2V at
offset 0, V2C at SLOT_NUM * SLOT_SIZE, total 2 * SLOT_NUM * SLOT_SIZE. Both terms are
compile-time constants, so the generated address arithmetic is unchanged in cost.

The bidirectional ST case allocated 2 * M * N * sizeof(T) = exactly one ring
(tpushpop_dir_both/main.cpp:47); it is sized for two here, as the frontend now must.

Ordering. This needs a frontend that allocates 2 * SLOT_NUM * SLOT_SIZE for a
bidirectional pipe. pypto currently sizes it as one ring, and that half must ship first, or
this fix writes the V2C ring past the end of the allocation. (On the GitHub mirror the
frontend half is hw-native-sys/pypto#2269.)

关联的Issue

Fixes #516

Mirrored from GitHub, where this is hw-native-sys/pto-isa#227 against
#226.

测试

Atlas A2/A3, fp32, at the stock ring depth of 4, no DSL overrides, with both halves
applied:

Check	Before	After
Minimal `DIR_BOTH` repro (issue #516), C=16, N ∈ {2,4,5,6,7,8,16} × 3 dispatches	12/21 corrupted	21/21 clean
Same kernel at 4 KiB slots, N ∈ {4,8,16,32}	corrupt at every N and every ring depth (4/8/16/32)	clean
GLA/ZeCO fused forward, C ∈ {16,32} × P ∈ {1,2,4} × N ∈ {2,4,8,16}	5/12 fail at C=16, 6/12 at C=32	24/24 pass, max abs err ≤ 3.1e-5
Downstream regression suites	4 / 3 / 3 pass	4 / 3 / 3 pass

The tpushpop_dir_both ST case passes both before and after: it is a single round trip, so
the data dependency serialises the overwrite behind the read. Exposing the defect needs two
tiles in flight in opposite directions, which needs a loop — hence the repro in the issue.

文档更新

None. The layout this implements is the one already described in the TPUSH/TPOP design note;
no document changes.

类型标签

Bug修复
新特性
性能优化
文档更新
其他，请描述：

Pull Request已成功合入, 合并人@CANN-robot

（感谢 puff_the_magic_dragon 的贡献）

P puff_the_magic_dragon

15 天前创建了 pull request，commit d3c36d33

P puff_the_magic_dragon

15 天前关联了issue：[Bug-Report|缺陷反馈]: A2A3 DIR_BOTH TPipe: the C2V and V2C rings alias the same GM slots

atomgit-bot

15 天前评论：

变更摘要

此 PR 修复了 A2A3 架构下 DIR_BOTH（双向）TPipe 中 C2V 和 V2C 两个环因共享同一 GM 缓冲区基址而互相覆盖数据的 bug。通过在 TPipe 构造函数中为 V2C 环设置 entryOffset（值为 SlotNum * SlotSize），使 C2V 环从偏移 0 开始、V2C 环从 SLOT_NUM * SLOT_SIZE 开始，两者不再重叠。同时更新了双向 ST 测试用例的缓冲区大小分配，使其容纳两个完整的环。

主要改动

TPipe 构造函数新增 V2C 偏移设置：在 include/pto/npu/a2a3/TPush.hpp 的 TPipe 构造函数中，针对 is_both 模式，通过 setEntryOffset 为 V2C 环设置基址偏移量 SlotNum * SlotSize，其中 Cube 端设置 Consumer 偏移、Vector 端设置 Producer 偏移，确保双向传输的两环在 GM 中物理隔离。
双向 ST 测试缓冲区扩容：tests/npu/a2a3/src/st/testcase/tpushpop_dir_both/main.cpp 中 fifoFileSize 从 2 * M * N * sizeof(T) 改为 4 * M * N * sizeof(T)（即 2 * SLOT_NUM * SLOT_SIZE），以匹配现在两个环的实际内存需求，避免 V2C 环写入越界。