Pull Request已成功合入, 合并人@CANN-robot
(感谢 Maksim Vlasov 的贡献)变更摘要
本次 PR 对 PyAsc 基础设施进行了大规模升级,主要涉及:引入 AscendC 寄存器 API 操作族(RegOp、BinaryRegOp、UnaryRegOp 等)及其对应的 IR 定义与 C++ 代码生成;新增 BroadcastOp、LayerNormOp、ReduceOp 族等高阶算子;对接口体系进行重构,新增 OpWithSrcInterface、OpWithReusableSrcInterface、CopyToL0OpInterface 等接口,并将 CopyDirection 从枚举改为结构体属性;同时将 HoistUBAllocation 重命名为 HoistTensorAllocation 并增加 excludeInOut 选项,MaterializeTensorPass 增加 alwaysBuf 选项。Python 侧新增 bfloat16 数据类型、性能分析模块 lib/profiling、KernelMeta/LaunchedKernel 内核元数据类,并添加了 C310 架构的编译支持。
主要改动
-
新增寄存器 API 操作体系:在
include/ascir/Dialect/Asc/IR/Basic/OpReg.td中新增了AddRegOp、MulRegOp、AbsRegOp、ExpRegOp、DataCopyLoadOp、DataCopyStoreOp、UpdateMaskOp、RegTensorOp、CreateMaskOp、SelectRegOp等 30+ 个寄存器级操作定义,并在Base.td中引入了RegOp、BinaryRegOp、UnaryRegOp、VecScalarRegOp基类模板和对应的BinaryRegOpInterface、UnaryRegOpInterface、VecScalarRegOpInterface接口 -
新增高阶算子与类型:新增
BroadcastOp(Broadcast.td)、LayerNormOp(Normalization.td)、ReduceOp族(Reduction.td,含ReduceProdOp、ReduceMinOp、ReduceMaxOp、ReduceSumOp),并增加了LayerNormTiling、LayerNormSeparateTiling、LayerNormPara、LoopModeParams、Dn2NzParams等 API 类型;向量标量运算新增Divs/Subs操作(OpVecBinaryScalar.td) -
接口体系重构:新增
OpWithSrcInterface和OpWithReusableSrcInterface接口,使UnaryOpInterface、BinaryOpInterface、VecScalarOpInterface等统一继承OpWithSrcInterface并实现getSrcTensors()方法;新增CopyToL0OpInterface抽象 L0 拷贝语义;CopyDirection从I32EnumAttr改为AscendC_CopyDirectionAttr结构体属性(含src/dst两个TPosition字段) -
Pass 管线调整与架构支持:
HoistUBAllocation重命名为HoistTensorAllocation,增加excludeInOut选项以区分输入输出张量;MaterializeTensorPass增加alwaysBuf选项;LegalizeKernelArgsPass增加setFftsAddr选项;DetectKernelTypePass重构为按VectorOp/MmadOp检测 kernel 类型并写入asc.kernel_type属性;新增CompilationArch枚举支持 C220/C310 架构,编译器增加vf_vec_len向量寄存器长度配置 -
Python 运行时扩展与新增教程:新增
bfloat16数据类型支持(dtype.py、OpBuilder.cpp中get_bf16_type等);新增lib/profiling性能分析模块(Profiler、MsprofInterface、ProfilingResult);新增KernelMeta、CompiledKernel、LaunchedKernel数据类用于内核生命周期管理;缓存哈希从sha256切换为blake2b;新增三个 Ascend C 教程文件(01-vector-add.py、02-fused-softmax.py、03-matrix-multiplication.py)


PyAsc Infrastructure Changes
This patch introduces modifications to the existing PyAsc infrastructure required by the tile-based programming add-on. Currently, there are no changes in public API or user experience. All existing features remain fully functional, as well as unit and system tests.
1. MLIR Changes
1.1 Asc Dialect — IR
ReducePattern), register-based API (~40 ops for C310: binary, unary, vec-scalar, reduce, utility), LayerNorm, Log2, get_buf/rls_buf (BufId sync for C310), data_copy_nd_dma + NdDmaParams, set_loop_mode_para/reset_loop_mode_para, trans_data_to_5hd_tensor, local_tensor_v3, local_tensor.get_phy_addr_v2.OpWithSrcInterface(get source tensors),OpWithReusableSrcInterface(marker for safe same-op reuse),CopyToL0OpInterface,MicroAPIOpInterface(+ Binary/Unary/VecScalar variants),ReduceOpInterface,BinaryL0OpInterface,BinaryL2OpInterface.OpWithDstInterfacegainedgetDstTensors()default;UnaryOpInterface/BinaryOpInterface/VecScalarOpInterfacenow includeOpWithSrcInterfaceandOpWithReusableSrcInterface; L0/L2 interfaces gained mutable operand accessors andsetIsSetMask.CopyDirectionenum: Replaced with corresponding methodsGlobalToLocal/LocalToGlobal/LocalToLocal/GlobalToGlobal.VectorOpwith src interface, sumTensor/maxTensor made Optional; RmsNorm renamed mnemonic torms_norm, changed toVectorOp; Fixpipe changed toDataCopyOpwith generalized dst type and C310 params support; DataCopyL0/L2 gained src interface; LocalTensorAutoOp gainedpositionattribute; SubIndex ops gained folders (zero-index identity); ReinterpretCastOp fold enhanced to eliminate double-cast chains; MulCast ops moved to BinaryCast templates; VecScalar ops gained Subs and Divs variants; all unary/binary/vec-scalar/math base classes gained defaultgetSrcTensors()/getDstTensors().1.2 Asc Dialect — Passes
HoistUBAllocation→HoistTensorAllocation(addedexclude-in-outoption),InsertSync→InsertQueSync.MaterializeTensor(addedalways-bufoption),LegalizeKernelArgs(addedset-ffts-addroption, conditional on architecture),DetectKernelType(now classifies as "vector"/"cube"/"mixed" instead of binary flag),InsertSync(extended with V_S/S_V event sync for get_value/set_value),InputOutputTensor(handles input-only tensors used for ubuf_gm copy).descriptionfields in TableGen.1.3 EmitAsc Dialect
init_struct(struct initialization with named fields),mask(create bit-by-bit mask pair).mask(2-element i64 array for high/low mask).variable: RemovedPuretrait; added canonicalizer support.InitStructBuilderhelper class.1.4 Code Emitter (Target/AscendC)
arith::NegFOp.CodeEmitter: Added methods for C310 types (CO2Layout, FixpipeParamsC310, RegTensor, MaskReg, NdDmaParams).1.5 Build System & Tools
ConstantOpBuilder: Widened parameter types toint64_t; addedi1()helper.2. Python Changes
2.1 Codegen (
asc/codegen/)FunctionVisitor:CustomBuiltinssupport for injecting custom builtins into the name scope.MatMult(@operator) support.and/or/not) andIfExp: compile-time constant folding before falling back to IR.visit_Call: Handlesast.Starredarguments (*argsunpacking).visit_For: Generalized to accept anyBaseRangesubclass; callshandle_op()on the range object.compute_inout: Materializes initial handles outside the block; acceptsinit_handlesfor if/else merge.visit_If: Else-branch inherits init handles from then-branch.NameScope:builtins→default_builtins; constructor acceptscustom_builtins;inherit()propagates them.Function: Addedcompute_globals()for closure variable resolution; improved AST line number tracking for decorated functions;ConstExprdetection checks runtimeisinstancein addition to annotations.Specialization:PointerArgType.to_ir()switched toget_unranked_memref_type.2.2 Runtime & Compiler (
asc/runtime/)CompilationArchenum (C220/C310),platform_to_arch()mapping, 12 new platforms (Ascend950PR_95xx);set_platform()accepts string values;CompilePlatformenum removed in favor ofCompilationArch.compilation_arch,soc_versionon the module before passes; added-fcce-vf-vlBisheng flag for C310;bisheng_optionstype fixed toTuple[str, ...];opt_leveldefault changed toint = 3; compilation pipeline extended with new pass stages.CompilePrereqsdataclass; kernel handles cached and reused across calls (LaunchedKernel);__getitem__returnsself;compute_globals()used for closures;jit()injectsCustomBuiltins(range=asc_range)by default; 0-dim torch tensors treated as scalars;LaunchOptions.core_numchanged toOptional[int] = None(auto-detect). Cache hash algorithm abstracted viaHashDriverprotocol (default: Blake2b instead of SHA-256).expand_kernel_argshandles torch 0-dim tensors as scalars;core_numauto-detected ifNone;DRY_RUNenv var renamed toPYASC_DRY_RUN; kernel binary handles optionally cached and unregistered after use.2.3 Language Core (
asc/language/core/)bfloat16dtype: Added throughout —DataTyperegex/kind mapping,KnownTypes, exports, builder bindings.IRValue/PlainValue/materialize_ir_value:__bool__raisesTypeErroron IR values;__not__replaced bylogical_not(); addedmax()/min()methods; type inference refactored (bool→int1, int→int_, float→float_).BaseRange/range:BaseRangeextracted as base class withhandle_op()hook;rangeinherits from it.2.4 Pybind11 Bindings (
python/src/)ir.attrsubmodule, bindings for more builtin types (bfloat16, math dialect),clone_shaped_type,TypedAttr,get_splat_attr,get_dict_of_int_attr,ub_block_size; registered math dialect in context.PyOpBuilder(Operation*)constructor; new bindings for bfloat16 type/constants/attrs, bool/i8/i16/f16/f32/f64 attrs, i32/bool array attrs; new arith ops (MaxSI, MinSI, MaximumF, MinimumF, ShLI, ShRSI, generic ConstantOp); full math dialect op bindings.add_hoist_ub_allocationremoved (replaced byadd_hoist_tensor_allocation).2.5 Build System (
setup.py)LLVM_INSTALL_PREFIX.PYASC_SETUP_COMPILER,PYASC_SETUP_LINKER,PYASC_SETUP_CMAKE_APPEND,PYASC_SETUP_JOBSenv vars;PYASC_SETUP_CLANG_LLDnow sets defaults instead of hardcoding.