JJérôme Forissierplat-zynqmp: fixes interrupt controller
| 文件 | 最后提交记录 | 最后更新时间 |
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core: add cxxflags for CPU support Otherwise the compiler is not able to determine the FPU setting from the CPU architecture for cxx files. Signed-off-by: Rouven Czerwinski <r.czerwinski@pengutronix.de> Acked-by: Jerome Forissier <jerome@forissier.org> | 5 年前 | |
core: arm64: SHAKE128 using ARMv8.2-A cryptographic extensions Adds support for SHAKE128 or SHA3-128 sized blocks in sha3_ce_transform(). Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org> Acked-by: Jerome Forissier <jerome.forissier@linaro.org> | 3 年前 | |
dts: stm32: add OTP index for HUK on stm32mp15 platform Add the OTP index on stm32mp15 platform to indicate where to find the previously provisioned HUK. Signed-off-by: Nicolas Toromanoff <nicolas.toromanoff@foss.st.com> Signed-off-by: Thomas BOURGOIN <thomas.bourgoin@foss.st.com> Acked-by: Gatien Chevallier <gatien.chevallier@foss.st.com> Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org> | 3 年前 | |
core: ffa: Allow multiple SPs with same UUID The FF-A spec allows multiple SPs to have the same UUID. This makes it possible to use the FF-A UUID as a identifier for the protocol on top of the FF-A layer. To achieve this we have to make sure that the FFA_PARTITION_INFO_GET can return more then one endpoint id if we pass a UUID. To make sure that there is no collision between the SP binaries names, we distinguish between the FF-A UUID and the SP UUID. The SP UUID is used to identify the SP itself. While the FF-A UUID is used as part of the FF-A protocol. Signed-off-by: Jelle Sels <jelle.sels@arm.com> Acked-by: Jerome Forissier <jerome.forissier@linaro.org> Acked-by: Jens Wiklander <jens.wiklander@linaro.org> | 3 年前 | |
core: ffa: Allow multiple SPs with same UUID The FF-A spec allows multiple SPs to have the same UUID. This makes it possible to use the FF-A UUID as a identifier for the protocol on top of the FF-A layer. To achieve this we have to make sure that the FFA_PARTITION_INFO_GET can return more then one endpoint id if we pass a UUID. To make sure that there is no collision between the SP binaries names, we distinguish between the FF-A UUID and the SP UUID. The SP UUID is used to identify the SP itself. While the FF-A UUID is used as part of the FF-A protocol. Signed-off-by: Jelle Sels <jelle.sels@arm.com> Acked-by: Jerome Forissier <jerome.forissier@linaro.org> Acked-by: Jens Wiklander <jens.wiklander@linaro.org> | 3 年前 | |
core: mm: Fix idx truncation bug When the idx of TA memory mapping is assigned, it is saved in the l1_idx_t, which is the uint8_t or uint16_t type. But when it is parsed, it is saved in uint8_t which can cause truncation. To solve this problem, the idx should be saved in the l1_idx_t type when parsing the idx. Signed-off-by: leisen <leisen1@huawei.com> Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org> Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org> [jf: edit commit description] Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org> | 3 年前 | |
core: arm.mk: set CFG_WITH_LPAE=y when CFG_ARCH64_core=y Since CFG_WITH_LPAE=y is mandatory when CFG_ARCH64_core=y, set it in the common file core/arch/arm/arm.mk instead of leaving it to the platforms. Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org> Acked-by: Jens Wiklander <jens.wiklander@linaro.org> Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org> | 4 年前 | |
plat-aspeed: ast2600: control HACE into Secure World 1. Prohibit non-secure access to HACE controller 2. Grant TEE secure memory access to HACE. Signed-off-by: Neal Liu <neal_liu@aspeedtech.com> Acked-by: Jerome Forissier <jerome.forissier@linaro.org> | 4 年前 | |
core: plat-bcm: remove virtual address lookup from main_init_gic() - Commit 60801696667d ("plat: arm: refactor GIC initialization") refactored GIC initialization to have gic_init_base_addr() take in a physical address instead of a virtual one, meaning that a virtual address lookup is no longer necessary within a platform's gic_init(). - BCM's main_init_gic() would still perform a virtual memory lookup and hand over its virtual address instead of the expected physical one. This caused the lookup in gic_init_base_addr() to fail and panic. - This new commit removes the virtual memory lookup from BCM's main_gic_init() and instead hands gic_init_base_addr() a physical address. Signed-off-by: Andrew Mustea <andrew.mustea@microsoft.com> Acked-by: Jens Wiklander <jens.wiklander@linaro.org> | 4 年前 | |
plat-corstone1000: add corstone1000 platform These changes are to add corstone1000 platform to optee core. arch/arm/plat-vexpress is taken as a reference to make these changes. Signed-off-by: Vishnu Banavath <vishnu.banavath@arm.com> Acked-by: Jerome Forissier <jerome.forissier@linaro.org> Acked-by: Jens Wiklander <jens.wiklander@linaro.org> | 3 年前 | |
core: arm.mk: set CFG_ARM32_core=y when CFG_ARM34_core != y Updates core/arch/arm/arm.mk to assume 32-bit mode when not 64-bit and simplify the platforms conf.mk accordingly. Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org> Acked-by: Jens Wiklander <jens.wiklander@linaro.org> Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org> | 4 年前 | |
drivers: implement lpc_uart driver Support for lpc_uart that is a serial driver. Signed-off-by: Xiaoxu Zeng <zengxiaoxu@huawei.com> Signed-off-by: Zeng Tao <prime.zeng@hisilicon.com> Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org> Acked-by: Jens Wiklander <jens.wiklander@linaro.org> | 3 年前 | |
plat-hikey: Add embedded DTB to define SDP For Hikey, the Secure Data Path memory region definition is done in an embedded dtb as defined in Documentation/devicetree/bindings/reserved-memory/linaro,secure-heap.yaml Signed-off-by: Olivier Masse <olivier.masse@nxp.com> Acked-by: Etienne Carriere <etienne.carriere@linaro.org> Acked-by: Jerome Forissier <jerome.forissier@linaro.org> | 4 年前 | |
core_mmu: fix phys_to_virt() to check length phys_to_virt() function without length parameter doesn t always have ability to find the correct mapping for requested physical address. This is because physical address can be mapped in the same time in different virtual regions with different length. So the first found region which contains the requested physical address possibly doesnt have enough mapped data. This is fixed by adding the length parameter to phys_to_virt() function. Length parameter can be set to 1 if caller knows that requested (pa + len) doesn`t cross mapping granule boundary. core_mmu_get_va() and io_pa_or_va() functions now are take length parameter too as they based on phys_to_virt() in case of MMU enabled. Signed-off-by: Anton Rybakov <a.rybakov@omp.ru> Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org> Acked-by: Etienne Carriere <etienne.carriere@linaro.org> Tested-by: Etienne Carriere <etienne.carriere@linaro.org> (stm32mp1-157C_DK2) Tested-by: Clement Faure <clement.faure@nxp.com> (imx-mx6dlsabreauto) Tested-by: Clement Faure <clement.faure@nxp.com> (imx-mx6dlsabresd) Tested-by: Clement Faure <clement.faure@nxp.com> (imx-mx6qpsabreauto) Tested-by: Clement Faure <clement.faure@nxp.com> (imx-mx6sllevk) Tested-by: Clement Faure <clement.faure@nxp.com> (imx-mx6ulevk) Tested-by: Clement Faure <clement.faure@nxp.com> (imx-mx6ullevk) Tested-by: Clement Faure <clement.faure@nxp.com> (imx-mx6ulzevk) Tested-by: Clement Faure <clement.faure@nxp.com> (imx-mx7dsabresd) Tested-by: Clement Faure <clement.faure@nxp.com> (imx-mx7ulpevk) Tested-by: Clement Faure <clement.faure@nxp.com> (imx-mx8mmevk) Tested-by: Clement Faure <clement.faure@nxp.com> (imx-mx8mnevk) Tested-by: Clement Faure <clement.faure@nxp.com> (imx-mx8mqevk) Tested-by: Clement Faure <clement.faure@nxp.com> (imx-mx8mpevk) Tested-by: Clement Faure <clement.faure@nxp.com> (imx-mx8qmmek) Tested-by: Clement Faure <clement.faure@nxp.com> (imx-mx8qxpmek) | 4 年前 | |
core: imx: remove duplicate driver_init() call Remove duplicated call to driver_init(). The previous driver_init() call would only initialize the driver. The new driver_init() call initializes the driver and its power management callback. Fixes: 97eb916803fe ("drivers: imx: tzc380: re-configure TZ380 upon PM resume") Signed-off-by: Clement Faure <clement.faure@nxp.com> Acked-by: Jerome Forissier <jerome.forissier@linaro.org> Acked-by: Jens Wiklander <jens.wiklander@linaro.org> | 3 年前 | |
plat-k3: remove duplicate comments Removing duplicated comments in the existing as well as newly added functions. Signed-off-by: Manorit Chawdhry <m-chawdhry@ti.com> Acked-by: Etienne Carriere <etienne.carriere@linaro.org> | 3 年前 | |
core: arm: link.mk: produce tee-raw.bin by default Adds tee-raw.bin as a dependency of all. This produces a tee-raw.bin for all platforms when building. tee-raw.bin is more useful than for instance tee-pager_v2.bin which often is used when a raw binary is needed. Platforms with a link.mk only to produce tee-raw.bin have their link.mk removed since the generic version suffices now. Acked-by: Clement Faure <clement.faure@nxp.com> Acked-by: Jerome Forissier <jerome.forissier@linaro.org> Acked-by: Ilias Apalodimas <ilias.apalodimas@linaro.org> Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org> | 3 年前 | |
core: arm.mk: set CFG_ARM32_core=y when CFG_ARM34_core != y Updates core/arch/arm/arm.mk to assume 32-bit mode when not 64-bit and simplify the platforms conf.mk accordingly. Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org> Acked-by: Jens Wiklander <jens.wiklander@linaro.org> Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org> | 4 年前 | |
plat-mediatek: add support for MT8195 SoC Add OP-TEE support for the MT8195 SoC. Acked-by: Jens Wiklander <jens.wiklander@linaro.org> Acked-by: Etienne Carriere <etienne.carriere@linaro.org> Signed-off-by: Fabien Parent <fparent@baylibre.com> Signed-off-by: Ricardo Salveti <ricardo@foundries.io> | 3 年前 | |
core: arm.mk: set CFG_ARM32_core=y when CFG_ARM34_core != y Updates core/arch/arm/arm.mk to assume 32-bit mode when not 64-bit and simplify the platforms conf.mk accordingly. Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org> Acked-by: Jens Wiklander <jens.wiklander@linaro.org> Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org> | 4 年前 | |
plat: rcar: fix core pos calculation for H3 boards Due to mistake, cluster position wasn't shifted left if chip is not M3W. This led to erroneous core ID calculation on chips that are not M3W. Actually, this affected only H3, as only this chip has two clusters. Fix this by always shifting x1 (cluster ID) to the left, before doing one additional shift for non-M3W chips. Fixes: 572afdce53ea ("plat: rcar: Derive core map from PRR") Reported-by: Oleksandr Grytsov <oleksandr_grytsov@epam.com> Tested-by: Volodymyr Babchuk <volodymyr_babchuk@epam.com> (R-Car M3) Tested-by: Oleksandr Grytsov <oleksandr_grytsov@epam.com> (R-Car H3) Signed-off-by: Volodymyr Babchuk <volodymyr_babchuk@epam.com> Acked-by: Jerome Forissier <jerome.forissier@linaro.org> | 3 年前 | |
plat-rockchip: rk3399: set CFG_CRYPTO_WITH_CE ?= y Enables Arm Cryptography Extensions by default for the rk3399 SoC since they are supported [1]. Link: [1] http://opensource.rock-chips.com/images/d/d7/Rockchip_RK3399_Datasheet_V2.1-20200323.pdf Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org> Acked-by: Jens Wiklander <jens.wiklander@linaro.org> | 4 年前 | |
core: arm.mk: set CFG_ARM32_core=y when CFG_ARM34_core != y Updates core/arch/arm/arm.mk to assume 32-bit mode when not 64-bit and simplify the platforms conf.mk accordingly. Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org> Acked-by: Jens Wiklander <jens.wiklander@linaro.org> Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org> | 4 年前 | |
core: arm.mk: set CFG_ARM32_core=y when CFG_ARM34_core != y Updates core/arch/arm/arm.mk to assume 32-bit mode when not 64-bit and simplify the platforms conf.mk accordingly. Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org> Acked-by: Jens Wiklander <jens.wiklander@linaro.org> Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org> | 4 年前 | |
core: arm: link.mk: produce tee-raw.bin by default Adds tee-raw.bin as a dependency of all. This produces a tee-raw.bin for all platforms when building. tee-raw.bin is more useful than for instance tee-pager_v2.bin which often is used when a raw binary is needed. Platforms with a link.mk only to produce tee-raw.bin have their link.mk removed since the generic version suffices now. Acked-by: Clement Faure <clement.faure@nxp.com> Acked-by: Jerome Forissier <jerome.forissier@linaro.org> Acked-by: Ilias Apalodimas <ilias.apalodimas@linaro.org> Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org> | 3 年前 | |
plat-sam: matrix: add matrix_dt_get_id() to parse matrix id from dt Rather than using hardcoded values for matrix identifier in drivers themselves, (which might change in future hardware SoC), add matrix_dt_get_id() function which allows to retrieve the ID based on a devite-tree node reg property. This property contains the address of the peripheral and thus can be used to match the address with an identifier. This is also useful for peripheral which have multiple instances and thus id is not the same for all of them. Signed-off-by: Clément Léger <clement.leger@bootlin.com> Acked-by: Jerome Forissier <jerome.forissier@linaro.org> | 3 年前 | |
core: arm.mk: set CFG_ARM32_core=y when CFG_ARM34_core != y Updates core/arch/arm/arm.mk to assume 32-bit mode when not 64-bit and simplify the platforms conf.mk accordingly. Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org> Acked-by: Jens Wiklander <jens.wiklander@linaro.org> Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org> | 4 年前 | |
drivers: struct serial_ops: make all functions optional except putc() Many platforms only use the putc() function pointer in struct serial_ops. Therefore, explicitly make the others optional (flush(), have_rx_data() and getchar()) by adding comments to the struct and making sure the code checks the pointer before using them. With this it should be clear that drivers do not need to provide stub functions. Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org> Acked-by: Jens Wiklander <jens.wiklander@linaro.org> Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org> | 3 年前 | |
drivers: stm32mp15_huk: use DT HUK NVMEM layout API Adds the possibility to get the HUK from OTP definition in the device tree using the function stm32_bsec_find_otp_in_nvmem_layout(). Signed-off-by: Thomas BOURGOIN <thomas.bourgoin@foss.st.com> Acked-by: Gatien Chevallier <gatien.chevallier@foss.st.com> Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org> | 3 年前 | |
core: arm.mk: set CFG_WITH_LPAE=y when CFG_ARCH64_core=y Since CFG_WITH_LPAE=y is mandatory when CFG_ARCH64_core=y, set it in the common file core/arch/arm/arm.mk instead of leaving it to the platforms. Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org> Acked-by: Jens Wiklander <jens.wiklander@linaro.org> Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org> | 4 年前 | |
plat-synquacer: rename rng_pta.h to synquacer_rng_pta.h Renames plat-synquacer rng_pta.h to synquacer_rng_pta.h to prevent confusion with generic RNG PTA header file pta_rng.h. Acked-by: Jerome Forissier <jerome.forissier@linaro.org> Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org> | 4 年前 | |
plat-ti: Remove extra license text as we have SPDX No functional change here. Signed-off-by: Andrew Davis <afd@ti.com> Acked-by: Jerome Forissier <jerome.forissier@linaro.org> | 4 年前 | |
plat-totalcompute: remap console logs Remapping console logs from soc uart1 (s0 termial) to css secure (uart1_ap terminal) Signed-off-by: Annam Sai Manisha <annam.saimanisha@arm.com> Acked-by: Jens Wiklander <jens.wiklander@linaro.org> | 3 年前 | |
core: arm: link.mk: produce tee-raw.bin by default Adds tee-raw.bin as a dependency of all. This produces a tee-raw.bin for all platforms when building. tee-raw.bin is more useful than for instance tee-pager_v2.bin which often is used when a raw binary is needed. Platforms with a link.mk only to produce tee-raw.bin have their link.mk removed since the generic version suffices now. Acked-by: Clement Faure <clement.faure@nxp.com> Acked-by: Jerome Forissier <jerome.forissier@linaro.org> Acked-by: Ilias Apalodimas <ilias.apalodimas@linaro.org> Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org> | 3 年前 | |
core: arm: link.mk: produce tee-raw.bin by default Adds tee-raw.bin as a dependency of all. This produces a tee-raw.bin for all platforms when building. tee-raw.bin is more useful than for instance tee-pager_v2.bin which often is used when a raw binary is needed. Platforms with a link.mk only to produce tee-raw.bin have their link.mk removed since the generic version suffices now. Acked-by: Clement Faure <clement.faure@nxp.com> Acked-by: Jerome Forissier <jerome.forissier@linaro.org> Acked-by: Ilias Apalodimas <ilias.apalodimas@linaro.org> Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org> | 3 年前 | |
plat-vexpress: enable CFG_PCKS11_TA by default Enable the PKCS#11 TA in plat-vexpress for easier testing (such as in CI). With this, the PKCS#11 in-tree TA is built with optee_os and CFG_PKCS11_TA is exported in the host_include folder of the TA dev kit (host_include/conf.{mk,h,cmake}) where optee_test will find it and also enable the PKCS#11 tests. Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org> Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org> | 3 年前 | |
plat-zynq7k: Configure platform needing NMFI workaround Unfortunately Xilinx Zynq-7000's ARM Cortext-A9 core has been configured with NMFI support. This causes problems for OP-TEE's atomic context protections rendering FIQ interrupt un-usable in the system designs. Signed-off-by: Vesa Jääskeläinen <vesa.jaaskelainen@vaisala.com> Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org> Acked-by: Etienne Carriere <etienne.carriere@linaro.org> Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org> | 3 年前 | |
plat-zynqmp: fixes interrupt controller Updates GICC_OFFSET to account for the already-offset GIC_BASE. Additionally initializes the interrupt controller with a pointer to the interrupt chip. Signed-off-by: Zachary Clark <zach.clark@dornerworks.com> Reviewed-by: Ricardo Salveti <ricardo@foundries.io> | 3 年前 | |
arm32: sm: Apply FIQ workaround if configured On systems with Non-maskable FIQ (NMFI) support in OP-TEE's atomic contexts when trying to mask FIQ it cannot be set leaving it non-masked. This state is then carried back into sm_ctx structure thus causing next call to SMC entry having incorrect FIQ masking configured. This can represent itself as: E/TC:0 assertion 'thread_get_exceptions() == THREAD_EXCP_ALL' failed at core/arch/arm/kernel/thread_optee_smc.c:50 <thread_handle_fast_smc> As a workaround force FIQ to be masked before entering SMC entry handler. Note: on systems having the issue -- FIQ is considered un-usable and causes panic in OP-TEE if received. Note2: If you have system without SCTLR.NMFI enabled and you do get that assertion do not enable the workaround! Eg. fix the real problem. Signed-off-by: Vesa Jääskeläinen <vesa.jaaskelainen@vaisala.com> Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org> Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org> | 3 年前 | |
virt: rename CFG_VIRTUALIZATION to CFG_NS_VIRTUALIZATION With the advent of virtualization support at S-EL2 in the Armv8.4-A architecture, CFG_VIRTUALIZATION has become ambiguous. Let's rename it to CFG_NS_VIRTUALIZATION to indicate more clearly that it is about supporting virtualization on the non-secure side. This commit is the result of the following command: $ for f in $(git grep -l -w CFG_VIRTUALIZATION); do \ sed -i -e 's/CFG_VIRTUALIZATION/CFG_NS_VIRTUALIZATION/g' $f; \ done ...plus the compatibility line in mk/config.mk: CFG_NS_VIRTUALIZATION ?= $(CFG_VIRTUALIZATION) Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org> Acked-by: Jens Wiklander <jens.wiklander@linaro.org> Acked-by: Etienne Carriere <etienne.carriere@linaro.org> Acked-by: Volodymyr Babchuk <volodymyr_babchuk@epam.com> | 3 年前 | |
core: add driver for hafnium interrupt controller Adds a driver for the paravirtualized interrupt controller provided by Hafnium at S-EL2. The driver is enabled with CFG_CORE_HAFNIUM_INTC=y. The interrupt controller is limited compared to the GIC and only works with interrupt ids which are already added in the SP manifest or as predefined reserved interrupt ids. Acked-by: Jerome Forissier <jerome.forissier@linaro.org> Acked-by: Etienne Carriere <etienne.carriere@linaro.org> Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org> | 3 年前 |