JJérôme Forissiercore: riscv: provide arch_scall.h
| 文件 | 最后提交记录 | 最后更新时间 |
|---|---|---|
core: riscv: provide arch_scall.h Specifies what registers from thread_scall_regs are used for system calls. The syscall number is provided in t0 register. The syscall max args is provided in t1 register. The return value is provided in a0 register. The panic and panic code are provided respectively in a1 and a2 registers. Signed-off-by: Marouene Boubakri <marouene.boubakri@nxp.com> Acked-by: Jens Wiklander <jens.wiklander@linaro.org> | 3 年前 | |
riscv: include: add core_mmu_arch.h Add defines for MMU configuration and helper functions. Signed-off-by: Marouene Boubakri <marouene.boubakri@nxp.com> Acked-by: Etienne Carriere <etienne.carriere@linaro.org> | 3 年前 | |
core: riscv: define RISC-V instruction set architecture in encoding.h Define standard RISC-V instruction opcodes, control and status registers. This file is auto-generated from riscv-opcodes and it is subject of regular updates. Signed-off-by: Marouene Boubakri <marouene.boubakri@nxp.com> Acked-by: Etienne Carriere <etienne.carriere@linaro.org> Acked-by: Jerome Forissier <jerome.forissier@linaro.org> | 3 年前 | |
core: riscv: riscv.h: bind registers to their ABI names For better readability of code, allow using register ABI names in ASM sources to match registers declarations in C files. Signed-off-by: Marouene Boubakri <marouene.boubakri@nxp.com> Acked-by: Jens Wiklander <jens.wiklander@linaro.org> | 3 年前 | |
core: riscv: riscv_macros.S: add load_xregs and save_xregs macros Introduce helper macros to load/store a range registers from/to a base register at a given offset. It uses LDR and STR macros defined in riscv.h for respectively RV32 and RV64. Offsets are shifted by RISCV_XLEN_BYTES. Signed-off-by: Marouene Boubakri <marouene.boubakri@nxp.com> Acked-by: Jens Wiklander <jens.wiklander@linaro.org> | 3 年前 | |
riscv: kernel: sbi: add RISC-V SBI interface Allow OP-TEE core running in S-Mode (supervisor) to interface with Supervisor Execution Environment (SEE) through environmental calls (ecall). Adds CFG_RISCV_SBI flag to enable or disable it. Signed-off-by: Marouene Boubakri <marouene.boubakri@nxp.com> Acked-by: Jerome Forissier <jerome.forissier@linaro.org> Acked-by: Jens Wiklander <jens.wiklander@linaro.org> [jf: set author to be same as Signed-off-by:] Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org> | 3 年前 | |
core: riscv: define RISC-V instruction set architecture in encoding.h Define standard RISC-V instruction opcodes, control and status registers. This file is auto-generated from riscv-opcodes and it is subject of regular updates. Signed-off-by: Marouene Boubakri <marouene.boubakri@nxp.com> Acked-by: Etienne Carriere <etienne.carriere@linaro.org> Acked-by: Jerome Forissier <jerome.forissier@linaro.org> | 3 年前 |