* arch/arm/src/sam34/sam_emac.c
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <inttypes.h>
#include <stdint.h>
#include <stdbool.h>
#include <time.h>
#include <string.h>
#include <assert.h>
#include <debug.h>
#include <errno.h>
#include <arpa/inet.h>
#include <nuttx/arch.h>
#include <nuttx/wdog.h>
#include <nuttx/kmalloc.h>
#include <nuttx/wqueue.h>
#include <nuttx/spinlock.h>
#include <nuttx/net/mii.h>
#include <nuttx/net/ip.h>
#include <nuttx/net/netdev.h>
#include <nuttx/net/phy.h>
#ifdef CONFIG_NET_PKT
# include <nuttx/net/pkt.h>
#endif
#include "arm_internal.h"
#include "chip.h"
#include "hardware/sam_pinmap.h"
#include "sam_gpio.h"
#include "sam_periphclks.h"
#include "sam_cmcc.h"
#include "sam_emac.h"
#include <arch/board/board.h>
#if defined(CONFIG_NET) && defined(CONFIG_SAM34_EMAC)
* Pre-processor Definitions
****************************************************************************/
* is required.
*/
#if !defined(CONFIG_SCHED_WORKQUEUE)
# error Work queue support is required
#endif
* will be the same as HPWORK.
*
* NOTE: However, the network should NEVER run on the high priority work
* queue! That queue is intended only to service short back end interrupt
* processing that never suspends. Suspending the high priority work queue
* may bring the system to its knees!
*/
#define ETHWORK LPWORK
#ifndef CONFIG_SAM34_EMAC_NRXBUFFERS
# define CONFIG_SAM34_EMAC_NRXBUFFERS 16
#endif
#ifndef CONFIG_SAM34_EMAC_NTXBUFFERS
# define CONFIG_SAM34_EMAC_NTXBUFFERS 8
#endif
#undef CONFIG_SAM34_EMAC_NBC
#ifndef CONFIG_SAM34_EMAC_PHYADDR
# error "CONFIG_SAM34_EMAC_PHYADDR must be defined in the NuttX configuration"
#endif
#if !defined(CONFIG_SAM34_EMAC_MII) && !defined(CONFIG_SAM34_EMAC_RMII)
# warning "Neither CONFIG_SAM34_EMAC_MII nor CONFIG_SAM34_EMAC_RMII defined"
#endif
#if defined(CONFIG_SAM34_EMAC_MII) && defined(CONFIG_SAM34_EMAC_RMII)
# error "Both CONFIG_SAM34_EMAC_MII and CONFIG_SAM34_EMAC_RMII defined"
#endif
#ifdef CONFIG_SAM34_EMAC_AUTONEG
# ifndef CONFIG_SAM34_EMAC_PHYSR
# error "CONFIG_SAM34_EMAC_PHYSR must be defined in the NuttX configuration"
# endif
# ifdef CONFIG_SAM34_EMAC_PHYSR_ALTCONFIG
# ifndef CONFIG_SAM34_EMAC_PHYSR_ALTMODE
# error "CONFIG_SAM34_EMAC_PHYSR_ALTMODE must be defined in the NuttX configuration"
# endif
# ifndef CONFIG_SAM34_EMAC_PHYSR_10HD
# error "CONFIG_SAM34_EMAC_PHYSR_10HD must be defined in the NuttX configuration"
# endif
# ifndef CONFIG_SAM34_EMAC_PHYSR_100HD
# error "CONFIG_SAM34_EMAC_PHYSR_100HD must be defined in the NuttX configuration"
# endif
# ifndef CONFIG_SAM34_EMAC_PHYSR_10FD
# error "CONFIG_SAM34_EMAC_PHYSR_10FD must be defined in the NuttX configuration"
# endif
# ifndef CONFIG_SAM34_EMAC_PHYSR_100FD
# error "CONFIG_SAM34_EMAC_PHYSR_100FD must be defined in the NuttX configuration"
# endif
# else
# ifndef CONFIG_SAM34_EMAC_PHYSR_SPEED
# error "CONFIG_SAM34_EMAC_PHYSR_SPEED must be defined in the NuttX configuration"
# endif
# ifndef CONFIG_SAM34_EMAC_PHYSR_100MBPS
# error "CONFIG_SAM34_EMAC_PHYSR_100MBPS must be defined in the NuttX configuration"
# endif
# ifndef CONFIG_SAM34_EMAC_PHYSR_MODE
# error "CONFIG_SAM34_EMAC_PHYSR_MODE must be defined in the NuttX configuration"
# endif
# ifndef CONFIG_SAM34_EMAC_PHYSR_FULLDUPLEX
# error "CONFIG_SAM34_EMAC_PHYSR_FULLDUPLEX must be defined in the NuttX configuration"
# endif
# endif
#endif
#if defined(CONFIG_ETH0_PHY_DM9161)
# define MII_OUI_MSB 0x0181
# define MII_OUI_LSB 0x2e
#elif defined(CONFIG_ETH0_PHY_LAN8700)
# define MII_OUI_MSB 0x0007
# define MII_OUI_LSB 0x30
#elif defined(CONFIG_ETH0_PHY_KSZ8051)
# define MII_OUI_MSB 0x0022
# define MII_OUI_LSB 0x05
#else
# error EMAC PHY unrecognized
#endif
#ifdef CONFIG_SAM34_EMAC_PHYSR_ALTCONFIG
# define PHYSR_MODE(sr) ((sr) & CONFIG_SAM34_EMAC_PHYSR_ALTMODE)
# define PHYSR_ISMODE(sr,m) (PHYSR_MODE(sr) == (m))
# define PHYSR_IS10HDX(sr) PHYSR_ISMODE(sr,CONFIG_SAM34_EMAC_PHYSR_10HD)
# define PHYSR_IS100HDX(sr) PHYSR_ISMODE(sr,CONFIG_SAM34_EMAC_PHYSR_100HD)
# define PHYSR_IS10FDX(sr) PHYSR_ISMODE(sr,CONFIG_SAM34_EMAC_PHYSR_10FD)
# define PHYSR_IS100FDX(sr) PHYSR_ISMODE(sr,CONFIG_SAM34_EMAC_PHYSR_100FD)
#else
# define PHYSR_MODESPEED (CONFIG_PHYSR_MODE | CONFIG_PHYSR_SPEED)
# define PHYSR_10HDX (0)
# define PHYSR_100HDX (CONFIG_PHYSR_100MBPS)
# define PHYSR_10FDX (CONFIG_PHYSR_FULLDUPLEX)
# define PHYSR_100FDX (CONFIG_PHYSR_FULLDUPLEX | CONFIG_PHYSR_100MBPS)
# define PHYSR_IS10HDX(sr) (((sr) & PHYSR_MODESPEED) == PHYSR_10HDX)
# define PHYSR_IS100HDX(sr) (((sr) & PHYSR_MODESPEED) == PHYSR_100HDX)
# define PHYSR_IS10FDX(sr) (((sr) & PHYSR_MODESPEED) == PHYSR_10FDX)
# define PHYSR_IS100FDX(sr) (((sr) & PHYSR_MODESPEED) == PHYSR_100FDX)
#endif
#define EMAC_RX_UNITSIZE 128
#define EMAC_TX_UNITSIZE CONFIG_NET_ETH_PKTSIZE
#define SAM_EMAC_NFREEBUFFERS (CONFIG_SAM34_EMAC_NTXBUFFERS+1)
* enabled.
*/
#ifndef CONFIG_DEBUG_NET_INFO
# undef CONFIG_SAM34_EMAC_REGDEBUG
#endif
#ifdef CONFIG_NET_DUMPPACKET
# define sam_dumppacket(m,a,n) lib_dumpbuffer(m,a,n)
#else
# define sam_dumppacket(m,a,n)
#endif
#define SAM_TXTIMEOUT (60*CLK_TCK)
#define PHY_RETRY_MAX 1000000
* header
*/
#define BUF ((struct eth_hdr_s *)priv->dev.d_buf)
* Private Types
****************************************************************************/
struct sam_emac_s
{
uint8_t ifup : 1;
struct wdog_s txtimeout;
struct work_s irqwork;
struct work_s pollwork;
struct net_driver_s dev;
uint8_t phyaddr;
uint16_t txhead;
uint16_t txtail;
uint16_t rxndx;
uint8_t *rxbuffer;
uint8_t *txbuffer;
struct emac_rxdesc_s *rxdesc;
struct emac_txdesc_s *txdesc;
#ifdef CONFIG_SAM34_EMAC_REGDEBUG
bool wrlast;
uintptr_t addrlast;
uint32_t vallast;
int ntimes;
#endif
};
* Private Data
****************************************************************************/
static struct sam_emac_s g_emac;
*
* REVISIT: It might be possible to use this option to send and receive
* messages directly into the DMA buffers, saving a copy. There might be
* complications on the receiving side, however, where buffers may wrap
* and where the size of the received frame will typically be smaller than
* a full packet.
*/
static uint8_t g_pktbuf[MAX_NETDEV_PKTSIZE + CONFIG_NET_GUARDSIZE];
#ifdef CONFIG_SAM34_EMAC_PREALLOCATE
static struct emac_txdesc_s g_txdesc[CONFIG_SAM34_EMAC_NTXBUFFERS]
aligned_data(8);
static struct emac_rxdesc_s g_rxdesc[CONFIG_SAM34_EMAC_NRXBUFFERS]
aligned_data(8);
*
* Section 3.6 of AMBA 2.0 spec states that burst should not cross 1K
* Boundaries. Receive buffer manager writes are burst of 2 words => 3
* lsb bits of the address shall be set to 0
*/
static uint8_t g_txbuffer[CONFIG_SAM34_EMAC_NTXBUFFERS * EMAC_TX_UNITSIZE]
aligned_data(8);
static uint8_t g_rxbuffer[CONFIG_SAM34_EMAC_NRXBUFFERS * EMAC_RX_UNITSIZE]
aligned_data(8);
#endif
* Private Function Prototypes
****************************************************************************/
#if defined(CONFIG_SAM34_EMAC_REGDEBUG) && defined(CONFIG_DEBUG_FEATURES)
static bool sam_checkreg(struct sam_emac_s *priv, bool wr,
uint32_t regval, uintptr_t address);
static uint32_t sam_getreg(struct sam_emac_s *priv, uintptr_t addr);
static void sam_putreg(struct sam_emac_s *priv,
uintptr_t addr, uint32_t val);
#else
# define sam_getreg(priv,addr) getreg32(addr)
# define sam_putreg(priv,addr,val) putreg32(val,addr)
#endif
static uint16_t sam_txinuse(struct sam_emac_s *priv);
static uint16_t sam_txfree(struct sam_emac_s *priv);
static int sam_buffer_initialize(struct sam_emac_s *priv);
static void sam_buffer_free(struct sam_emac_s *priv);
static int sam_transmit(struct sam_emac_s *priv);
static int sam_txpoll(struct net_driver_s *dev);
static void sam_dopoll(struct sam_emac_s *priv);
static int sam_recvframe(struct sam_emac_s *priv);
static void sam_receive(struct sam_emac_s *priv);
static void sam_txdone(struct sam_emac_s *priv);
static void sam_interrupt_work(void *arg);
static int sam_emac_interrupt(int irq, void *context, void *arg);
static void sam_txtimeout_work(void *arg);
static void sam_txtimeout_expiry(wdparm_t arg);
static int sam_ifup(struct net_driver_s *dev);
static int sam_ifdown(struct net_driver_s *dev);
static void sam_txavail_work(void *arg);
static int sam_txavail(struct net_driver_s *dev);
#if defined(CONFIG_NET_MCASTGROUP) || defined(CONFIG_NET_ICMPv6)
static unsigned int sam_hashindx(const uint8_t *mac);
static int sam_addmac(struct net_driver_s *dev, const uint8_t *mac);
#endif
#ifdef CONFIG_NET_MCASTGROUP
static int sam_rmmac(struct net_driver_s *dev, const uint8_t *mac);
#endif
#ifdef CONFIG_NETDEV_IOCTL
static int sam_ioctl(struct net_driver_s *dev, int cmd, unsigned long arg);
#endif
#if defined(CONFIG_DEBUG_NET) && defined(CONFIG_DEBUG_INFO)
static void sam_phydump(struct sam_emac_s *priv);
#else
# define sam_phydump(priv)
#endif
#if defined(CONFIG_NETDEV_PHY_IOCTL) && defined(CONFIG_ARCH_PHY_INTERRUPT)
static int sam_phyintenable(struct sam_emac_s *priv);
#endif
static int sam_phywait(struct sam_emac_s *priv);
static int sam_phyreset(struct sam_emac_s *priv);
static int sam_phyfind(struct sam_emac_s *priv, uint8_t *phyaddr);
static int sam_phyread(struct sam_emac_s *priv, uint8_t phyaddr,
uint8_t regaddr, uint16_t *phyval);
static int sam_phywrite(struct sam_emac_s *priv, uint8_t phyaddr,
uint8_t regaddr, uint16_t phyval);
static int sam_autonegotiate(struct sam_emac_s *priv);
static bool sam_linkup(struct sam_emac_s *priv);
static int sam_phyinit(struct sam_emac_s *priv);
static void sam_txreset(struct sam_emac_s *priv);
static void sam_rxreset(struct sam_emac_s *priv);
static void sam_emac_reset(struct sam_emac_s *priv);
static void sam_macaddress(struct sam_emac_s *priv);
static int sam_emac_configure(struct sam_emac_s *priv);
* Private Functions
****************************************************************************/
* Name: sam_checkreg
*
* Description:
* Check if the current register access is a duplicate of the preceding.
*
* Input Parameters:
* regval - The value to be written
* address - The address of the register to write to
*
* Returned Value:
* true: This is the first register access of this type.
* flase: This is the same as the preceding register access.
*
****************************************************************************/
#ifdef CONFIG_SAM34_EMAC_REGDEBUG
static bool sam_checkreg(struct sam_emac_s *priv, bool wr, uint32_t regval,
uintptr_t address)
{
if (wr == priv->wrlast &&
regval == priv->vallast &&
address == priv->addrlast)
{
priv->ntimes++;
return false;
}
else
{
if (priv->ntimes > 0)
{
ninfo("...[Repeats %d times]...\n", priv->ntimes);
}
priv->wrlast = wr;
priv->vallast = regval;
priv->addrlast = address;
priv->ntimes = 0;
}
return true;
}
#endif
* Name: sam_getreg
*
* Description:
* Read any 32-bit register using an absolute
*
****************************************************************************/
#ifdef CONFIG_SAM34_EMAC_REGDEBUG
static uint32_t sam_getreg(struct sam_emac_s *priv, uintptr_t address)
{
uint32_t regval = getreg32(address);
if (sam_checkreg(priv, false, regval, address))
{
ninfo("%08x->%08x\n", address, regval);
}
return regval;
}
#endif
* Name: sam_putreg
*
* Description:
* Write to any 32-bit register using an absolute address
*
****************************************************************************/
#ifdef CONFIG_SAM34_EMAC_REGDEBUG
static void sam_putreg(struct sam_emac_s *priv,
uintptr_t address, uint32_t regval)
{
if (sam_checkreg(priv, true, regval, address))
{
ninfo("%08x<-%08x\n", address, regval);
}
putreg32(regval, address);
}
#endif
* Function: sam_txinuse
*
* Description:
* Return the number of TX buffers in-use
*
* Input Parameters:
* priv - The EMAC driver state
*
* Returned Value:
* The number of TX buffers in-use
*
****************************************************************************/
static uint16_t sam_txinuse(struct sam_emac_s *priv)
{
uint32_t txhead32 = (uint32_t)priv->txhead;
if ((uint32_t)priv->txtail > txhead32)
{
txhead32 += CONFIG_SAM34_EMAC_NTXBUFFERS;
}
return (uint16_t)(txhead32 - (uint32_t)priv->txtail);
}
* Function: sam_txfree
*
* Description:
* Return the number of TX buffers available
*
* Input Parameters:
* priv - The EMAC driver state
*
* Returned Value:
* The number of TX buffers available
*
****************************************************************************/
static uint16_t sam_txfree(struct sam_emac_s *priv)
{
* number of buffers in use. Notice that that actual number of buffers is
* the configured size minus 1.
*/
return (CONFIG_SAM34_EMAC_NTXBUFFERS - 1) - sam_txinuse(priv);
}
* Function: sam_buffer_initialize
*
* Description:
* Allocate aligned TX and RX descriptors and buffers. For the case of
* pre-allocated structures, the function degenerates to a few assignments.
*
* Input Parameters:
* priv - The EMAC driver state
*
* Returned Value:
* OK on success; Negated errno on failure.
*
* Assumptions:
* Called very early in the initialization sequence.
*
****************************************************************************/
static int sam_buffer_initialize(struct sam_emac_s *priv)
{
#ifdef CONFIG_SAM34_EMAC_PREALLOCATE
priv->txdesc = g_txdesc;
priv->rxdesc = g_rxdesc;
priv->txbuffer = g_txbuffer;
priv->rxbuffer = g_rxbuffer;
#else
size_t allocsize;
allocsize = CONFIG_SAM34_EMAC_NTXBUFFERS * sizeof(struct emac_txdesc_s);
priv->txdesc = kmm_memalign(8, allocsize);
if (!priv->txdesc)
{
nerr("ERROR: Failed to allocate TX descriptors\n");
return -ENOMEM;
}
memset(priv->txdesc, 0, allocsize);
allocsize = CONFIG_SAM34_EMAC_NRXBUFFERS * sizeof(struct emac_rxdesc_s);
priv->rxdesc = kmm_memalign(8, allocsize);
if (!priv->rxdesc)
{
nerr("ERROR: Failed to allocate RX descriptors\n");
sam_buffer_free(priv);
return -ENOMEM;
}
memset(priv->rxdesc, 0, allocsize);
allocsize = CONFIG_SAM34_EMAC_NTXBUFFERS * EMAC_TX_UNITSIZE;
priv->txbuffer = kmm_memalign(8, allocsize);
if (!priv->txbuffer)
{
nerr("ERROR: Failed to allocate TX buffer\n");
sam_buffer_free(priv);
return -ENOMEM;
}
allocsize = CONFIG_SAM34_EMAC_NRXBUFFERS * EMAC_RX_UNITSIZE;
priv->rxbuffer = kmm_memalign(8, allocsize);
if (!priv->rxbuffer)
{
nerr("ERROR: Failed to allocate RX buffer\n");
sam_buffer_free(priv);
return -ENOMEM;
}
#endif
DEBUGASSERT(((uintptr_t)priv->rxdesc & 7) == 0 &&
((uintptr_t)priv->rxbuffer & 7) == 0 &&
((uintptr_t)priv->txdesc & 7) == 0 &&
((uintptr_t)priv->txbuffer & 7) == 0);
return OK;
}
* Function: sam_buffer_free
*
* Description:
* Free aligned TX and RX descriptors and buffers. For the case of
* pre-allocated structures, the function does nothing.
*
* Input Parameters:
* priv - The EMAC driver state
*
* Returned Value:
* None
*
****************************************************************************/
static void sam_buffer_free(struct sam_emac_s *priv)
{
#ifndef CONFIG_SAM34_EMAC_PREALLOCATE
if (priv->txdesc)
{
kmm_free(priv->txdesc);
priv->txdesc = NULL;
}
if (priv->rxdesc)
{
kmm_free(priv->rxdesc);
priv->rxdesc = NULL;
}
if (priv->txbuffer)
{
kmm_free(priv->txbuffer);
priv->txbuffer = NULL;
}
if (priv->rxbuffer)
{
kmm_free(priv->rxbuffer);
priv->rxbuffer = NULL;
}
#endif
}
* Function: sam_transmit
*
* Description:
* Start hardware transmission. Called either from the txdone interrupt
* handling or from watchdog based polling.
*
* Input Parameters:
* priv - Reference to the driver state structure
*
* Returned Value:
* OK on success; a negated errno on failure
*
* Assumptions:
* May or may not be called from an interrupt handler. In either case,
* global interrupts are disabled, either explicitly or indirectly through
* interrupt handling logic.
*
****************************************************************************/
static int sam_transmit(struct sam_emac_s *priv)
{
struct net_driver_s *dev = &priv->dev;
volatile struct emac_txdesc_s *txdesc;
uint32_t regval;
uint32_t status;
ninfo("d_len: %d txhead: %d\n", dev->d_len, priv->txhead);
sam_dumppacket("Transmit packet", dev->d_buf, dev->d_len);
if (dev->d_len > EMAC_TX_UNITSIZE)
{
nerr("ERROR: Packet too big: %d\n", dev->d_len);
return -EINVAL;
}
txdesc = &priv->txdesc[priv->txhead];
if (sam_txfree(priv) < 1)
{
nerr("ERROR: No free TX descriptors\n");
return -EBUSY;
}
if (dev->d_len > 0)
{
memcpy((void *)txdesc->addr, dev->d_buf, dev->d_len);
}
status = dev->d_len | EMACTXD_STA_LAST;
if (priv->txhead == CONFIG_SAM34_EMAC_NTXBUFFERS - 1)
{
status |= EMACTXD_STA_WRAP;
}
txdesc->status = status;
if (++priv->txhead >= CONFIG_SAM34_EMAC_NTXBUFFERS)
{
priv->txhead = 0;
}
regval = sam_getreg(priv, SAM_EMAC_NCR);
regval |= EMAC_NCR_TSTART;
sam_putreg(priv, SAM_EMAC_NCR, regval);
wd_start(&priv->txtimeout, SAM_TXTIMEOUT,
sam_txtimeout_expiry, (wdparm_t)priv);
* available.
*/
dev->d_len = 0;
* RCOMP interrupt to stop further RX processing. Why? Because EACH RX
* packet that is dispatched is also an opportunity to reply with a TX
* packet. So, if we cannot handle an RX packet reply, then we disable
* all RX packet processing.
*/
if (sam_txfree(priv) < 1)
{
ninfo("Disabling RX interrupts\n");
sam_putreg(priv, SAM_EMAC_IDR, EMAC_INT_RCOMP);
}
return OK;
}
* Function: sam_txpoll
*
* Description:
* The transmitter is available, check if the network has any outgoing
* packets ready to send. This is a callback from devif_poll().
* devif_poll() may be called:
*
* 1. When the preceding TX packet send is complete,
* 2. When the preceding TX packet send timesout and the interface is reset
* 3. During normal TX polling
*
* Input Parameters:
* dev - Reference to the NuttX driver state structure
*
* Returned Value:
* OK on success; a negated errno on failure
*
* Assumptions:
* May or may not be called from an interrupt handler. In either case,
* global interrupts are disabled, either explicitly or indirectly through
* interrupt handling logic.
*
****************************************************************************/
static int sam_txpoll(struct net_driver_s *dev)
{
struct sam_emac_s *priv = (struct sam_emac_s *)dev->d_private;
sam_transmit(priv);
* the TX poll if we do not have buffering for another packet.
*/
if (sam_txfree(priv) == 0)
{
* available for another transfer.
*/
return -EBUSY;
}
* have been examined.
*/
return 0;
}
* Function: sam_dopoll
*
* Description:
* The function is called in order to perform an out-of-sequence TX poll.
* This is done:
*
* 1. After completion of a transmission (sam_txdone),
* 2. When new TX data is available (sam_txavail_process), and
* 3. After a TX timeout to restart the sending process
* (sam_txtimeout_process).
*
* Input Parameters:
* priv - Reference to the driver state structure
*
* Returned Value:
* None
*
* Assumptions:
* Global interrupts are disabled by interrupt handling logic.
*
****************************************************************************/
static void sam_dopoll(struct sam_emac_s *priv)
{
struct net_driver_s *dev = &priv->dev;
* TX poll if we do not have buffering for another packet.
*/
if (sam_txfree(priv) > 0)
{
* then poll the network for new XMIT data.
*/
devif_poll(dev, sam_txpoll);
}
}
* Function: sam_recvframe
*
* Description:
* The function is called when a frame is received. It scans the RX
* descriptors of the received frame and assembles the full packet/
*
* NOTE: This function will silently discard any packets containing errors.
*
* Input Parameters:
* priv - Reference to the driver state structure
*
* Returned Value:
* OK if a packet was successfully returned; -EAGAIN if there are no
* further packets available
*
* Assumptions:
* - Global interrupts are disabled by interrupt handling logic.
* - The RX descriptor D-cache list has been invalided to force fetching
* from RAM.
*
****************************************************************************/
static int sam_recvframe(struct sam_emac_s *priv)
{
struct emac_rxdesc_s *rxdesc;
struct net_driver_s *dev;
const uint8_t *src;
uint8_t *dest;
uint32_t rxndx;
uint32_t pktlen;
uint16_t copylen;
bool isframe;
* once it has successfully written a frame to memory.
*/
dev = &priv->dev;
dev->d_len = 0;
dest = dev->d_buf;
pktlen = 0;
rxndx = priv->rxndx;
rxdesc = &priv->rxdesc[rxndx];
isframe = false;
sam_cmcc_invalidate((uintptr_t)rxdesc,
(uintptr_t)rxdesc + sizeof(struct emac_rxdesc_s));
ninfo("rxndx: %" PRId32 "\n", rxndx);
while ((rxdesc->addr & EMACRXD_ADDR_OWNER) != 0)
{
* any previous fragments.
*/
if ((rxdesc->status & EMACRXD_STA_SOF) != 0)
{
while (rxndx != priv->rxndx)
{
rxdesc = &priv->rxdesc[priv->rxndx];
rxdesc->addr &= ~(EMACRXD_ADDR_OWNER);
if (++priv->rxndx >= CONFIG_SAM34_EMAC_NRXBUFFERS)
{
priv->rxndx = 0;
}
}
dest = dev->d_buf;
pktlen = 0;
isframe = true;
}
if (++rxndx >= CONFIG_SAM34_EMAC_NRXBUFFERS)
{
rxndx = 0;
}
if (isframe)
{
if (rxndx == priv->rxndx)
{
nerr("ERROR: No EOF (Invalid of buffers too small)\n");
do
{
rxdesc = &priv->rxdesc[priv->rxndx];
rxdesc->addr &= ~(EMACRXD_ADDR_OWNER);
if (++priv->rxndx >= CONFIG_SAM34_EMAC_NRXBUFFERS)
{
priv->rxndx = 0;
}
}
while (rxndx != priv->rxndx);
return -EIO;
}
copylen = EMAC_RX_UNITSIZE;
if ((pktlen + copylen) > CONFIG_NET_ETH_PKTSIZE)
{
copylen = CONFIG_NET_ETH_PKTSIZE - pktlen;
}
* force reload from RAM.
*/
src = (const uint8_t *)(rxdesc->addr & EMACRXD_ADDR_MASK);
sam_cmcc_invalidate((uintptr_t)src, (uintptr_t)src + copylen);
memcpy(dest, src, copylen);
dest += copylen;
pktlen += copylen;
if ((rxdesc->status & EMACRXD_STA_EOF) != 0)
{
dev->d_len = (rxdesc->status & EMACRXD_STA_FRLEN_MASK);
ninfo("packet %d-%" PRId32 " (%d)\n",
priv->rxndx, rxndx, dev->d_len);
* release the RX descriptor
*/
while (priv->rxndx != rxndx)
{
rxdesc = &priv->rxdesc[priv->rxndx];
rxdesc->addr &= ~(EMACRXD_ADDR_OWNER);
if (++priv->rxndx >= CONFIG_SAM34_EMAC_NRXBUFFERS)
{
priv->rxndx = 0;
}
}
* all of the data.
*/
ninfo("rxndx: %d d_len: %d\n", priv->rxndx, dev->d_len);
if (pktlen < dev->d_len)
{
nerr("ERROR: Buffer size %d; frame size %" PRId32 "\n",
dev->d_len, pktlen);
return -E2BIG;
}
return OK;
}
}
* discard this fragment and keep looking
*/
else
{
rxdesc->addr &= ~(EMACRXD_ADDR_OWNER);
priv->rxndx = rxndx;
}
rxdesc = &priv->rxdesc[rxndx];
sam_cmcc_invalidate((uintptr_t)rxdesc,
(uintptr_t)rxdesc + sizeof(struct emac_rxdesc_s));
}
* but not an EOF in the sequential buffers we own, it must mean that we
* have a partial packet. This should only happen if there was a Buffer
* Not Available (BNA) error. When bursts of data come in, quickly
* filling the available buffers, before our interrupts can even service
* them. Eventually, the ring buffer loops back on itself and the
* peripheral sees it cannot write the next fragment of the packet.
*
* In this case, we keep the rxndx at the start of the last frame, since
* the peripheral will finish writing the packet there next.
*/
if (!isframe)
{
priv->rxndx = rxndx;
}
ninfo("rxndx: %d\n", priv->rxndx);
return -EAGAIN;
}
* Function: sam_receive
*
* Description:
* An interrupt was received indicating the availability of one or more
* new RX packets in FIFO memory.
*
* Input Parameters:
* priv - Reference to the driver state structure
*
* Returned Value:
* None
*
* Assumptions:
* Global interrupts are disabled by interrupt handling logic.
*
****************************************************************************/
static void sam_receive(struct sam_emac_s *priv)
{
struct net_driver_s *dev = &priv->dev;
* EMAC frames.
*/
while (sam_recvframe(priv) == OK)
{
sam_dumppacket("Received packet", dev->d_buf, dev->d_len);
* configuration (this should not happen)
*/
if (dev->d_len > CONFIG_NET_ETH_PKTSIZE)
{
nwarn("WARNING: Dropped, Too big: %d\n", dev->d_len);
continue;
}
#ifdef CONFIG_NET_PKT
pkt_input(&priv->dev);
#endif
#ifdef CONFIG_NET_IPv4
if (BUF->type == HTONS(ETHTYPE_IP))
{
ninfo("IPv4 frame\n");
ipv4_input(&priv->dev);
* sent out on the network, d_len field will set to a value > 0.
*/
if (priv->dev.d_len > 0)
{
sam_transmit(priv);
}
}
else
#endif
#ifdef CONFIG_NET_IPv6
if (BUF->type == HTONS(ETHTYPE_IP6))
{
ninfo("IPv6 frame\n");
ipv6_input(&priv->dev);
* sent out on the network, d_len field will set to a value > 0.
*/
if (priv->dev.d_len > 0)
{
sam_transmit(priv);
}
}
else
#endif
#ifdef CONFIG_NET_ARP
if (BUF->type == HTONS(ETHTYPE_ARP))
{
ninfo("ARP frame\n");
arp_input(&priv->dev);
* sent out on the network, d_len field will set to a value > 0.
*/
if (priv->dev.d_len > 0)
{
sam_transmit(priv);
}
}
else
#endif
{
nwarn("WARNING: Dropped, Unknown type: %04x\n", BUF->type);
}
}
}
* Function: sam_txdone
*
* Description:
* An interrupt was received indicating that one or more frames have
* completed transmission.
*
* Input Parameters:
* priv - Reference to the driver state structure
*
* Returned Value:
* None
*
* Assumptions:
* Global interrupts are disabled by the watchdog logic.
*
****************************************************************************/
static void sam_txdone(struct sam_emac_s *priv)
{
struct emac_txdesc_s *txdesc;
* the TX descriptors have been examined, or (2) until we encounter the
* first descriptor that is still in use by the hardware.
*/
while (priv->txhead != priv->txtail)
{
txdesc = &priv->txdesc[priv->txtail];
sam_cmcc_invalidate((uintptr_t)txdesc,
(uintptr_t)txdesc + sizeof(struct emac_txdesc_s));
if ((txdesc->status & EMACTXD_STA_USED) == 0)
{
* case (only repeatable on start-up) where the USED bit is never
* set. Yikes! If we have encountered the first still busy
* descriptor, then we should also have TQBD equal to the
* descriptor address. If it is not, then treat is as used anyway.
*/
#if 0
#warning REVISIT
if (priv->txtail == 0 &&
sam_physramaddr((uintptr_t)txdesc) !=
sam_getreg(priv, SAM_EMAC_TBQB))
{
txdesc->status = (uint32_t)EMACTXD_STA_USED;
}
else
#endif
{
* loop now.
*/
break;
}
}
if (++priv->txtail >= CONFIG_SAM34_EMAC_NTXBUFFERS)
{
priv->txtail = 0;
}
* RX interrupts may previously have been disabled when we ran out of
* TX descriptors (see comments in sam_transmit()).
*/
sam_putreg(priv, SAM_EMAC_IER, EMAC_INT_RCOMP);
}
sam_dopoll(priv);
}
* Function: sam_interrupt_work
*
* Description:
* Perform interrupt related work from the worker thread
*
* Input Parameters:
* arg - The argument passed when work_queue() was called.
*
* Returned Value:
* OK on success
*
* Assumptions:
* Ethernet interrupts are disabled
*
****************************************************************************/
static void sam_interrupt_work(void *arg)
{
struct sam_emac_s *priv = (struct sam_emac_s *)arg;
uint32_t isr;
uint32_t rsr;
uint32_t tsr;
uint32_t imr;
uint32_t regval;
uint32_t pending;
uint32_t clrbits;
net_lock();
isr = sam_getreg(priv, SAM_EMAC_ISR);
rsr = sam_getreg(priv, SAM_EMAC_RSR);
tsr = sam_getreg(priv, SAM_EMAC_TSR);
imr = sam_getreg(priv, SAM_EMAC_IMR);
pending = isr & ~(imr | EMAC_INT_UNUSED);
ninfo("isr: %08" PRIx32 " pending: %08" PRIx32 "\n", isr, pending);
* checking for received data (because receiving can cause another
* transmission before we had a chance to handle the last one).
*
* ISR:TCOMP is set when a frame has been transmitted. Cleared on read.
* TSR:TXCOMP is set when a frame has been transmitted. Cleared by writing
* a one to this bit.
*/
if ((pending & EMAC_INT_TCOMP) != 0 || (tsr & EMAC_TSR_TXCOMP) != 0)
{
clrbits = EMAC_TSR_TXCOMP;
if ((tsr & EMAC_TSR_RLE) != 0)
{
clrbits = EMAC_TSR_RLE | sam_txinuse(priv);
sam_txreset(priv);
nerr("ERROR: Retry Limit Exceeded TSR: %08" PRIx32 "\n", tsr);
regval = sam_getreg(priv, SAM_EMAC_NCR);
regval |= EMAC_NCR_TXEN;
sam_putreg(priv, SAM_EMAC_NCR, regval);
}
if ((tsr & EMAC_TSR_COL) != 0)
{
nerr("ERROR: Collision occurred TSR: %08" PRIx32 "\n", tsr);
clrbits |= EMAC_TSR_COL;
}
if ((tsr & EMAC_TSR_TFC) != 0)
{
nerr("ERROR: Transmit Frame Corruption due to AHB error: "
"%08" PRIx32 "\n",
tsr);
clrbits |= EMAC_TSR_TFC;
}
*
* ISR:UND is set transmit DMA was not able to read data from memory,
* either because the bus was not granted in time, because a not
* OK hresp(bus error) was returned or because a used bit was read
* midway through frame transmission. If this occurs, the
* transmitter forces bad CRC. Cleared by writing a one to this bit.
*/
if ((tsr & EMAC_TSR_UND) != 0)
{
nerr("ERROR: Transmit Underrun TSR: %08" PRIx32 "\n", tsr);
clrbits |= EMAC_TSR_UND;
}
sam_putreg(priv, SAM_EMAC_TSR, clrbits);
sam_txdone(priv);
}
*
* RXCOMP indicates that a packet has been received and stored in memory.
* The RXCOMP bit is cleared whent he interrupt status register was read.
* RSR:REC indicates that one or more frames have been received and placed
* in memory. This indication is cleared by writing a one to this bit.
*/
if ((pending & EMAC_INT_RCOMP) != 0 || (rsr & EMAC_RSR_REC) != 0)
{
clrbits = EMAC_RSR_REC;
*
* RSR:RXOVR will be set if the RX FIFO is not able to store the
* receive frame due to a FIFO overflow, or if the receive status
* was not taken at the end of the frame. This bit is also set in
* DMA packet buffer mode if the packet buffer overflows. For DMA
* operation, the buffer will be recovered if an overrun occurs. This
* bit is cleared when set to 1.
*/
if ((rsr & EMAC_RSR_RXOVR) != 0)
{
nerr("ERROR: Receiver overrun RSR: %08" PRIx32 "\n", rsr);
clrbits |= EMAC_RSR_RXOVR;
}
*
* RSR:BNA means that an attempt was made to get a new buffer and the
* pointer indicated that it was owned by the processor. The DMA will
* reread the pointer each time an end of frame is received until a
* valid pointer is found. This bit is set following each descriptor
* read attempt that fails, even if consecutive pointers are
* unsuccessful and software has in the mean time cleared the status
* flag. Cleared by writing a one to this bit.
*/
if ((rsr & EMAC_RSR_BNA) != 0)
{
nerr("ERROR: Buffer not available RSR: %08" PRIx32 "\n", rsr);
clrbits |= EMAC_RSR_BNA;
}
sam_putreg(priv, SAM_EMAC_RSR, clrbits);
sam_receive(priv);
}
#ifdef CONFIG_DEBUG_NET
*
* ISR:PFRE indicates that a pause frame has been received with non-zero
* pause quantum. Cleared on a read.
*/
if ((pending & EMAC_INT_PFNZ) != 0)
{
nwarn("WARNING: Pause frame received\n");
}
*
* ISR:PTZ is set Pause Time Zero
*/
if ((pending & EMAC_INT_PTZ) != 0)
{
nwarn("WARNING: Pause TO!\n");
}
#endif
net_unlock();
up_enable_irq(SAM_IRQ_EMAC);
}
* Function: sam_emac_interrupt
*
* Description:
* Hardware interrupt handler
*
* Input Parameters:
* irq - Number of the IRQ that generated the interrupt
* context - Interrupt register state save info (architecture-specific)
*
* Returned Value:
* OK on success
*
* Assumptions:
*
****************************************************************************/
static int sam_emac_interrupt(int irq, void *context, void *arg)
{
struct sam_emac_s *priv = &g_emac;
uint32_t tsr;
* also disabled if the TX timeout event occurs, there can be no race
* condition here.
*/
up_disable_irq(SAM_IRQ_EMAC);
*
* ISR:TCOMP is set when a frame has been transmitted. Cleared on read (so
* we cannot read it here).
* TSR:TXCOMP is set when a frame has been transmitted. Cleared by writing
* a one to this bit.
*/
tsr = sam_getreg(priv, SAM_EMAC_TSR);
if ((tsr & EMAC_TSR_TXCOMP) != 0)
{
* there will be do race condition between any subsequent timeout
* expiration and the deferred interrupt processing.
*/
wd_cancel(&priv->txtimeout);
}
work_queue(ETHWORK, &priv->irqwork, sam_interrupt_work, priv, 0);
return OK;
}
* Function: sam_txtimeout_work
*
* Description:
* Perform TX timeout related work from the worker thread
*
* Input Parameters:
* arg - The argument passed when work_queue() as called.
*
* Returned Value:
* OK on success
*
* Assumptions:
* Ethernet interrupts are disabled
*
****************************************************************************/
static void sam_txtimeout_work(void *arg)
{
struct sam_emac_s *priv = (struct sam_emac_s *)arg;
nerr("ERROR: Timeout!\n");
* up again.
*/
net_lock();
sam_ifdown(&priv->dev);
sam_ifup(&priv->dev);
sam_dopoll(priv);
net_unlock();
}
* Function: sam_txtimeout_expiry
*
* Description:
* Our TX watchdog timed out. Called from the timer interrupt handler.
* The last TX never completed. Reset the hardware and start again.
*
* Input Parameters:
* arg - The argument
*
* Returned Value:
* None
*
* Assumptions:
* Global interrupts are disabled by the watchdog logic.
*
****************************************************************************/
static void sam_txtimeout_expiry(wdparm_t arg)
{
struct sam_emac_s *priv = (struct sam_emac_s *)arg;
* conditions with interrupt work. There is still a potential race
* condition with interrupt work that is already queued and in progress.
*/
up_disable_irq(SAM_IRQ_EMAC);
work_queue(ETHWORK, &priv->irqwork, sam_txtimeout_work, priv, 0);
}
* Function: sam_ifup
*
* Description:
* NuttX Callback: Bring up the EMAC interface when an IP address is
* provided
*
* Input Parameters:
* dev - Reference to the NuttX driver state structure
*
* Returned Value:
* None
*
* Assumptions:
*
****************************************************************************/
static int sam_ifup(struct net_driver_s *dev)
{
struct sam_emac_s *priv = (struct sam_emac_s *)dev->d_private;
int ret;
ninfo("Bringing up: %u.%u.%u.%u\n",
ip4_addr1(dev->d_ipaddr), ip4_addr2(dev->d_ipaddr),
ip4_addr3(dev->d_ipaddr), ip4_addr4(dev->d_ipaddr));
ninfo("Initialize the EMAC\n");
sam_emac_configure(priv);
sam_macaddress(priv);
ret = sam_phyinit(priv);
if (ret < 0)
{
nerr("ERROR: sam_phyinit failed: %d\n", ret);
return ret;
}
ret = sam_autonegotiate(priv);
if (ret < 0)
{
nerr("ERROR: sam_autonegotiate failed: %d\n", ret);
return ret;
}
while (sam_linkup(priv) == 0);
ninfo("Link detected\n");
ninfo("Enable normal operation\n");
priv->ifup = true;
up_enable_irq(SAM_IRQ_EMAC);
return OK;
}
* Function: sam_ifdown
*
* Description:
* NuttX Callback: Stop the interface.
*
* Input Parameters:
* dev - Reference to the NuttX driver state structure
*
* Returned Value:
* None
*
* Assumptions:
*
****************************************************************************/
static int sam_ifdown(struct net_driver_s *dev)
{
struct sam_emac_s *priv = (struct sam_emac_s *)dev->d_private;
irqstate_t flags;
ninfo("Taking the network down\n");
flags = enter_critical_section();
up_disable_irq(SAM_IRQ_EMAC);
wd_cancel(&priv->txtimeout);
* a known configuration that will guarantee the sam_ifup() always
* successfully brings the interface back up.
*/
sam_emac_reset(priv);
priv->ifup = false;
leave_critical_section(flags);
return OK;
}
* Function: sam_txavail_work
*
* Description:
* Perform an out-of-cycle poll on the worker thread.
*
* Input Parameters:
* arg - Reference to the NuttX driver state structure (cast to void*)
*
* Returned Value:
* None
*
* Assumptions:
* Called on the higher priority worker thread.
*
****************************************************************************/
static void sam_txavail_work(void *arg)
{
struct sam_emac_s *priv = (struct sam_emac_s *)arg;
ninfo("ifup: %d\n", priv->ifup);
net_lock();
if (priv->ifup)
{
sam_dopoll(priv);
}
net_unlock();
}
* Function: sam_txavail
*
* Description:
* Driver callback invoked when new TX data is available. This is a
* stimulus perform an out-of-cycle poll and, thereby, reduce the TX
* latency.
*
* Input Parameters:
* dev - Reference to the NuttX driver state structure
*
* Returned Value:
* None
*
* Assumptions:
* Called in normal user mode
*
****************************************************************************/
static int sam_txavail(struct net_driver_s *dev)
{
struct sam_emac_s *priv = (struct sam_emac_s *)dev->d_private;
* pending interrupt actions and we will have to ignore the Tx
* availability action.
*/
if (work_available(&priv->pollwork))
{
work_queue(ETHWORK, &priv->pollwork, sam_txavail_work, priv, 0);
}
return OK;
}
* Name: sam_hashindx
*
* Description:
* Cacuclate the hash address register index. The hash address register
* is 64 bits long and takes up two locations in the memory map. The
* destination address is reduced to a 6-bit index into the 64-bit Hash
* Register using the following hash function: The hash function is an XOR
* of every sixth bit of the destination address.
*
* ndx:05 = da:05 ^ da:11 ^ da:17 ^ da:23 ^ da:29 ^ da:35 ^ da:41 ^ da:47
* ndx:04 = da:04 ^ da:10 ^ da:16 ^ da:22 ^ da:28 ^ da:34 ^ da:40 ^ da:46
* ndx:03 = da:03 ^ da:09 ^ da:15 ^ da:21 ^ da:27 ^ da:33 ^ da:39 ^ da:45
* ndx:02 = da:02 ^ da:08 ^ da:14 ^ da:20 ^ da:26 ^ da:32 ^ da:38 ^ da:44
* ndx:01 = da:01 ^ da:07 ^ da:13 ^ da:19 ^ da:25 ^ da:31 ^ da:37 ^ da:43
* ndx:00 = da:00 ^ da:06 ^ da:12 ^ da:18 ^ da:24 ^ da:30 ^ da:36 ^ da:42
*
* Where da:00 represents the least significant bit of the first byte
* received and da:47 represents the most significant bit of the last byte
* received.
*
* Input Parameters:
* mac - The multicast address to be hashed
*
* Returned Value:
* The 6-bit hash table index
*
****************************************************************************/
#if defined(CONFIG_NET_MCASTGROUP) || defined(CONFIG_NET_ICMPv6)
static unsigned int sam_hashindx(const uint8_t *mac)
{
unsigned int ndx;
* ... 05 04 03 02 01 00]
*/
ndx = mac[0];
* ...11 10 09 08] [07 06 ...
*
* Accumulate: 05 04 03 02 01 00
* XOR: 11 10 09 08 07 06
*/
ndx ^= (mac[1] << 2) | (mac[0] >> 6);
* ... 17 16] [15 14 13 12 ...
*
* Accumulate: 05 04 03 02 01 00
* XOR: 11 10 09 08 07 06
* XOR: 17 16 15 14 13 12
*/
ndx ^= (mac[2] << 4) | (mac[1] >> 4);
* [23 22 21 20 19 18 ...
*
* Accumulate: 05 04 03 02 01 00
* XOR: 11 10 09 08 07 06
* XOR: 17 16 15 14 13 12
* XOR: 23 22 21 20 19 18
*/
ndx ^= (mac[2] >> 2);
* ... 29 28 27 26 25 24]
*
* Accumulate: 05 04 03 02 01 00
* XOR: 11 10 09 08 07 06
* XOR: 17 16 15 14 13 12
* XOR: 23 22 21 20 19 18
* XOR: 29 28 27 26 25 24
*/
ndx ^= mac[3];
* ... 35 34 33 32] [31 30 ...
*
* Accumulate: 05 04 03 02 01 00
* XOR: 11 10 09 08 07 06
* XOR: 17 16 15 14 13 12
* XOR: 23 22 21 20 19 18
* XOR: 29 28 27 26 25 24
* XOR: 35 34 33 32 31 30
*/
ndx ^= (mac[4] << 2) | (mac[3] >> 6);
* ... 41 40] [39 38 37 36 ...
*
* Accumulate: 05 04 03 02 01 00
* XOR: 11 10 09 08 07 06
* XOR: 17 16 15 14 13 12
* XOR: 23 22 21 20 19 18
* XOR: 29 28 27 26 25 24
* XOR: 35 34 33 32 31 30
* XOR: 41 40 39 38 37 36
*/
ndx ^= (mac[5] << 4) | (mac[4] >> 4);
* [47 46 45 44 43 42 ...
*
* Accumulate: 05 04 03 02 01 00
* XOR: 11 10 09 08 07 06
* XOR: 17 16 15 14 13 12
* XOR: 23 22 21 20 19 18
* XOR: 29 28 27 26 25 24
* XOR: 35 34 33 32 31 30
* XOR: 41 40 39 38 37 36
* XOR: 47 46 45 44 43 42
*/
ndx ^= (mac[5] >> 2);
return ndx & 0x3f;
}
#endif
* Function: sam_addmac
*
* Description:
* NuttX Callback: Add the specified MAC address to the hardware multicast
* address filtering
*
* Input Parameters:
* dev - Reference to the NuttX driver state structure
* mac - The MAC address to be added
*
* Returned Value:
* None
*
* Assumptions:
*
****************************************************************************/
#if defined(CONFIG_NET_MCASTGROUP) || defined(CONFIG_NET_ICMPv6)
static int sam_addmac(struct net_driver_s *dev, const uint8_t *mac)
{
struct sam_emac_s *priv = (struct sam_emac_s *)dev->d_private;
uintptr_t regaddr;
uint32_t regval;
unsigned int ndx;
unsigned int bit;
UNUSED(priv);
ninfo("MAC: %02x:%02x:%02x:%02x:%02x:%02x\n",
mac[0], mac[1], mac[2], mac[3], mac[4], mac[5]);
ndx = sam_hashindx(mac);
if (ndx >= 32)
{
regaddr = SAM_EMAC_HRT;
bit = 1 << (ndx - 32);
}
else
{
regaddr = SAM_EMAC_HRB;
bit = 1 << ndx;
}
regval = sam_getreg(priv, regaddr);
regval |= bit;
sam_putreg(priv, regaddr, regval);
* Network Configuration Register enable the reception of hash matched
* frames:
*
* - A multicast match will be signalled if the multicast hash enable bit
* is set, da:00 is logic 1 and the hash index points to a bit set in
* the Hash Register.
* - A unicast match will be signalled if the unicast hash enable bit is
* set, da:00 is logic 0 and the hash index points to a bit set in the
* Hash Register.
*/
regval = sam_getreg(priv, SAM_EMAC_NCFGR);
regval &= ~EMAC_NCFGR_UNIHEN;
regval |= EMAC_NCFGR_MTIHEN;
sam_putreg(priv, SAM_EMAC_NCFGR, regval);
return OK;
}
#endif
* Function: sam_rmmac
*
* Description:
* NuttX Callback: Remove the specified MAC address from the hardware
* multicast address filtering
*
* Input Parameters:
* dev - Reference to the NuttX driver state structure
* mac - The MAC address to be removed
*
* Returned Value:
* None
*
* Assumptions:
*
****************************************************************************/
#ifdef CONFIG_NET_MCASTGROUP
static int sam_rmmac(struct net_driver_s *dev, const uint8_t *mac)
{
struct sam_emac_s *priv = (struct sam_emac_s *)dev->d_private;
uint32_t regval;
unsigned int regaddr1;
unsigned int regaddr2;
unsigned int ndx;
unsigned int bit;
UNUSED(priv);
ninfo("MAC: %02x:%02x:%02x:%02x:%02x:%02x\n",
mac[0], mac[1], mac[2], mac[3], mac[4], mac[5]);
ndx = sam_hashindx(mac);
if (ndx >= 32)
{
regaddr1 = SAM_EMAC_HRT;
regaddr2 = SAM_EMAC_HRB;
bit = 1 << (ndx - 32);
}
else
{
regaddr1 = SAM_EMAC_HRB;
regaddr2 = SAM_EMAC_HRT;
bit = 1 << ndx;
}
regval = sam_getreg(priv, regaddr1);
regval &= ~bit;
sam_putreg(priv, regaddr1, regval);
* Network Configuration Register enable the reception of hash matched
* frames:
*
* - A multicast match will be signalled if the multicast hash enable bit
* is set, da:00 is logic 1 and the hash index points to a bit set in
* the Hash Register.
* - A unicast match will be signalled if the unicast hash enable bit is
* set, da:00 is logic 0 and the hash index points to a bit set in the
* Hash Register.
*/
if (regval == 0 && sam_getreg(priv, regaddr2) == 0)
{
regval = sam_getreg(priv, SAM_EMAC_NCFGR);
regval &= ~(EMAC_NCFGR_UNIHEN | EMAC_NCFGR_MTIHEN);
sam_putreg(priv, SAM_EMAC_NCFGR, regval);
}
return OK;
}
#endif
* Function: sam_ioctl
*
* Description:
* Handles driver ioctl calls:
*
* SIOCMIINOTIFY - Set up to received notifications from PHY interrupting
* events.
*
* SIOCGMIIPHY, SIOCGMIIREG, and SIOCSMIIREG:
* Executes the SIOCxMIIxxx command and responds using the request struct
* that must be provided as its 2nd parameter.
*
* When called with SIOCGMIIPHY it will get the PHY address for the device
* and write it to the req->phy_id field of the request struct.
*
* When called with SIOCGMIIREG it will read a register of the PHY that is
* specified using the req->reg_no struct field and then write its output
* to the req->val_out field.
*
* When called with SIOCSMIIREG it will write to a register of the PHY
* that is specified using the req->reg_no struct field and use req->
* val_in as its input.
*
* Input Parameters:
* dev - Ethernet device structure
* cmd - SIOCxMIIxxx command code
* arg - Request structure also used to return values
*
* Returned Value: Negated errno on failure.
*
* Assumptions:
*
****************************************************************************/
#ifdef CONFIG_NETDEV_IOCTL
static int sam_ioctl(struct net_driver_s *dev, int cmd, unsigned long arg)
{
#ifdef CONFIG_NETDEV_PHY_IOCTL
struct sam_emac_s *priv = (struct sam_emac_s *)dev->d_private;
#endif
int ret;
switch (cmd)
{
#ifdef CONFIG_NETDEV_PHY_IOCTL
#ifdef CONFIG_ARCH_PHY_INTERRUPT
case SIOCMIINOTIFY:
{
struct mii_ioctl_notify_s *req =
(struct mii_ioctl_notify_s *)((uintptr_t)arg);
ret = phy_notify_subscribe(dev->d_ifname, req->pid, &req->event);
if (ret == OK)
{
ret = sam_phyintenable(priv);
}
}
break;
#endif
case SIOCGMIIPHY:
{
struct mii_ioctl_data_s *req =
(struct mii_ioctl_data_s *)((uintptr_t)arg);
req->phy_id = priv->phyaddr;
ret = OK;
}
break;
case SIOCGMIIREG:
{
struct mii_ioctl_data_s *req =
(struct mii_ioctl_data_s *)((uintptr_t)arg);
uint32_t regval;
regval = sam_getreg(priv, SAM_EMAC_NCR);
sam_putreg(priv, SAM_EMAC_NCR, regval | EMAC_NCR_MPE);
ret = sam_phyread(priv, req->phy_id, req->reg_num, &req->val_out);
sam_putreg(priv, SAM_EMAC_NCR, regval);
}
break;
case SIOCSMIIREG:
{
struct mii_ioctl_data_s *req =
(struct mii_ioctl_data_s *)((uintptr_t)arg);
uint32_t regval;
regval = sam_getreg(priv, SAM_EMAC_NCR);
sam_putreg(priv, SAM_EMAC_NCR, regval | EMAC_NCR_MPE);
ret = sam_phywrite(priv, req->phy_id, req->reg_num, req->val_in);
sam_putreg(priv, SAM_EMAC_NCR, regval);
}
break;
#endif
default:
ret = -ENOTTY;
break;
}
return ret;
}
#endif
* Function: sam_phydump
*
* Description:
* Dump the contents of PHY registers
*
* Input Parameters:
* priv - A reference to the private driver state structure
*
* Returned Value:
* None
*
****************************************************************************/
#if defined(CONFIG_DEBUG_NET) && defined(CONFIG_DEBUG_INFO)
static void sam_phydump(struct sam_emac_s *priv)
{
uint32_t regval;
uint16_t phyval;
regval = sam_getreg(priv, SAM_EMAC_NCR);
regval |= EMAC_NCR_MPE;
sam_putreg(priv, SAM_EMAC_NCR, regval);
#ifdef CONFIG_SAM34_EMAC_RMII
ninfo("RMII Registers (Address %02x)\n", priv->phyaddr);
#else
ninfo("MII Registers (Address %02x)\n", priv->phyaddr);
#endif
sam_phyread(priv, priv->phyaddr, MII_MCR, &phyval);
ninfo(" MCR: %04x\n", phyval);
sam_phyread(priv, priv->phyaddr, MII_MSR, &phyval);
ninfo(" MSR: %04x\n", phyval);
sam_phyread(priv, priv->phyaddr, MII_ADVERTISE, &phyval);
ninfo(" ADVERTISE: %04x\n", phyval);
sam_phyread(priv, priv->phyaddr, MII_LPA, &phyval);
ninfo(" LPR: %04x\n", phyval);
sam_phyread(priv, priv->phyaddr, CONFIG_SAM34_EMAC_PHYSR, &phyval);
ninfo(" PHYSR: %04x\n", phyval);
regval = sam_getreg(priv, SAM_EMAC_NCR);
regval &= ~EMAC_NCR_MPE;
sam_putreg(priv, SAM_EMAC_NCR, regval);
}
#endif
* Function: sam_phyintenable
*
* Description:
* Enable link up/down PHY interrupts. The interrupt protocol is like this:
*
* - Interrupt status is cleared when the interrupt is enabled.
* - Interrupt occurs. Interrupt is disabled (at the processor level) when
* is received.
* - Interrupt status is cleared when the interrupt is re-enabled.
*
* Input Parameters:
* priv - A reference to the private driver state structure
*
* Returned Value:
* OK on success; Negated errno (-ETIMEDOUT) on failure.
*
****************************************************************************/
#if defined(CONFIG_NETDEV_PHY_IOCTL) && defined(CONFIG_ARCH_PHY_INTERRUPT)
static int sam_phyintenable(struct sam_emac_s *priv)
{
#if defined(CONFIG_ETH0_PHY_KSZ8051) || defined(CONFIG_ETH0_PHY_KSZ8081)
uint32_t regval;
uint16_t phyval;
int ret;
regval = sam_getreg(priv, SAM_EMAC_NCR);
sam_putreg(priv, SAM_EMAC_NCR, regval | EMAC_NCR_MPE);
* interrupts
*/
ret = sam_phyread(priv, priv->phyaddr, MII_KSZ8081_INT, &phyval);
if (ret == OK)
{
ret = sam_phywrite(priv, priv->phyaddr, MII_KSZ8081_INT,
(MII_KSZ80X1_INT_LDEN | MII_KSZ80X1_INT_LUEN));
}
sam_putreg(priv, SAM_EMAC_NCR, regval);
return ret;
#else
# warning Missing logic
return -ENOSYS;
#endif
}
#endif
* Function: sam_phywait
*
* Description:
* Wait for the PHY to become IDLE
*
* Input Parameters:
* priv - A reference to the private driver state structure
*
* Returned Value:
* OK on success; Negated errno (-ETIMEDOUT) on failure.
*
****************************************************************************/
static int sam_phywait(struct sam_emac_s *priv)
{
volatile unsigned int retries;
for (retries = 0; retries < PHY_RETRY_MAX; retries++)
{
if ((sam_getreg(priv, SAM_EMAC_NSR) & EMAC_NSR_IDLE) != 0)
{
return OK;
}
}
return -ETIMEDOUT;
}
* Function: sam_phyreset
*
* Description:
* Reset the PHY
*
* Input Parameters:
* priv - A reference to the private driver state structure
*
* Returned Value:
* OK on success; Negated errno on failure.
*
* Assumptions:
*
****************************************************************************/
static int sam_phyreset(struct sam_emac_s *priv)
{
uint32_t regval;
uint16_t mcr;
int timeout;
int ret;
ninfo(" sam_phyreset\n");
regval = sam_getreg(priv, SAM_EMAC_NCR);
regval |= EMAC_NCR_MPE;
sam_putreg(priv, SAM_EMAC_NCR, regval);
ret = sam_phywrite(priv, priv->phyaddr, MII_MCR, MII_MCR_RESET);
if (ret < 0)
{
nerr("ERROR: sam_phywrite failed: %d\n", ret);
}
ret = -ETIMEDOUT;
for (timeout = 0; timeout < 10; timeout++)
{
mcr = MII_MCR_RESET;
int result = sam_phyread(priv, priv->phyaddr, MII_MCR, &mcr);
if (result < 0)
{
nerr("ERROR: Failed to read the MCR register: %d\n", ret);
ret = result;
}
else if ((mcr & MII_MCR_RESET) == 0)
{
ret = OK;
break;
}
}
regval = sam_getreg(priv, SAM_EMAC_NCR);
regval &= ~EMAC_NCR_MPE;
sam_putreg(priv, SAM_EMAC_NCR, regval);
return ret;
}
* Function: sam_phyfind
*
* Description:
* Verify the PHY address and, if it is bad, try to one that works.
*
* Input Parameters:
* priv - A reference to the private driver state structure
*
* Returned Value:
* OK on success; Negated errno on failure.
*
* Assumptions:
*
****************************************************************************/
static int sam_phyfind(struct sam_emac_s *priv, uint8_t *phyaddr)
{
uint32_t regval;
uint16_t phyval;
uint8_t candidate;
unsigned int offset;
int ret = -ESRCH;
ninfo("Find a valid PHY address\n");
regval = sam_getreg(priv, SAM_EMAC_NCR);
regval |= EMAC_NCR_MPE;
sam_putreg(priv, SAM_EMAC_NCR, regval);
candidate = *phyaddr;
ret = sam_phyread(priv, candidate, MII_PHYID1, &phyval);
if (ret == OK && phyval == MII_OUI_MSB)
{
*phyaddr = candidate;
ret = OK;
}
else
{
nerr("ERROR: sam_phyread failed for PHY address %02x: %d\n",
candidate, ret);
for (offset = 0; offset < 32; offset++)
{
candidate = (candidate + 1) & 0x1f;
ret = sam_phyread(priv, candidate, MII_PHYID1, &phyval);
if (ret == OK && phyval == MII_OUI_MSB)
{
ret = OK;
break;
}
}
}
if (ret == OK)
{
ninfo(" PHYID1: %04x PHY addr: %d\n", phyval, candidate);
*phyaddr = candidate;
sam_phyread(priv, candidate, CONFIG_SAM34_EMAC_PHYSR, &phyval);
ninfo(" PHYSR: %04x PHY addr: %d\n", phyval, candidate);
}
regval = sam_getreg(priv, SAM_EMAC_NCR);
regval &= ~EMAC_NCR_MPE;
sam_putreg(priv, SAM_EMAC_NCR, regval);
return ret;
}
* Function: sam_phyread
*
* Description:
* Read a PHY register.
*
* Input Parameters:
* priv - A reference to the private driver state structure
* phyaddr - The PHY device address
* regaddr - The PHY register address
* phyval - The location to return the 16-bit PHY register value.
*
* Returned Value:
* OK on success; Negated errno on failure.
*
* Assumptions:
*
****************************************************************************/
static int sam_phyread(struct sam_emac_s *priv, uint8_t phyaddr,
uint8_t regaddr, uint16_t *phyval)
{
uint32_t regval;
int ret;
ret = sam_phywait(priv);
if (ret < 0)
{
nerr("ERROR: sam_phywait failed: %d\n", ret);
return ret;
}
regval = EMAC_MAN_DATA(0) | EMAC_MAN_WTN | EMAC_MAN_REGA(regaddr) |
EMAC_MAN_PHYA(phyaddr) | EMAC_MAN_READ | EMAC_MAN_WZO;
#ifndef CONFIG_SAM34_EMAC_CLAUSE45
* 30 should be written with a 0 rather than a 1.
*/
regval |= EMAC_MAN_CLTTO;
#endif
sam_putreg(priv, SAM_EMAC_MAN, regval);
ret = sam_phywait(priv);
if (ret < 0)
{
nerr("ERROR: sam_phywait failed: %d\n", ret);
return ret;
}
*phyval = (uint16_t)(sam_getreg(priv, SAM_EMAC_MAN) & EMAC_MAN_DATA_MASK);
return OK;
}
* Function: sam_phywrite
*
* Description:
* Write to a PHY register.
*
* Input Parameters:
* priv - A reference to the private driver state structure
* phyaddr - The PHY device address
* regaddr - The PHY register address
* phyval - The 16-bit value to write to the PHY register.
*
* Returned Value:
* OK on success; Negated errno on failure.
*
* Assumptions:
*
****************************************************************************/
static int sam_phywrite(struct sam_emac_s *priv, uint8_t phyaddr,
uint8_t regaddr, uint16_t phyval)
{
uint32_t regval;
int ret;
ret = sam_phywait(priv);
if (ret < 0)
{
nerr("ERROR: sam_phywait failed: %d\n", ret);
return ret;
}
regval = EMAC_MAN_DATA(phyval) | EMAC_MAN_WTN | EMAC_MAN_REGA(regaddr) |
EMAC_MAN_PHYA(phyaddr) | EMAC_MAN_WRITE | EMAC_MAN_WZO;
#ifndef CONFIG_SAM34_EMAC_CLAUSE45
* 30 should be written with a 0 rather than a 1.
*/
regval |= EMAC_MAN_CLTTO;
#endif
sam_putreg(priv, SAM_EMAC_MAN, regval);
ret = sam_phywait(priv);
if (ret < 0)
{
nerr("ERROR: sam_phywait failed: %d\n", ret);
return ret;
}
return OK;
}
* Function: sam_autonegotiate
*
* Description:
* Autonegotiate speed and duplex.
*
* Input Parameters:
* priv - A reference to the private driver state structure
*
* Returned Value:
* OK on success; Negated errno on failure.
*
****************************************************************************/
static int sam_autonegotiate(struct sam_emac_s *priv)
{
uint32_t regval;
uint16_t phyid1;
uint16_t phyid2;
uint16_t mcr;
uint16_t msr;
uint16_t advertise;
uint16_t lpa;
int timeout;
int ret;
regval = sam_getreg(priv, SAM_EMAC_NCR);
regval |= EMAC_NCR_MPE;
sam_putreg(priv, SAM_EMAC_NCR, regval);
ret = sam_phyread(priv, priv->phyaddr, MII_PHYID1, &phyid1);
if (ret < 0)
{
nerr("ERROR: Failed to read PHYID1\n");
goto errout;
}
ninfo("PHYID1: %04x PHY address: %02x\n", phyid1, priv->phyaddr);
ret = sam_phyread(priv, priv->phyaddr, MII_PHYID2, &phyid2);
if (ret < 0)
{
nerr("ERROR: Failed to read PHYID2\n");
goto errout;
}
ninfo("PHYID2: %04x PHY address: %02x\n", phyid2, priv->phyaddr);
if (phyid1 == MII_OUI_MSB &&
((phyid2 & MII_PHYID2_OUI_MASK) >> MII_PHYID2_OUI_SHIFT) == MII_OUI_LSB)
{
ninfo(" Vendor Model Number: %04x\n",
(phyid2 & MII_PHYID2_MODEL_MASK) >> MII_PHYID2_MODEL_SHIFT);
ninfo(" Model Revision Number: %04x\n",
(phyid2 & MII_PHYID2_REV_MASK) >> MII_PHYID2_REV_SHIFT);
}
else
{
nerr("ERROR: PHY not recognized\n");
}
ret = sam_phyread(priv, priv->phyaddr, MII_MCR, &mcr);
if (ret < 0)
{
nerr("ERROR: Failed to read MCR\n");
goto errout;
}
mcr &= ~MII_MCR_ANENABLE;
mcr &= ~(MII_MCR_LOOPBACK | MII_MCR_PDOWN);
mcr |= MII_MCR_ISOLATE;
ret = sam_phywrite(priv, priv->phyaddr, MII_MCR, mcr);
if (ret < 0)
{
nerr("ERROR: Failed to write MCR\n");
goto errout;
}
* Next page 100BaseTxFD and HD, 10BaseTFD and HD, IEEE 802.3
*/
advertise = MII_ADVERTISE_100BASETXFULL | MII_ADVERTISE_100BASETXHALF |
MII_ADVERTISE_10BASETXFULL | MII_ADVERTISE_10BASETXHALF |
MII_ADVERTISE_8023;
ret = sam_phywrite(priv, priv->phyaddr, MII_ADVERTISE, advertise);
if (ret < 0)
{
nerr("ERROR: Failed to write ANAR\n");
goto errout;
}
ret = sam_phyread(priv, priv->phyaddr, MII_MCR, &mcr);
if (ret < 0)
{
nerr("ERROR: Failed to read MCR\n");
goto errout;
}
mcr |= (MII_MCR_SPEED100 | MII_MCR_ANENABLE | MII_MCR_FULLDPLX);
ret = sam_phywrite(priv, priv->phyaddr, MII_MCR, mcr);
if (ret < 0)
{
nerr("ERROR: Failed to write MCR\n");
goto errout;
}
mcr |= MII_MCR_ANRESTART;
mcr &= ~MII_MCR_ISOLATE;
ret = sam_phywrite(priv, priv->phyaddr, MII_MCR, mcr);
if (ret < 0)
{
nerr("ERROR: Failed to write MCR\n");
goto errout;
}
ninfo(" MCR: %04x\n", mcr);
timeout = 0;
for (; ; )
{
ret = sam_phyread(priv, priv->phyaddr, MII_MSR, &msr);
if (ret < 0)
{
nerr("ERROR: Failed to read MSR\n");
goto errout;
}
if ((msr & MII_MSR_ANEGCOMPLETE) != 0)
{
ninfo("AutoNegotiate complete\n");
break;
}
if (++timeout >= PHY_RETRY_MAX)
{
nerr("ERROR: TimeOut\n");
sam_phydump(priv);
ret = -ETIMEDOUT;
goto errout;
}
}
ret = sam_phyread(priv, priv->phyaddr, MII_LPA, &lpa);
if (ret < 0)
{
nerr("ERROR: Failed to read ANLPAR\n");
goto errout;
}
regval = sam_getreg(priv, SAM_EMAC_NCFGR);
regval &= ~(EMAC_NCFGR_SPD | EMAC_NCFGR_FD);
if (((advertise & lpa) & MII_ADVERTISE_100BASETXFULL) != 0)
{
regval |= (EMAC_NCFGR_SPD | EMAC_NCFGR_FD);
}
else if (((advertise & lpa) & MII_ADVERTISE_10BASETXFULL) != 0)
{
regval |= EMAC_NCFGR_FD;
}
else if (((advertise & lpa) & MII_ADVERTISE_100BASETXHALF) != 0)
{
regval |= EMAC_NCFGR_SPD;
}
#if 0
else if (((advertise & lpa) & MII_ADVERTISE_10BASETXHALF) != 0)
{
}
#endif
sam_putreg(priv, SAM_EMAC_NCFGR, regval);
regval = sam_getreg(priv, SAM_EMAC_UR);
#ifdef CONFIG_SAM34_EMAC_RMII
regval &= ~EMAC_UR_MII;
#else
regval |= EMAC_UR_MII;
#endif
sam_putreg(priv, SAM_EMAC_UR, regval);
errout:
regval = sam_getreg(priv, SAM_EMAC_NCR);
regval &= ~EMAC_NCR_MPE;
sam_putreg(priv, SAM_EMAC_NCR, regval);
return ret;
}
* Function: sam_linkup
*
* Description:
* Check if the link is up
*
* Input Parameters:
* priv - A reference to the private driver state structure
*
* Returned Value:
* true: The link is up
*
****************************************************************************/
static bool sam_linkup(struct sam_emac_s *priv)
{
uint32_t regval;
uint16_t msr;
uint16_t physr;
bool linkup = false;
int ret;
regval = sam_getreg(priv, SAM_EMAC_NCR);
regval |= EMAC_NCR_MPE;
sam_putreg(priv, SAM_EMAC_NCR, regval);
ret = sam_phyread(priv, priv->phyaddr, MII_MSR, &msr);
if (ret < 0)
{
nerr("ERROR: Failed to read MSR: %d\n", ret);
goto errout;
}
if ((msr & MII_MSR_LINKSTATUS) == 0)
{
nerr("ERROR: MSR LinkStatus: %04x\n", msr);
goto errout;
}
ret = sam_phyread(priv, priv->phyaddr, CONFIG_SAM34_EMAC_PHYSR, &physr);
if (ret < 0)
{
nerr("ERROR: Failed to read PHYSR: %d\n", ret);
goto errout;
}
regval = sam_getreg(priv, SAM_EMAC_NCFGR);
regval &= ~(EMAC_NCFGR_SPD | EMAC_NCFGR_FD);
if ((msr & MII_MSR_100BASETXFULL) != 0 && PHYSR_IS100FDX(physr))
{
regval |= (EMAC_NCFGR_SPD | EMAC_NCFGR_FD);
}
else if ((msr & MII_MSR_10BASETXFULL) != 0 && PHYSR_IS10FDX(physr))
{
regval |= EMAC_NCFGR_FD;
}
else if ((msr & MII_MSR_100BASETXHALF) != 0 && PHYSR_IS100HDX(physr))
{
regval |= EMAC_NCFGR_SPD;
}
#if 0
else if ((msr & MII_MSR_10BASETXHALF) != 0 && PHYSR_IS10HDX(physr))
{
}
#endif
sam_putreg(priv, SAM_EMAC_NCFGR, regval);
ninfo("Link is up\n");
linkup = true;
errout:
regval = sam_getreg(priv, SAM_EMAC_NCR);
regval &= ~EMAC_NCR_MPE;
sam_putreg(priv, SAM_EMAC_NCR, regval);
return linkup;
}
* Function: sam_phyinit
*
* Description:
* Configure the PHY and determine the link speed/duplex.
*
* Input Parameters:
* priv - A reference to the private driver state structure
*
* Returned Value:
* OK on success; Negated errno on failure.
*
****************************************************************************/
static int sam_phyinit(struct sam_emac_s *priv)
{
uint32_t regval;
int ret;
regval = sam_getreg(priv, SAM_EMAC_NCFGR);
regval &= ~EMAC_NCFGR_CLK_MASK;
#if BOARD_MCK_FREQUENCY > (160 * 1000 * 1000)
# error Supported MCK frequency
#elif BOARD_MCK_FREQUENCY > (80 * 1000 * 1000)
regval |= EMAC_NCFGR_CLK_DIV64;
#elif BOARD_MCK_FREQUENCY > (40 * 1000 * 1000)
regval |= EMAC_NCFGR_CLK_DIV32;
#elif BOARD_MCK_FREQUENCY > (20 * 1000 * 1000)
regval |= EMAC_NCFGR_CLK_DIV16;
#else
regval |= EMAC_NCFGR_CLK_DIV8;
#endif
sam_putreg(priv, SAM_EMAC_NCFGR, regval);
priv->phyaddr = CONFIG_SAM34_EMAC_PHYADDR;
ret = sam_phyfind(priv, &priv->phyaddr);
if (ret < 0)
{
nerr("ERROR: sam_phyfind failed: %d\n", ret);
return ret;
}
if (priv->phyaddr != CONFIG_SAM34_EMAC_PHYADDR)
{
sam_phyreset(priv);
}
return OK;
}
* Function: sam_ethgpioconfig
*
* Description:
* Configure GPIOs for the EMAC MII interface.
*
* Input Parameters:
* priv - A reference to the private driver state structure
*
* Returned Value:
* None.
*
* Assumptions:
*
****************************************************************************/
static inline void sam_ethgpioconfig(struct sam_emac_s *priv)
{
sam_configgpio(GPIO_EMAC_TXCK);
sam_configgpio(GPIO_EMAC_TXEN);
sam_configgpio(GPIO_EMAC_TX0);
sam_configgpio(GPIO_EMAC_TX1);
sam_configgpio(GPIO_EMAC_TX2);
sam_configgpio(GPIO_EMAC_TX3);
#if 0
sam_configgpio(GPIO_EMAC_TXER);
#endif
sam_configgpio(GPIO_EMAC_RXCK);
sam_configgpio(GPIO_EMAC_RXDV);
sam_configgpio(GPIO_EMAC_RX0);
sam_configgpio(GPIO_EMAC_RX1);
sam_configgpio(GPIO_EMAC_RX2);
sam_configgpio(GPIO_EMAC_RX3);
sam_configgpio(GPIO_EMAC_RXER);
sam_configgpio(GPIO_EMAC_CRS);
sam_configgpio(GPIO_EMAC_COL);
sam_configgpio(GPIO_EMAC_MDC);
sam_configgpio(GPIO_EMAC_MDIO);
}
* Function: sam_txreset
*
* Description:
* Reset the transmit logic
*
* Input Parameters:
* priv - A reference to the private driver state structure
*
* Returned Value:
* None.
*
* Assumptions:
*
****************************************************************************/
static void sam_txreset(struct sam_emac_s *priv)
{
uint8_t *txbuffer = priv->txbuffer;
struct emac_txdesc_s *txdesc = priv->txdesc;
uintptr_t bufaddr;
uint32_t regval;
int ndx;
regval = sam_getreg(priv, SAM_EMAC_NCR);
regval &= ~EMAC_NCR_TXEN;
sam_putreg(priv, SAM_EMAC_NCR, regval);
priv->txhead = 0;
priv->txtail = 0;
for (ndx = 0; ndx < CONFIG_SAM34_EMAC_NTXBUFFERS; ndx++)
{
bufaddr = (uint32_t)(&(txbuffer[ndx * EMAC_TX_UNITSIZE]));
* as in used by firmware
*/
txdesc[ndx].addr = bufaddr;
txdesc[ndx].status = EMACTXD_STA_USED;
}
txdesc[CONFIG_SAM34_EMAC_NTXBUFFERS - 1].status =
EMACTXD_STA_USED | EMACTXD_STA_WRAP;
sam_putreg(priv, SAM_EMAC_TBQB, (uintptr_t)txdesc);
}
* Function: sam_rxreset
*
* Description:
* Reset the receive logic
*
* Input Parameters:
* priv - A reference to the private driver state structure
*
* Returned Value:
* None.
*
* Assumptions:
*
****************************************************************************/
static void sam_rxreset(struct sam_emac_s *priv)
{
struct emac_rxdesc_s *rxdesc = priv->rxdesc;
uint8_t *rxbuffer = priv->rxbuffer;
uint32_t bufaddr;
uint32_t regval;
int ndx;
regval = sam_getreg(priv, SAM_EMAC_NCR);
regval &= ~EMAC_NCR_RXEN;
sam_putreg(priv, SAM_EMAC_NCR, regval);
priv->rxndx = 0;
for (ndx = 0; ndx < CONFIG_SAM34_EMAC_NRXBUFFERS; ndx++)
{
bufaddr = (uintptr_t)(&(rxbuffer[ndx * EMAC_RX_UNITSIZE]));
DEBUGASSERT((bufaddr & ~EMACRXD_ADDR_MASK) == 0);
* EMACRXD_ADDR_WRAP.
*/
rxdesc[ndx].addr = bufaddr;
rxdesc[ndx].status = 0;
}
rxdesc[CONFIG_SAM34_EMAC_NRXBUFFERS - 1].addr |= EMACRXD_ADDR_WRAP;
sam_putreg(priv, SAM_EMAC_RBQB, (uintptr_t)rxdesc);
}
* Function: sam_emac_reset
*
* Description:
* Reset the EMAC block.
*
* Input Parameters:
* priv - A reference to the private driver state structure
*
* Returned Value:
* None.
*
* Assumptions:
*
****************************************************************************/
static void sam_emac_reset(struct sam_emac_s *priv)
{
#ifdef CONFIG_NETDEV_PHY_IOCTL
uint32_t regval;
* then we cannot communicate with the PHY. So, instead, just disable
* interrupts, cancel timers, and disable TX and RX.
*/
sam_putreg(priv, SAM_EMAC_IDR, EMAC_INT_ALL);
sam_rxreset(priv);
sam_txreset(priv);
regval = sam_getreg(priv, SAM_EMAC_NCR);
regval &= ~(EMAC_NCR_RXEN | EMAC_NCR_TXEN | EMAC_NCR_WESTAT);
sam_putreg(priv, SAM_EMAC_NCR, regval);
#else
sam_putreg(priv, SAM_EMAC_IDR, EMAC_INT_ALL);
sam_rxreset(priv);
sam_txreset(priv);
sam_putreg(priv, SAM_EMAC_NCR, EMAC_NCR_CLRSTAT);
sam_emac_disableclk();
#endif
}
* Function: sam_macaddress
*
* Description:
* Configure the selected MAC address.
*
* Input Parameters:
* priv - A reference to the private driver state structure
*
* Returned Value:
* OK on success; Negated errno on failure.
*
* Assumptions:
*
****************************************************************************/
static void sam_macaddress(struct sam_emac_s *priv)
{
struct net_driver_s *dev = &priv->dev;
uint32_t regval;
ninfo("%s MAC: %02x:%02x:%02x:%02x:%02x:%02x\n",
dev->d_ifname,
dev->d_mac.ether.ether_addr_octet[0],
dev->d_mac.ether.ether_addr_octet[1],
dev->d_mac.ether.ether_addr_octet[2],
dev->d_mac.ether.ether_addr_octet[3],
dev->d_mac.ether.ether_addr_octet[4],
dev->d_mac.ether.ether_addr_octet[5]);
regval = (uint32_t)dev->d_mac.ether.ether_addr_octet[0] |
(uint32_t)dev->d_mac.ether.ether_addr_octet[1] << 8 |
(uint32_t)dev->d_mac.ether.ether_addr_octet[2] << 16 |
(uint32_t)dev->d_mac.ether.ether_addr_octet[3] << 24;
sam_putreg(priv, SAM_EMAC_SAB1, regval);
regval = (uint32_t)dev->d_mac.ether.ether_addr_octet[4] |
(uint32_t)dev->d_mac.ether.ether_addr_octet[5] << 8;
sam_putreg(priv, SAM_EMAC_SAT1, regval);
}
* Function: sam_emac_configure
*
* Description:
* Configure the EMAC interface for normal operation.
*
* Input Parameters:
* priv - A reference to the private driver state structure
*
* Returned Value:
* OK on success; Negated errno on failure.
*
* Assumptions:
*
****************************************************************************/
static int sam_emac_configure(struct sam_emac_s *priv)
{
uint32_t regval;
ninfo("Entry\n");
sam_emac_enableclk();
sam_putreg(priv, SAM_EMAC_NCR, EMAC_NCR_CLRSTAT);
sam_putreg(priv, SAM_EMAC_IDR, EMAC_INT_ALL);
regval = (EMAC_RSR_RXOVR | EMAC_RSR_REC | EMAC_RSR_BNA);
sam_putreg(priv, SAM_EMAC_RSR, regval);
regval = (EMAC_TSR_UBR | EMAC_TSR_COL | EMAC_TSR_RLE | EMAC_TSR_TFC |
EMAC_TSR_TXCOMP | EMAC_TSR_UND);
sam_putreg(priv, SAM_EMAC_TSR, regval);
sam_getreg(priv, SAM_EMAC_ISR);
* Don't copy FCS.
*/
regval = sam_getreg(priv, SAM_EMAC_NCFGR);
regval |= (EMAC_NCFGR_RFCS | EMAC_NCFGR_PEN);
#ifdef CONFIG_NET_PROMISCUOUS
regval |= EMAC_NCFGR_CAF;
#else
regval &= ~EMAC_NCFGR_CAF;
#endif
#ifdef CONFIG_SAM34_EMAC_NBC
regval |= EMAC_NCFGR_NBC;
#else
regval &= ~EMAC_NCFGR_NBC;
#endif
sam_putreg(priv, SAM_EMAC_NCFGR, regval);
sam_rxreset(priv);
sam_txreset(priv);
regval = sam_getreg(priv, SAM_EMAC_NCR);
regval |= (EMAC_NCR_RXEN | EMAC_NCR_TXEN | EMAC_NCR_WESTAT);
sam_putreg(priv, SAM_EMAC_NCR, regval);
regval = (EMAC_INT_RCOMP | EMAC_INT_RXUBR | EMAC_INT_TUR | EMAC_INT_RLEX |
EMAC_INT_TFC | EMAC_INT_TCOMP | EMAC_INT_ROVR | EMAC_INT_HRESP |
EMAC_INT_PFNZ | EMAC_INT_PTZ);
sam_putreg(priv, SAM_EMAC_IER, regval);
return OK;
}
* Public Functions
****************************************************************************/
* Function: arm_netinitialize
*
* Description:
* Initialize the EMAC driver.
*
* Input Parameters:
* None
*
* Returned Value:
* None
*
* Assumptions:
* Called very early in the initialization sequence.
*
****************************************************************************/
void arm_netinitialize(void)
{
struct sam_emac_s *priv = &g_emac;
int ret;
memset(priv, 0, sizeof(struct sam_emac_s));
priv->dev.d_buf = g_pktbuf;
priv->dev.d_ifup = sam_ifup;
priv->dev.d_ifdown = sam_ifdown;
priv->dev.d_txavail = sam_txavail;
#ifdef CONFIG_NET_MCASTGROUP
priv->dev.d_addmac = sam_addmac;
priv->dev.d_rmmac = sam_rmmac;
#endif
#ifdef CONFIG_NETDEV_IOCTL
priv->dev.d_ioctl = sam_ioctl;
#endif
priv->dev.d_private = &g_emac;
sam_ethgpioconfig(priv);
ret = sam_buffer_initialize(priv);
if (ret < 0)
{
nerr("ERROR: sam_buffer_initialize failed: %d\n", ret);
return;
}
* the interface is in the 'up' state.
*/
ret = irq_attach(SAM_IRQ_EMAC, sam_emac_interrupt, NULL);
if (ret < 0)
{
nerr("ERROR: Failed to attach the handler to the IRQ%d\n",
SAM_IRQ_EMAC);
goto errout_with_buffers;
}
sam_emac_enableclk();
ret = sam_ifdown(&priv->dev);
if (ret < 0)
{
nerr("ERROR: Failed to put the interface in the down state: %d\n",
ret);
goto errout_with_buffers;
}
ret = netdev_register(&priv->dev, NET_LL_ETHERNET);
if (ret >= 0)
{
return;
}
nerr("ERROR: netdev_register() failed: %d\n", ret);
errout_with_buffers:
sam_buffer_free(priv);
}
#endif