#
# For a description of the syntax of this configuration file,
# see the file kconfig-language.txt in the NuttX tools repository.
#

if ARCH_TRICORE
comment "Tricore Options"

choice
	prompt "Tricore Toolchain Selection"
	default TRICORE_TOOLCHAIN_GNU

config TRICORE_TOOLCHAIN_TASKING
	bool "AURIX Tasking C/C++ toolchain"
	select ARCH_TOOLCHAIN_TASKING

config TRICORE_TOOLCHAIN_GNU
	bool "Generic GNU toolchain"
	select ARCH_TOOLCHAIN_GNU
	---help---
		This option should work for any modern GNU toolchain (GCC 4.5 or newer)

endchoice # Tricore Toolchain Selection

config ARCH_TC1V6
	bool
	select ARCH_HAVE_MPU
	select ARCH_HAVE_IRQTRIGGER
	select ARCH_HAVE_PERF_EVENTS
	select ARCH_HAVE_POWEROFF
	select ARCH_HAVE_PERF_EVENTS_USER_ACCESS
	select ARCH_HAVE_SETJMP
	select ARCH_HAVE_RESET
	default n

config ARCH_TC1V8
	bool
	select ARCH_DCACHE
	select ARCH_ICACHE
	select ARCH_HAVE_MPU
	select ARCH_HAVE_IRQTRIGGER
	select ARCH_HAVE_PERF_EVENTS
	select ARCH_HAVE_PERF_EVENTS_USER_ACCESS
	select ARCH_HAVE_POWEROFF
	select ARCH_HAVE_PPRS
	select ARCH_HAVE_SETJMP
	select ARCH_HAVE_RESET
	default n

config ARCH_FAMILY
	string
	default "tc1v6"		if ARCH_TC1V6
	default "tc1v8"		if ARCH_TC1V8

config ARCH_CHIP_TC3XX
	bool "infineon aurix tc3xx"
	select ARCH_TC1V6
	select ARCH_HAVE_ADDRENV
	select ARCH_HAVE_MULTICPU
	select ARCH_HAVE_I2CRESET
	select ARCH_MINIMAL_VECTORTABLE
	select ARCH_MINIMAL_VECTORTABLE_DYNAMIC
	select ALARM_ARCH
	select ONESHOT
	select ONESHOT_COUNT
	---help---
		Infineon aurix tc3xx (six cores)

config ARCH_CHIP_TC4XX
	bool "infineon aurix tc4xx"
	select ARCH_TC1V8
	select ARCH_HAVE_ADDRENV
	select ARCH_HAVE_MULTICPU
	select ARCH_HAVE_I2CRESET
	select ARCH_MINIMAL_VECTORTABLE
	select ARCH_MINIMAL_VECTORTABLE_DYNAMIC
	select ALARM_ARCH
	select ONESHOT
	select ONESHOT_COUNT
	select HAVE_SECURITY_CORE
	---help---
		Infineon aurix tc4xx (six cores and one security core)

config ARCH_CHIP
	string
	default "tc3xx"		if ARCH_CHIP_TC3XX
	default "tc4xx"		if ARCH_CHIP_TC4XX

config ARCH_DCACHE_ADDR
	hex "AURIX Dcache base address"
	default 0x7003C000
	---help---
		AURIX Dcache base address, dcache line clear and invalidate need
		use thie address.

config ARCH_MPU_NSETS
	int "Protection sets number"
	default 7
	---help---
		The protection sets count

config ARCH_MPU_DATA_NREGIONS
	int "Data regions number"
	default 23
	---help---
		The data regions count

config ARCH_MPU_CODE_NREGIONS
	int "Code regions variables"
	default 15
	---help---
		The code regions count

config ARCH_HAVE_PPRS
	bool
	--help--
		The saving process for MPU PRS differs between TC1V6 and TC1V8.TC1V6
		saves PRS in the PSW, while TC1V8 saves PRS in the PPRS register.

config HAVE_SECURITY_CORE
	bool
	--help--
		In addition to the 6 cores, tc4xx also has one more security core.

if ARCH_CHIP_TC3XX
source "arch/tricore/src/tc3xx/Kconfig"
endif
endif # ARCH_TRICORE