* drivers/lcd/p14201.c
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <sys/types.h>
#include <stdint.h>
#include <stdbool.h>
#include <string.h>
#include <assert.h>
#include <errno.h>
#include <debug.h>
#include <nuttx/arch.h>
#include <nuttx/spi/spi.h>
#include <nuttx/lcd/lcd.h>
#include <nuttx/lcd/p14201.h>
#include <arch/irq.h>
#include "sd1329.h"
#ifdef CONFIG_LCD_P14201
* Pre-processor Definitions
****************************************************************************/
*
* CONFIG_P14201_SPIMODE - Controls the SPI mode
* CONFIG_P14201_FREQUENCY - Define to use a different bus frequency
* CONFIG_P14201_NINTERFACES - Specifies the number of physical P14201
* devices that will be supported.
* CONFIG_P14201_FRAMEBUFFER - If defined, accesses will be performed using
* an in-memory copy of the OLEDs GDDRAM. This cost of this buffer is
* 128 * 96 / 2 = 6Kb. If this is defined, then the driver will be fully
* functional. If not, then it will have the following limitations:
*
* - Reading graphics memory cannot be supported, and
* - All pixel writes must be aligned to byte boundaries.
*
* The latter limitation effectively reduces the 128x96 display to 64x96.
*
* Required LCD driver settings:
* CONFIG_LCD_P14201 - Enable P14201 support
* CONFIG_LCD_MAXCONTRAST should be 255, but any value >0 and <=255 will be
* accepted.
* CONFIG_LCD_MAXPOWER must be 1
*
* Required SPI driver settings:
* CONFIG_SPI_CMDDATA - Include support for cmd/data selection.
*/
#ifndef CONFIG_SPI_CMDDATA
# error "CONFIG_SPI_CMDDATA must be defined in your NuttX configuration"
#endif
* sometimes you need to tinker with these things.
*/
#ifndef CONFIG_P14201_SPIMODE
# define CONFIG_P14201_SPIMODE SPIDEV_MODE2
#endif
* that will be supported.
*/
#ifndef CONFIG_P14201_NINTERFACES
# define CONFIG_P14201_NINTERFACES 1
#endif
#if CONFIG_P14201_NINTERFACES != 1
# error "This implementation supports only a single OLED device"
#endif
#if !defined(CONFIG_LCD_MAXCONTRAST)
# define CONFIG_LCD_MAXCONTRAST 255
#endif
#if CONFIG_LCD_MAXCONTRAST <= 0|| CONFIG_LCD_MAXCONTRAST > 255
# error "CONFIG_LCD_MAXCONTRAST exceeds supported maximum"
#endif
#if !defined(CONFIG_LCD_MAXPOWER)
# define CONFIG_LCD_MAXPOWER 1
#endif
#if CONFIG_LCD_MAXPOWER != 1
# warning "CONFIG_LCD_MAXPOWER exceeds supported maximum"
# undef CONFIG_LCD_MAXPOWER
# define CONFIG_LCD_MAXPOWER 1
#endif
* (stuff you would never want to see unless you are debugging this file).
*
* Verbose debug must also be enabled
*/
#ifndef CONFIG_DEBUG_FEATURES
# undef CONFIG_DEBUG_INFO
# undef CONFIG_DEBUG_GRAPHICS
#endif
#ifndef CONFIG_DEBUG_INFO
# undef CONFIG_LCD_RITDEBUG
#endif
#define RIT_XRES 128
#define RIT_YRES 96
#define RIT_BPP 4
#define RIT_COLORFMT FB_FMT_Y4
#define RIT_CONTRAST ((23 * (CONFIG_LCD_MAXCONTRAST+1) / 32) - 1)
#define rit_sndcmd(p,b,l) rit_sndbytes(p,b,l,true);
#define rit_snddata(p,b,l) rit_sndbytes(p,b,l,false);
#ifdef CONFIG_LCD_RITDEBUG
# define riterr(format, ...) _err(format, ##__VA_ARGS__)
# define ritwarn(format, ...) _warn(format, ##__VA_ARGS__)
# define ritinfo(format, ...) _info(format, ##__VA_ARGS__)
#else
# define riterr(x...)
# define ritwarn(x...)
# define ritinfo(x...)
#endif
* Private Type Definition
****************************************************************************/
struct rit_dev_s
{
struct lcd_dev_s dev;
FAR struct spi_dev_s *spi;
uint8_t contrast;
bool on;
};
* Private Function Protototypes
****************************************************************************/
static void rit_select(FAR struct spi_dev_s *spi);
static void rit_deselect(FAR struct spi_dev_s *spi);
static void rit_sndbytes(FAR struct rit_dev_s *priv,
FAR const uint8_t *buffer,
size_t buflen, bool cmd);
static void rit_sndcmds(FAR struct rit_dev_s *priv,
FAR const uint8_t *table);
static int rit_putrun(FAR struct lcd_dev_s *dev,
fb_coord_t row, fb_coord_t col,
FAR const uint8_t *buffer,
size_t npixels);
static int rit_getrun(FAR struct lcd_dev_s *dev,
fb_coord_t row, fb_coord_t col,
FAR uint8_t *buffer,
size_t npixels);
static int rit_getvideoinfo(FAR struct lcd_dev_s *dev,
FAR struct fb_videoinfo_s *vinfo);
static int rit_getplaneinfo(FAR struct lcd_dev_s *dev,
unsigned int planeno,
FAR struct lcd_planeinfo_s *pinfo);
#ifdef CONFIG_FB_CMAP
# error "RGB color mapping not supported by this driver"
#endif
#ifdef CONFIG_FB_HWCURSOR
# error "Cursor control not supported by this driver"
#endif
static int rit_getpower(struct lcd_dev_s *dev);
static int rit_setpower(struct lcd_dev_s *dev, int power);
static int rit_getcontrast(struct lcd_dev_s *dev);
static int rit_setcontrast(struct lcd_dev_s *dev, unsigned int contrast);
* Private Data
****************************************************************************/
* and for each color plane. This memory will hold one raster line of data.
* The size of the allocated run buffer must therefore be at least
* (bpp * xres / 8). Actual alignment of the buffer must conform to the
* bitwidth of the underlying pixel type.
*
* If there are multiple planes, they may share the same working buffer
* because different planes will not be operate on concurrently. However,
* if there are multiple LCD devices, they must each have unique run buffers.
*/
static uint8_t g_runbuffer[RIT_XRES / 2];
* an in-memory copy of the OLEDs GDDRAM. This cost of this buffer is
* 128 * 64 / 2 = 4Kb. If this is defined, then the driver will be full
* functional. If not, then:
*
* - Reading graphics memory cannot be supported, and
* - All pixel writes must be aligned to byte boundaries.
*/
#ifdef CONFIG_P14201_FRAMEBUFFER
static uint8_t g_framebuffer[RIT_YRES * RIT_XRES / 2];
#endif
static const struct fb_videoinfo_s g_videoinfo =
{
.fmt = RIT_COLORFMT,
.xres = RIT_XRES,
.yres = RIT_YRES,
.nplanes = 1,
};
static const struct lcd_planeinfo_s g_planeinfo =
{
.putrun = rit_putrun,
.getrun = rit_getrun,
.buffer = (FAR uint8_t *)g_runbuffer,
.bpp = RIT_BPP,
};
* (only a single device is supported for now)
*/
static struct rit_dev_s g_oleddev =
{
.dev =
{
.getvideoinfo = rit_getvideoinfo,
.getplaneinfo = rit_getplaneinfo,
.getpower = rit_getpower,
.setpower = rit_setpower,
.getcontrast = rit_getcontrast,
.setcontrast = rit_setcontrast,
},
};
* derived from RiT Application Note for the P14201 (with a few tweaked
* values as discovered in some Luminary code examples).
*/
static const uint8_t g_initcmds[] =
{
3, SSD1329_CMD_LOCK,
SSD1329_LOCK_OFF,
SSD1329_NOOP,
2, SSD1329_SLEEP_ON,
SSD1329_NOOP,
3, SSD1329_ICON_ALL,
SSD1329_ICON_OFF,
SSD1329_NOOP,
3, SSD1329_MUX_RATIO,
95,
SSD1329_NOOP,
3, SSD1329_SET_CONTRAST,
RIT_CONTRAST,
SSD1329_NOOP,
3, SSD1329_PRECHRG2_SPEED,
(31 << 1) | SSD1329_PRECHRG2_DBL,
SSD1329_NOOP,
3, SSD1329_GDDRAM_REMAP,
(SSD1329_COM_SPLIT |
SSD1329_COM_REMAP |
SSD1329_NIBBLE_REMAP),
SSD1329_NOOP,
3, SSD1329_VERT_START,
0,
SSD1329_NOOP,
3, SSD1329_VERT_OFFSET,
0,
SSD1329_NOOP,
2, SSD1329_DISP_NORMAL,
SSD1329_NOOP,
3, SSD1329_PHASE_LENGTH,
1 |
(1 << 4),
SSD1329_NOOP,
3, SSD1329_FRAME_FREQ,
35,
SSD1329_NOOP,
3, SSD1329_DCLK_DIV,
2 |
(14 << 4),
SSD1329_NOOP,
17, SSD1329_GSCALE_LOOKUP,
1, 2, 3, 4, 5,
6, 8, 10, 12, 14,
16, 19, 22, 26, 30,
SSD1329_NOOP,
3, SSD1329_PRECHRG2_PERIOD,
1,
SSD1329_NOOP,
3, SSD1329_PRECHRG1_VOLT,
0x3f,
SSD1329_NOOP,
0
};
static const uint8_t g_sleepoff[] =
{
SSD1329_SLEEP_OFF,
SSD1329_NOOP,
};
static const uint8_t g_sleepon[] =
{
SSD1329_SLEEP_ON,
SSD1329_NOOP,
};
static const uint8_t g_horzinc[] =
{
SSD1329_GDDRAM_REMAP,
(SSD1329_COM_SPLIT | SSD1329_COM_REMAP | SSD1329_NIBBLE_REMAP),
};
static const uint8_t g_setallcol[] =
{
SSD1329_SET_COLADDR,
0,
(RIT_XRES / 2) - 1
};
static const uint8_t g_setallrow[] =
{
SSD1329_SET_ROWADDR,
0,
RIT_YRES - 1
};
* Private Functions
****************************************************************************/
* Name: rit_select
*
* Description:
* Select the SPI, locking and re-configuring if necessary
*
* Input Parameters:
* spi - Reference to the SPI driver structure
*
* Returned Value:
* None
*
* Assumptions:
*
****************************************************************************/
static void rit_select(FAR struct spi_dev_s *spi)
{
* devices competing for the SPI bus
*/
SPI_LOCK(spi, true);
SPI_SELECT(spi, SPIDEV_DISPLAY(0), true);
* might have gotten configured for a different device while unlocked)
*/
SPI_SETMODE(spi, CONFIG_P14201_SPIMODE);
SPI_SETBITS(spi, 8);
SPI_HWFEATURES(spi, 0);
#ifdef CONFIG_P14201_FREQUENCY
SPI_SETFREQUENCY(spi, CONFIG_P14201_FREQUENCY);
#endif
}
* Name: rit_deselect
*
* Description:
* De-select the SPI
*
* Input Parameters:
* spi - Reference to the SPI driver structure
*
* Returned Value:
* None
*
* Assumptions:
*
****************************************************************************/
static void rit_deselect(FAR struct spi_dev_s *spi)
{
SPI_SELECT(spi, SPIDEV_DISPLAY(0), false);
SPI_LOCK(spi, false);
}
* Name: rit_sndbytes
*
* Description:
* Send a sequence of command or data bytes to the SSD1329 controller.
*
* Input Parameters:
* spi - Reference to the SPI driver structure
* buffer - A reference to memory containing the command bytes to be sent.
* buflen - The number of command bytes in buffer to be sent
*
* Returned Value:
* None
*
* Assumptions:
* The caller as selected the OLED device.
*
****************************************************************************/
static void rit_sndbytes(FAR struct rit_dev_s *priv,
FAR const uint8_t *buffer,
size_t buflen, bool cmd)
{
FAR struct spi_dev_s *spi = priv->spi;
uint8_t tmp;
ritinfo("buflen: %d cmd: %s [%02x %02x %02x]\n",
buflen, cmd ? "YES" : "NO", buffer[0], buffer[1], buffer[2]);
DEBUGASSERT(spi);
SPI_CMDDATA(spi, SPIDEV_DISPLAY(0), cmd);
while (buflen-- > 0)
{
tmp = *buffer++;
SPI_SEND(spi, tmp);
}
}
* Name: rit_sndcmd
*
* Description:
* Send multiple commands from a table of commands.
*
* Input Parameters:
* spi - Reference to the SPI driver structure
* table - A reference to table containing all of the commands to be sent.
*
* Returned Value:
* None
*
* Assumptions:
*
****************************************************************************/
static void rit_sndcmds(FAR struct rit_dev_s *priv, FAR const uint8_t *table)
{
int cmdlen;
while ((cmdlen = *table++) != 0)
{
ritinfo("command: %02x cmdlen: %d\n", *table, cmdlen);
rit_sndcmd(priv, table, cmdlen);
table += cmdlen;
}
}
* Name: rit_clear
*
* Description:
* This method can be used to clear the entire display.
*
* Input Parameters:
* priv - Reference to private driver structure
*
* Assumptions:
* Caller has selected the OLED section.
*
****************************************************************************/
#ifdef CONFIG_P14201_FRAMEBUFFER
static inline void rit_clear(FAR struct rit_dev_s *priv)
{
FAR uint8_t *ptr = g_framebuffer;
unsigned int row;
ritinfo("Clear display\n");
memset(g_framebuffer,
(RIT_Y4_BLACK << 4) | RIT_Y4_BLACK,
RIT_YRES * RIT_XRES / 2);
rit_sndcmd(priv, g_setallcol, sizeof(g_setallcol));
rit_sndcmd(priv, g_setallrow, sizeof(g_setallrow));
rit_sndcmd(priv, g_horzinc, sizeof(g_horzinc));
for (row = 0; row < RIT_YRES; row++)
{
rit_snddata(priv, ptr, RIT_XRES / 2);
ptr += RIT_XRES / 2;
}
}
#else
static inline void rit_clear(FAR struct rit_dev_s *priv)
{
unsigned int row;
ritinfo("Clear display\n");
memset(g_runbuffer, (RIT_Y4_BLACK << 4) | RIT_Y4_BLACK, RIT_XRES / 2);
rit_sndcmd(priv, g_setallcol, sizeof(g_setallcol));
rit_sndcmd(priv, g_setallrow, sizeof(g_setallrow));
rit_sndcmd(priv, g_horzinc, sizeof(g_horzinc));
for (row = 0; row < RIT_YRES; row++)
{
rit_snddata(priv, g_runbuffer, RIT_XRES / 2);
}
}
#endif
* Name: rit_putrun
*
* Description:
* This method can be used to write a partial raster line to the LCD.
*
* Input Parameters:
* dev - The lcd device
* row - Starting row to write to (range: 0 <= row < yres)
* col - Starting column to write to (range: 0 <= col <= xres-npixels)
* buffer - The buffer containing the run to be written to the LCD
* npixels - The number of pixels to write to the LCD
* (range: 0 < npixels <= xres-col)
*
****************************************************************************/
#ifdef CONFIG_P14201_FRAMEBUFFER
static int rit_putrun(FAR struct lcd_dev_s *dev,
fb_coord_t row, fb_coord_t col,
FAR const uint8_t *buffer,
size_t npixels)
{
FAR struct rit_dev_s *priv = (FAR struct rit_dev_s *)dev;
uint8_t cmd[3];
uint8_t *run;
int start;
int end;
int aend;
int i;
ritinfo("row: %d col: %d npixels: %d\n", row, col, npixels);
DEBUGASSERT(buffer);
if (npixels < 1)
{
return OK;
}
run = g_framebuffer + row * RIT_XRES / 2;
* the run starts at &run[start] and continues through run[end-1].
* However, the first and final pixels at these locations may
* not be byte aligned.
*/
start = col >> 1;
aend = (col + npixels) >> 1;
end = (col + npixels + 1) >> 1;
ritinfo("start: %d aend: %d end: %d\n", start, aend, end);
*
* CASE 1: First pixel X position is byte aligned
*
* example col=6 npixels = 8 example col=6 npixels=7
*
* Run: |AB|AB|AB|AB| |AB|AB|AB|AB|
* GDDRAM row:
* Byte | 0| 1| 2| 3| 4| 5| 6| | 0| 1| 2| 3| 4| 5| 6|
* Pixel: |--|--|--|AB|AB|AB|AB| |--|--|--|AB|AB|AB|A-|
*
* start = 3 start = 3
* aend = 6 aend = 6
* end = 6 end = 7
*
*/
if ((col & 1) == 0)
{
if (npixels > 1)
{
memcpy(&run[start], buffer, aend - start);
}
* zero counts as an even number). If npixels was was odd (including
* npixels == 1), then handle the final, byte aligned pixel.
*/
if (aend != end)
{
* destination bits 7:4
*/
run[aend] = (run[aend] & 0x0f) | (buffer[aend - start] & 0xf0);
}
}
*
* example col=7 npixels = 8 example col=7 npixels=7
*
* Run: |AB|AB|AB|AB| |AB|AB|AB|AB|
* GDDRAM row:
* Byte | 0| 1| 2| 3| 4| 5| 6| 7| | 0| 1| 2| 3| 4| 5| 6|
* Pixel: |--|--|--|-A|BA|BA|BA|B-| |--|--|--|-A|BA|BA|BA|
*
* start = 3 start = 3
* aend = 7 aend = 7
* end = 8 end = 7
*/
else
{
uint8_t curr = buffer[0];
uint8_t last;
* destination bits 3:0. In the special case of npixel == 1,
* this finished the job.
*/
run[start] = (run[start] & 0xf0) | (curr >> 4);
* casing the final, partial byte below).
*/
for (i = start + 1; i < aend; i++)
{
* bits 7:4 of current byte to run bits 3:0
*/
last = curr;
curr = buffer[i - start];
run[i] = (last << 4) | (curr >> 4);
}
* may have been as small as one). If npixels was was even, then
* handle the final, unaligned pixel.
*/
if (aend != end)
{
* destination bits 7:4
*/
run[aend] = (run[aend] & 0x0f) | (curr << 4);
}
}
rit_select(priv->spi);
* and row, and ending at the column + npixels on the same row.
*/
cmd[0] = SSD1329_SET_COLADDR;
cmd[1] = start;
cmd[2] = end - 1;
rit_sndcmd(priv, cmd, 3);
cmd[0] = SSD1329_SET_ROWADDR;
cmd[1] = row;
cmd[2] = row;
rit_sndcmd(priv, cmd, 3);
rit_sndcmd(priv, g_horzinc, sizeof(g_horzinc));
rit_snddata(priv, &run[start], end - start);
rit_deselect(priv->spi);
return OK;
}
#else
static int rit_putrun(FAR struct lcd_dev_s *dev,
fb_coord_t row, fb_coord_t col,
FAR const uint8_t *buffer,
size_t npixels)
{
FAR struct rit_dev_s *priv = (FAR struct rit_dev_s *)dev;
uint8_t cmd[3];
ritinfo("row: %d col: %d npixels: %d\n", row, col, npixels);
DEBUGASSERT(buffer);
if (npixels > 0)
{
DEBUGASSERT(col < RIT_XRES &&
(col + npixels) <= RIT_XRES &&
row < RIT_YRES);
* (this needs to get fixed somehow)
*/
DEBUGASSERT((col & 1) == 0 && (npixels & 1) == 0);
rit_select(priv->spi);
* and row, and ending at the column + npixels on the same row.
*/
cmd[0] = SSD1329_SET_COLADDR;
cmd[1] = col >> 1;
cmd[2] = ((col + npixels) >> 1) - 1;
rit_sndcmd(priv, cmd, 3);
cmd[0] = SSD1329_SET_ROWADDR;
cmd[1] = row;
cmd[2] = row;
rit_sndcmd(priv, cmd, 3);
rit_sndcmd(priv, g_horzinc, sizeof(g_horzinc));
rit_snddata(priv, buffer, npixels >> 1);
rit_deselect(priv->spi);
}
return OK;
}
#endif
* Name: rit_getrun
*
* Description:
* This method can be used to read a partial raster line from the LCD:
*
* dev - The lcd device
* row - Starting row to read from (range: 0 <= row < yres)
* col - Starting column to read read (range: 0 <= col <= xres-npixels)
* buffer - The buffer in which to return the run read from the LCD
* npixels - The number of pixels to read from the LCD
* (range: 0 < npixels <= xres-col)
*
****************************************************************************/
#ifdef CONFIG_P14201_FRAMEBUFFER
static int rit_getrun(FAR struct lcd_dev_s *dev,
fb_coord_t row, fb_coord_t col,
FAR uint8_t *buffer,
size_t npixels)
{
uint8_t *run;
int start;
int end;
int aend;
int i;
ritinfo("row: %d col: %d npixels: %d\n", row, col, npixels);
DEBUGASSERT(buffer);
* framebuffer
*/
if (npixels < 1)
{
return OK;
}
run = g_framebuffer + row * RIT_XRES / 2;
* the run starts at &run[start] and continues through run[end-1].
* However, the first and final pixels at these locations may
* not be byte aligned (see examples in putrun()).
*/
start = col >> 1;
aend = (col + npixels) >> 1;
end = (col + npixels + 1) >> 1;
if ((col & 1) == 0)
{
if (npixels > 1)
{
memcpy(buffer, &run[start], aend - start + 1);
}
* (including the special case where npixels == 1).
*/
if (aend != end)
{
* destination bits 7:4
*/
buffer[aend - start] = run[aend] & 0xf0;
}
}
else
{
uint8_t curr = run[start];
uint8_t last;
* casing the final, partial byte below).
*/
for (i = start + 1; i < aend; i++)
{
* bits 7:4 of current byte to run bits 3:0
*/
last = curr;
curr = run[i];
*buffer++ = (last << 4) | (curr >> 4);
}
* (including the special case where npixels == 1).
*/
if (aend != end)
{
* destination bits 7:4
*/
*buffer = (curr << 4);
}
}
return OK;
}
#else
static int rit_getrun(FAR struct lcd_dev_s *dev, fb_coord_t row,
fb_coord_t col, FAR uint8_t *buffer, size_t npixels)
{
return -ENOSYS;
}
#endif
* Name: rit_getvideoinfo
*
* Description:
* Get information about the LCD video controller configuration.
*
****************************************************************************/
static int rit_getvideoinfo(FAR struct lcd_dev_s *dev,
FAR struct fb_videoinfo_s *vinfo)
{
DEBUGASSERT(dev && vinfo);
ginfo("fmt: %d xres: %d yres: %d nplanes: %d\n",
g_videoinfo.fmt, g_videoinfo.xres,
g_videoinfo.yres, g_videoinfo.nplanes);
memcpy(vinfo, &g_videoinfo, sizeof(struct fb_videoinfo_s));
return OK;
}
* Name: rit_getplaneinfo
*
* Description:
* Get information about the configuration of each LCD color plane.
*
****************************************************************************/
static int rit_getplaneinfo(FAR struct lcd_dev_s *dev,
unsigned int planeno,
FAR struct lcd_planeinfo_s *pinfo)
{
DEBUGASSERT(pinfo && planeno == 0);
ginfo("planeno: %d bpp: %d\n", planeno, g_planeinfo.bpp);
memcpy(pinfo, &g_planeinfo, sizeof(struct lcd_planeinfo_s));
pinfo->dev = dev;
return OK;
}
* Name: rit_getpower
*
* Description:
* Get the LCD panel power status
* (0: full off - CONFIG_LCD_MAXPOWER: full on.
* On backlit LCDs, this setting may correspond to the backlight setting.
*
****************************************************************************/
static int rit_getpower(FAR struct lcd_dev_s *dev)
{
FAR struct rit_dev_s *priv = (FAR struct rit_dev_s *)dev;
DEBUGASSERT(priv);
ginfo("power: %s\n", priv->on ? "ON" : "OFF");
return priv->on ? CONFIG_LCD_MAXPOWER : 0;
}
* Name: rit_setpower
*
* Description:
* Enable/disable LCD panel power
* (0: full off - CONFIG_LCD_MAXPOWER: full on).
* On backlit LCDs, this setting may correspond to the backlight setting.
*
****************************************************************************/
static int rit_setpower(struct lcd_dev_s *dev, int power)
{
struct rit_dev_s *priv = (struct rit_dev_s *)dev;
DEBUGASSERT(priv && (unsigned)power <= CONFIG_LCD_MAXPOWER && priv->spi);
ginfo("power: %d\n", power);
rit_select(priv->spi);
if (power > 0)
{
rit_sndcmds(priv, g_initcmds);
rit_sndcmd(priv, g_sleepoff, sizeof(g_sleepoff));
priv->on = true;
}
else
{
rit_sndcmd(priv, g_sleepon, sizeof(g_sleepon));
priv->on = false;
}
rit_deselect(priv->spi);
return OK;
}
* Name: rit_getcontrast
*
* Description:
* Get the current contrast setting (0-CONFIG_LCD_MAXCONTRAST).
*
****************************************************************************/
static int rit_getcontrast(struct lcd_dev_s *dev)
{
struct rit_dev_s *priv = (struct rit_dev_s *)dev;
ginfo("contrast: %d\n", priv->contrast);
return priv->contrast;
}
* Name: rit_setcontrast
*
* Description:
* Set LCD panel contrast (0-CONFIG_LCD_MAXCONTRAST).
*
****************************************************************************/
static int rit_setcontrast(struct lcd_dev_s *dev, unsigned int contrast)
{
struct rit_dev_s *priv = (struct rit_dev_s *)dev;
uint8_t cmd[3];
ginfo("contrast: %d\n", contrast);
DEBUGASSERT(contrast <= CONFIG_LCD_MAXCONTRAST);
rit_select(priv->spi);
cmd[0] = SSD1329_SET_CONTRAST;
cmd[1] = contrast;
cmd[2] = SSD1329_NOOP;
rit_sndcmd(priv, cmd, 3);
rit_deselect(priv->spi);
priv->contrast = contrast;
return OK;
}
* Public Functions
****************************************************************************/
* Name: rit_initialize
*
* Description:
* Initialize the P14201 video hardware.
* The initial state of the OLED is fully initialized, display memory
* cleared, and the OLED ready to use, but with the power setting at 0
* (full off == sleep mode).
*
* Input Parameters:
* spi - A reference to the SPI driver instance.
* devno - A value in the range of 0 through CONFIG_P14201_NINTERFACES-1.
* This allows support for multiple OLED devices.
*
* Returned Value:
* On success, this function returns a reference to the LCD object for the
* specified OLED. NULL is returned on any failure.
*
****************************************************************************/
FAR struct lcd_dev_s *rit_initialize(FAR struct spi_dev_s *spi,
unsigned int devno)
{
FAR struct rit_dev_s *priv = (FAR struct rit_dev_s *)&g_oleddev;
DEBUGASSERT(devno == 0 && spi);
ginfo("Initializing devno: %d\n", devno);
priv->spi = spi;
priv->contrast = RIT_CONTRAST;
priv->on = false;
rit_select(spi);
rit_clear(priv);
rit_sndcmds(priv, g_initcmds);
rit_deselect(spi);
return &priv->dev;
}
#endif