| 文件 | 最后提交记录 | 最后更新时间 |
|---|---|---|
arm_a_r: merge arm_prefetchabort.c to arm_a_r Signed-off-by: hujun5 <hujun5@xiaomi.com> | 2 个月前 | |
arch/armv8-r: add GICv2 This adds GICv2 support in armv8-r. Selection of GIC version is done via ARM_GIC_VERSION config from now on. Signed-off-by: Yanfeng Liu <p-liuyanfeng9@xiaomi.com> | 2 个月前 | |
arm_a_r: merge arm_prefetchabort.c to arm_a_r Signed-off-by: hujun5 <hujun5@xiaomi.com> | 2 个月前 | |
armv8-r:cmake use -march inside of -mcpu Avoid specifying both the architecture ( -march) and the processor ( -mcpu) because specifying both has the potential to cause a conflict. The compiler infers the correct architecture from the processor. Documentation:https://developer.arm.com/documentation/101754/0624/armclang-Reference/armclang-Command-line-Options/-march?lang=en Signed-off-by: anjiahao <anjiahao@xiaomi.com> | 2 个月前 | |
Protect:use MPU to protect elf_fixup apps global data Signed-off-by: anjiahao <anjiahao@xiaomi.com> | 2 个月前 | |
arch/arm/arm_cache: remove not required critical_section Signed-off-by: buxiasen <buxiasen@xiaomi.com> | 2 个月前 | |
qemu/arm_a_r: use cp15 as percpu offset Should avoid touch cpuid in userspace, optimze reduce the offset*cpuid Signed-off-by: buxiasen <buxiasen@xiaomi.com> | 2 个月前 | |
arch/arm/armv8-r: add compatible for NCPUS > 1 but UP We use SMP like method to do AMP, need NCPUS > 1 but not BMP, this patch for compatible, revert this patch later Signed-off-by: buxiasen <buxiasen@xiaomi.com> | 2 个月前 | |
Merge branch 'master' into vela apache/nuttx commit id: eb27ebba8adfe29644a7b890f86e6f16941921dc Signed-off-by: ligd <liguiding1@xiaomi.com> Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com> | 2 个月前 | |
qemu/armv8-r: replace SMP_NCPUS to NCPUS Signed-off-by: buxiasen <buxiasen@xiaomi.com> | 2 个月前 | |
dns: fix dns failed when ipv4/6 dual stack enable The ipv6 address filled the cache, and the ipv4 address did not have a place to store it, causing the resolution to fail. so if IPV6 has already filled the buffer, rewrite ipv4 DNS results from half of the buffer. Signed-off-by: zhanghongyu <zhanghongyu@xiaomi.com> | 2 个月前 | |
Merge branch 'master' into vela apache/nuttx commit id: eb27ebba8adfe29644a7b890f86e6f16941921dc Signed-off-by: ligd <liguiding1@xiaomi.com> Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com> | 2 个月前 | |
arch/armv8-r: enable smp_call when BMP Reference: https://developer.arm.com/documentation/ddi0516/c/programmers-model/distributor-register-summary [h] GICD_ISENABLER0 is a mixed type register. [i] GICD_ISENABLER0 SGI bits are RO, PPI bits are RW. [j] The reset value for the register that contains the SGI and PPI interrupts is 0x0000FFFF because SGIs are always enabled. However, SGIs areGroup 0 on reset, so the reset value for Non-secure reads is 0x00000000. Signed-off-by: buxiasen <buxiasen@xiaomi.com> | 2 个月前 | |
arch/armv8-r: fix GICv2M issues This fixes build and missing initialization call issues. Signed-off-by: Yanfeng Liu <p-liuyanfeng9@xiaomi.com> | 2 个月前 | |
arch/armv8-r: enable smp_call when BMP Reference: https://developer.arm.com/documentation/ddi0516/c/programmers-model/distributor-register-summary [h] GICD_ISENABLER0 is a mixed type register. [i] GICD_ISENABLER0 SGI bits are RO, PPI bits are RW. [j] The reset value for the register that contains the SGI and PPI interrupts is 0x0000FFFF because SGIs are always enabled. However, SGIs areGroup 0 on reset, so the reset value for Non-secure reads is 0x00000000. Signed-off-by: buxiasen <buxiasen@xiaomi.com> | 2 个月前 | |
qemu/arm_a_r: use cp15 as percpu offset Should avoid touch cpuid in userspace, optimze reduce the offset*cpuid Signed-off-by: buxiasen <buxiasen@xiaomi.com> | 2 个月前 | |
arch/arm/arm_a_r: use up_cpu_idlestack when up_initail_state Align idlestack init between UP AMP BMP. Signed-off-by: buxiasen <buxiasen@xiaomi.com> | 2 个月前 | |
arch/arm: update all ARM_DSB/ISB to UP_DSB/ISB Fix error: implicit declaration of funciton 'ARM_DSB' [-Werror=implict-funciton-decaration] Signed-off-by: buxiasen <buxiasen@xiaomi.com> | 2 个月前 | |
qemu/armv8-r: add Bound Multi-Processing (BMP) support Run qemu with: bash qemu-system-arm -M virt,virtualization=on,highmem=off \ -semihosting -nographic -cpu cortex-r52 \ -device loader,file=./nuttx/nuttx -smp 4 Change core by cu -l /dev/ttyCORE1, etc. Signed-off-by: chao an <anchao@lixiang.com> Signed-off-by: buxiasen <buxiasen@xiaomi.com> | 2 个月前 | |
perf: add noinstrument_function to up_perf_gettime and related functions Add noinstrument_function attribute to up_perf_gettime and its helper functions (like cp15_pmu_rdccr) across all architectures. These functions are called by perf_gettime which is used in the instrument callback path, and must not be instrumented to avoid infinite recursion when CONFIG_ARCH_INSTRUMENT_ALL is enabled. Signed-off-by: yezhonghui <yezhonghui@xiaomi.com> | 2 个月前 | |
dns: fix dns failed when ipv4/6 dual stack enable The ipv6 address filled the cache, and the ipv4 address did not have a place to store it, causing the resolution to fail. so if IPV6 has already filled the buffer, rewrite ipv4 DNS results from half of the buffer. Signed-off-by: zhanghongyu <zhanghongyu@xiaomi.com> | 2 个月前 | |
arch/arm/arm_scu: skip cpu0 wait current_task updated After g_assignedtasks change from .data to .bss, we should no longer wait current_task updated in core0 when SMP. Also the up_update_task will be called in nx_start, when UP & BMP Signed-off-by: buxiasen <buxiasen@xiaomi.com> | 2 个月前 | |
arch/armv8-r: enable smp_call when BMP Reference: https://developer.arm.com/documentation/ddi0516/c/programmers-model/distributor-register-summary [h] GICD_ISENABLER0 is a mixed type register. [i] GICD_ISENABLER0 SGI bits are RO, PPI bits are RW. [j] The reset value for the register that contains the SGI and PPI interrupts is 0x0000FFFF because SGIs are always enabled. However, SGIs areGroup 0 on reset, so the reset value for Non-secure reads is 0x00000000. Signed-off-by: buxiasen <buxiasen@xiaomi.com> | 2 个月前 | |
driver/timers: Simplify the up_timer_initialize. This commit simplified the up_timer_initialize. Signed-off-by: ouyangxiangzhen <ouyangxiangzhen@xiaomi.com> | 2 个月前 | |
arm_a_r: merge cp15.h to arm_a_r Signed-off-by: hujun5 <hujun5@xiaomi.com> | 2 个月前 | |
arm: remove up_set_current_regs/up_current_regs reason: up_set_current_regs initially had two functions: 1: To mark the entry into an interrupt state. 2: To record the context before an interrupt/exception. If we switch to a new task, we need to store the upcoming context regs by calling up_set_current_regs(regs). Currently, we record the context in other ways, so the second function is obsolete. Therefore, we need to rename up_set_current_regs to better reflect its actual meaning, which is solely to mark an interrupt. Signed-off-by: hujun5 <hujun5@xiaomi.com> | 2 个月前 | |
arch: add signal disabled support in interrupt handling impl When the signal functionality is turned off, there is no need to allocate additional stack space for the signal handling process. Signed-off-by: guoshichao <guoshichao@xiaomi.com> | 2 个月前 | |
arch/armv8-r: fix SMP build This fixes build issues of SMP support. Signed-off-by: Yanfeng Liu <p-liuyanfeng9@xiaomi.com> | 2 个月前 | |
arch/arm:use UP_DSB, UP_DMB, UP_ISB as barrier standard API Signed-off-by: lipengfei28 <lipengfei28@xiaomi.com> | 2 个月前 | |
armv8-r: change the wrong use of mrc to mcr Signed-off-by: zhangyuan29 <zhangyuan29@xiaomi.com> | 2 个月前 | |
qemu/armv8-r: replace SMP_NCPUS to NCPUS Signed-off-by: buxiasen <buxiasen@xiaomi.com> | 2 个月前 | |
arm/armv8-r: Adding a cache interface to armv8-r Summary: 1. Add up_get_icache_size、up_get_dcache_size 2. Added L2 cahce PL310 implementation Signed-off-by: wangming9 <wangming9@xiaomi.com> | 2 个月前 | |
arm/armv8-r: Adding a cache interface to armv8-r Summary: 1. Add up_get_icache_size、up_get_dcache_size 2. Added L2 cahce PL310 implementation Signed-off-by: wangming9 <wangming9@xiaomi.com> | 2 个月前 | |
arch/armv8-r: add GICv2 This adds GICv2 support in armv8-r. Selection of GIC version is done via ARM_GIC_VERSION config from now on. Signed-off-by: Yanfeng Liu <p-liuyanfeng9@xiaomi.com> | 2 个月前 | |
qemu/armv8-r: add support for BMP protected 4 cpus Run qemu with: bash qemu-system-arm -M virt,virtualization=on,highmem=off \ -semihosting -nographic -cpu cortex-r52 \ -device loader,file=./nuttx/nuttx \ -device loader,file=./nuttx/nuttx_user \ -smp 4 Change core by cu -l /dev/ttyCORE1, etc. Signed-off-by: buxiasen <buxiasen@xiaomi.com> | 2 个月前 | |
arch/armv8-r: add SMP sources This adds SMP related sources to armv8-r mostly from armv7-r. The cpuhead.S is tweaked to support EL2 settings then switch to EL1. Signed-off-by: Yanfeng Liu <p-liuyanfeng9@xiaomi.com> | 2 个月前 | |
qemu/armv8-r: replace SMP_NCPUS to NCPUS Signed-off-by: buxiasen <buxiasen@xiaomi.com> | 2 个月前 |
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