| 文件 | 最后提交记录 | 最后更新时间 |
|---|---|---|
arch: change all g_interrupt_context to percpu Signed-off-by: buxiasen <buxiasen@xiaomi.com> | 2 个月前 | |
arch/esp32s3: The MISO, MOSI and C/S are optional The MISO or MOSI pin is optional. The C/S pin is unnecessary when ESP32S3_SPI_UDCS is enabled. Signed-off-by: wangjianyu3 <wangjianyu3@xiaomi.com> | 2 个月前 | |
mm: Fix some typos Signed-off-by: xuxingliang <xuxingliang@xiaomi.com> | 2 个月前 | |
nuttx/atomic: For rc04 Apache-Ci, some chips that do not support atomic operations, select LIBC_ATOMIC_IRQ. The following types are not supported: 1. ARCH_ARMV6M, ARCH_ARM7TDMI, and ARCH_ARM926EJS architectures are not supported by the architecture itself. 2. Single-core CPUs, such as ARCH_CHIP_BM3823. 3. Special chips are not supported, such as ARCH_CHIP_RV32M1(RISV32). for special chips have hwspinlock, l'm working for it. Signed-off-by: zhangyu117 <zhangyu117@xiaomi.com> | 2 个月前 |