Oopenvela-robotsched/misc: fix stack dump format and update parser
| 文件 | 最后提交记录 | 最后更新时间 |
|---|---|---|
Merge branch 'master' into vela apache/nuttx commit id: eb27ebba8adfe29644a7b890f86e6f16941921dc Signed-off-by: ligd <liguiding1@xiaomi.com> Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com> | 2 个月前 | |
coredump:Move coredump to sched/misc 1. move coredump form libelf to sched/misc 2. rename core_dump to coredump Signed-off-by: anjiahao <anjiahao@xiaomi.com> | 2 个月前 | |
sched/misc: fix stack dump format and update parser Add colon separator after address in stack dump output to improve readability and distinguish the address field from stack values. Update the nxstub parser regex to handle flexible whitespace before the address, ensuring it correctly parses the updated stack dump format. Signed-off-by: xuxingliang <xuxingliang@xiaomi.com> | 2 个月前 | |
Revert tricore coredump register handling changes Revert two commits that introduced special register handling for tricore architecture: - f0006bec "coredump.c:make the registers saved by active assert consistent with those in the coredump" - 5835c0ed "coredump: fix tricore coredump not working" Reason: Tricore has an ordinary register context layout similar to other architectures and doesn't require up_copyusercontext. The current implementation where tcb->xcp.regs points to the upper register causes the lower CSA to be lost (the last CSA is located 0x40 bytes above the upper CSA). Treating tricore consistently with other architectures allows all registers to be accessed correctly via g_reginfo.toffset, providing a unified solution. Signed-off-by: xuxingliang <xuxingliang@xiaomi.com> | 2 个月前 | |
Revert tricore coredump register handling changes Revert two commits that introduced special register handling for tricore architecture: - f0006bec "coredump.c:make the registers saved by active assert consistent with those in the coredump" - 5835c0ed "coredump: fix tricore coredump not working" Reason: Tricore has an ordinary register context layout similar to other architectures and doesn't require up_copyusercontext. The current implementation where tcb->xcp.regs points to the upper register causes the lower CSA to be lost (the last CSA is located 0x40 bytes above the upper CSA). Treating tricore consistently with other architectures allows all registers to be accessed correctly via g_reginfo.toffset, providing a unified solution. Signed-off-by: xuxingliang <xuxingliang@xiaomi.com> | 2 个月前 | |
sched/spinlock: Debug tools for spinlock. Automatically find deadspinlock when assert. Signed-off-by: wangzhi16 <wangzhi16@xiaomi.com> | 2 个月前 | |
bmp/sched: add bmp support Signed-off-by: buxiasen <buxiasen@xiaomi.com> | 2 个月前 | |
bmp/sched: add bmp support Signed-off-by: buxiasen <buxiasen@xiaomi.com> | 2 个月前 |