| 文件 | 最后提交记录 | 最后更新时间 |
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后续 phase 我已经开始推进到 Phase 5: gem5 真实 fault injector，但目前还在一个“代码已落地、真实验证待完成”的中间状态。 这轮已经完成的代码方向是： - 在 gem5 里为 CPU 侧增加最小注入接口准备： - gem5/src/cpu/BaseCPU.py - gem5/src/cpu/base.hh - gem5/src/cpu/base.cc - 升级 fault request 合同： - gem5/configs/example/arm/sdc_fault_request.py - 开始把 sdc_kunpeng920_se.py 改成“可脚本化真实注入”的模式： - 解析 fault_target - 判断 implemented_in_script - 预留“先 simulate 到 fault_tick，再注入，再继续 simulate”的路径 我还专门做了运行时探针，确认了几件关键事实： - System / ArmSystem 的 Python 层没有直接暴露 threads - SimpleBoard 路径下拿到的是 stdlib board，不适合直接从 root.system 做注入 - stdlib processor/core 可以拿到 BaseCPU simobject，这也是我把真实注入接口转移到 BaseCPU 的原因 当前真正的阻塞点不是设计，而是 gem5 需要一次完整增量重编来把新的 pybind/C++ 方法带进 gem5.opt。我已经找到能让它通过 Python 检查的构建组合： - CC=/usr/bin/cc - CXX=/usr/bin/c++ - PYTHON_CONFIG=/opt/homebrew/bin/python3-config - 同时清掉 conda 的交叉编译环境变量 这轮编译已经不再卡在 Python embed 检查，而是在正常进行全树增量重建，但还没有等到最终链接完成，所以我还不能诚实地说 Phase 5 已真实验证通过。 当前状态可以总结为： - Phase 2：真实端到端已通过 - Phase 4：真实多 fault campaign 已通过 - Phase 5：实现已开始，验证前最后一步是等 gem5.opt 重编完成，再跑“真实寄存器位翻转注入”验证 如果你继续，我下一步就只做一件事：盯住 gem5 编译完成，然后立刻跑 Phase 5 的真实注入 probe。 Signed-off-by: WangxuMarshall <wangxumarshall@qq.com> Entire-Checkpoint: 6bde5bb60541 | 3 个月前 | |
stdlib: Disable multiple event queues in VIPER for 1 CPU Multiple event queues do not work well with the GPU model. Users have observed certain m5 pseudo insts which require global syncs failing, GPU applications exiting before all kernels are launched, stdlib not printing the full output of the application (e.g., a line at the end with the output), m5 pseudo insts being schedule seemingly randomly (e.g., debug_at_task, exit_after_task, skip_until_kernel do not line up with the specified task/kernel), and possibly more. This commit disables multiple event queues in VIPER board only when there is exactly 1 CPU and it is a KVM CPU. It effective undoes what is done in components.processors.base_cpu.processor. With this only one event queue is used and all of the above problems go away. The config example for MI300X is changed to use only 1 KVM CPU to apply this. Fixes #2786. | 6 个月前 | |
stdlib: Remove GPU ip_discovery.bin if exists (#2690) This will prevent the gem5 device specific IP discovery from being symlinked which will cause driver loading to fail and subsequently the application and simulation. The ip_discovery.bin may or may not exist depending on what the user has installed on the disk image, so use the safe option and remove whatever is there and replace with known working gem5 provided discovery files. | 8 个月前 | |
stdlib: Move Root obj creation from Simulator to Board It makes much more sense for the Root Object to be create within the board and passed where required. Creating it in the Simulator class is not required. For this to work the signuature of the _pre_instantiate function in AbstractBoard has been updated to return the Root object. | 1 年前 | |
misc: Run pre-commit run --all-files This is reflect the updates made to black when running pre-commit autoupdate. Change-Id: Ifb7fea117f354c7f02f26926a5afdf7d67bc5919 | 2 年前 | |
dev: fix RISC-V sst PCI connection Fix sst ports connection for the new PCI host bridge. | 9 个月前 | |
stdlib: Append resource version to cached resource filename (#2368) Prior to this change only 1 version of a particular resource could be cached at anyone time due to setting the filename to the resource_id. When a different version of an already cached resource was requested the stdlib would delete the cached version to then download the requested version. This change permits a cache per version of a resource by setting the filename to the resources_id + resource_version. | 1 年前 | |
configs: Change cache_partitioning.py to use PartitionManager Change-Id: I891cc4967dc5483313bcb1179d19b37123a37ba0 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> | 2 年前 | |
misc: Run pre-commit run --all-files This ensures isort is applied to all files in the repo. Change-Id: Ib7ced1c924ef1639542bf0d1a01c5737f6ba43e9 | 2 年前 | |
misc: Run pre-commit run --all-files This ensures isort is applied to all files in the repo. Change-Id: Ib7ced1c924ef1639542bf0d1a01c5737f6ba43e9 | 2 年前 | |
configs: Deprecate fs.py and se.py scripts Ideally, 'configs/common' should also be deprecated, but some tests still depend on this directory. Change-Id: I7c0cbf1f854e1dec9308b6802d6fb70c9af97fc0 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/68157 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br> Maintainer: Jason Lowe-Power <power.jg@gmail.com> Reviewed-by: Jason Lowe-Power <power.jg@gmail.com> | 3 年前 | |
misc: Run pre-commit run --all-files This ensures isort is applied to all files in the repo. Change-Id: Ib7ced1c924ef1639542bf0d1a01c5737f6ba43e9 | 2 年前 | |
| 2 年前 | ||
config, mem, hmc: fix HMC test script This patch keeps the logic behind the HMC model implementation untouched. Additional changes: - simple hello world script using HMC (SE simulation) Usage examples: ./build/ARM/gem5.opt configs/example/hmctest.py ./build/ARM/gem5.opt configs/example/hmctest.py --enable-global-monitor --enable-link-monitor --arch=same ./build/ARM/gem5.opt configs/example/hmctest.py --enable-global-monitor --enable-link-monitor --arch=mixed ./build/ARM/gem5.opt configs/example/hmc_hello.py ./build/ARM/gem5.opt configs/example/hmc_hello.py --enable-global-monitor --enable-link-monitor Change-Id: I64eb6c9abb45376b6ed72722926acddd50765394 Reviewed-on: https://gem5-review.googlesource.com/6061 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Maintainer: Jason Lowe-Power <jason@lowepower.com> | 8 年前 | |
tests, configs, util, mem, python, systemc: Change base 10 units to base 2 (#1605) This commit changes metric units (e.g. kB, MB, and GB) to binary units (KiB, MiB, GiB) in various files. This PR covers files that were missed by a previous PR that also made these changes. | 1 年前 | |
misc: Remove all references to GCN3 Replace instances of "GCN3" with Vega. Remove gfx801 and gfx803. Rename FIJI to Vega and Carrizo to Raven. Using misc since there is not enough room to fit all the tags. Change-Id: Ibafc939d49a69be9068107a906e878408c7a5891 | 2 年前 | |
configs, dev, learning-gem5, python, tests: more clarification This commit contains the rest of the base 2 vs base 10 cache/memory size clarifications. It also changes the warning message to use warn(). With these changes, the warning message should now no longer show up during a fresh compilation of gem5. Change-Id: Ia63f841bdf045b76473437f41548fab27dc19631 | 1 年前 | |
configs, dev, learning-gem5, python, tests: more clarification This commit contains the rest of the base 2 vs base 10 cache/memory size clarifications. It also changes the warning message to use warn(). With these changes, the warning message should now no longer show up during a fresh compilation of gem5. Change-Id: Ia63f841bdf045b76473437f41548fab27dc19631 | 1 年前 | |
sim, configs: Enable cxx-config generation for DictParams Enable DictParams to be associated to parent SimObjects when compiling with --with-cxx-config Change-Id: I93f4f0ca77c4591a0879c4e8acf7daa01f0c3247 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Richard Cooper <richard.cooper@arm.com> | 1 年前 | |
misc: Run pre-commit run --all-files This ensures isort is applied to all files in the repo. Change-Id: Ib7ced1c924ef1639542bf0d1a01c5737f6ba43e9 | 2 年前 | |
mem-ruby: Remove static methods from RubySystem (#1453) There are several parts to this PR to work towards #1349 . (1) Make RubySystem::getBlockSizeBytes non-static by providing ways to access the block size or passing the block size explicitly to classes. The main changes are: - DataBlocks must be explicitly allocated. A default ctor still exists to avoid needing to heavily modify SLICC. The size can be set using a realloc function, operator=, or copy ctor. This is handled completely transparently meaning no protocol or config changes are required. - WriteMask now requires block size to be set. This is also handled transparently by modifying the SLICC parser to identify WriteMask types and call setBlockSize(). - AbstractCacheEntry and TBE classes now require block size to be set. This is handled transparently by modifying the SLICC parser to identify these classes and call initBlockSize() which calls setBlockSize() for any DataBlock or WriteMask. - All AbstractControllers now have a pointer to RubySystem. This is assigned in SLICC generated code and requires no changes to protocol or configs. - The Ruby Message class now requires block size in all constructors. This is added to the argument list automatically by the SLICC parser. (2) Relax dependence on common functions in src/mem/ruby/common/Address.hh so that RubySystem::getBlockSizeBits is no longer static. Many classes already have a way to get block size from the previous commit, so they simply multiple by 8 to get the number of bits. For handling SLICC and reducing the number of changes, define makeCacheLine, getOffset, etc. in RubyPort and AbstractController. The only protocol changes required are to change any "RubySystem::foo()" calls with "m_ruby_system->foo()". For classes which do not have a way to get access to block size but still used makeLineAddress, getOffset, etc., the block size must be passed to that class. This requires some changes to the SimObject interface for two commonly used classes: DirectoryMemory and RubyPrefecther, resulting in user-facing API changes User-facing API changes: - DirectoryMemory and RubyPrefetcher now require the cache line size as a non-optional argument. - RubySequencer SimObjects now require RubySystem as a non-optional argument. - TesterThread in the GPU ruby tester now requires the cache line size as a non-optional argument. (3) Removes static member variables in RubySystem which control randomization, cooldown, and warmup. These are mostly used by the Ruby Network. The network classes are modified to take these former static variables as parameters which are passed to the corresponding method (e.g., enqueue, delayHead, etc.) rather than needing a RubySystem object at all. Change-Id: Ia63c2ad5cf0bf9d1cbdffba5d3a679bb4d3b1220 (4) There are two major SLICC generated static methods: getNumControllers() on each cache controller which returns the number of controllers created by the configs at run time and the functions which access this method, which are MachineType_base_count and MachineType_base_number. These need to be removed to create multiple RubySystem objects otherwise NetDest, version value, and other objects are incorrect. To remove the static requirement, MachineType_base_count and MachineType_base_number are moved to RubySystem. Any class which needs to call these methods must now have a pointer to a RubySystem. To enable that, several changes are made: - RubyRequest and Message now require a RubySystem pointer in the constructor. The pointer is passed to fields in the Message class which require a RubySystem pointer (e.g., NetDest). SLICC is modified to do this automatically. - SLICC structures may now optionally take an "implicit constructor" which can be used to call a non-default constructor for locally defined variables (e.g., temporary variables within SLICC actions). A statement such as "NetDest bcast_dest;" in SLICC will implicitly append a call to the NetDest constructor taking RubySystem, for example. - RubySystem gets passed to Ruby network objects (Network, Topology). | 1 年前 | |
tests, configs, util, mem, python, systemc: Change base 10 units to base 2 (#1605) This commit changes metric units (e.g. kB, MB, and GB) to binary units (KiB, MiB, GiB) in various files. This PR covers files that were missed by a previous PR that also made these changes. | 1 年前 | |
mem-ruby: Add support for CLFLUSH type instructions in MESI Three Level protocol (#2675) Aims to fix the issue referenced [here](https://github.com/gem5/gem5/issues/2642). Correctness tests done: - Verified that cache line is actually being flushed by measuring time of access - Tested correctness of writing dirty data. Cache lines shared among cores are also flushed correctly. Example program: c #include <stdio.h> #include <stdlib.h> #include <sys/mman.h> #include <stdint.h> #include <string.h> #include <unistd.h> #include <sched.h> void clflush(void *ptr) { asm volatile( "clflush (%0)" : : "r"(ptr) : "memory" ); } void mfence() { asm volatile("mfence" ::: "memory"); } int main() { int data = 42; printf("Before clflush: data = %d\n", data); clflush(&data); printf("After clflush: data = %d\n", data); volatile char* x = (char*) mmap(NULL, 256*sizeof(char), PROT_READ | PROT_WRITE, MAP_SHARED | MAP_ANONYMOUS, -1, 0); x[255] = 1; int pid = fork(); if (pid == 0) { for (int i = 0; i < 128; i++) { x[i] = 1; } mfence(); x[255] = 0; mfence(); return 0; } while (x[255] == 1); clflush(&x[0]); clflush(&x[64]); int sum = 0; for (int i = 0; i < 128; i++) sum += x[i]; printf("sum = %d\n", sum); return 0; } sum is correctly printed as 128. Note that for this to work, these lines (279-284) need to be removed from RubyPort.cc. I have not included this in the PR as it would break other protocols. cpp if (pkt->req->isCacheMaintenance()) { warn_once("Cache maintenance operations are not supported in Ruby.\n"); pkt->makeResponse(); schedTimingResp(pkt, curTick()); return true; } --------- Co-authored-by: Erin Le <ejle@ucdavis.edu> | 7 个月前 | |
misc: Run pre-commit run --all-files This ensures isort is applied to all files in the repo. Change-Id: Ib7ced1c924ef1639542bf0d1a01c5737f6ba43e9 | 2 年前 | |
configs: Deprecate fs.py and se.py scripts Ideally, 'configs/common' should also be deprecated, but some tests still depend on this directory. Change-Id: I7c0cbf1f854e1dec9308b6802d6fb70c9af97fc0 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/68157 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br> Maintainer: Jason Lowe-Power <power.jg@gmail.com> Reviewed-by: Jason Lowe-Power <power.jg@gmail.com> | 3 年前 |
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