Ascend 950PR/Ascend 950DT New Feature Navigation
This document indexes the new hardware features of Ascend 950PR/Ascend 950DT (NPU architecture version 3510) compared with the previous generation (2201), and provides links to the corresponding programming models, APIs, and operator practice materials for each feature.
Applicable chips: Ascend 950PR, Ascend 950DT (
__NPU_ARCH__= 3510)
For details about the architecture changes, see 2201-to-3510 Architecture Changes.
New Feature Overview
| No. | New Feature | Corresponding Programming Model and Feature | Corresponding API | Corresponding Operator Practice Material |
|---|---|---|---|---|
| 1 | RegBase architecture: The AIV core Vector computation switches from MemBase to RegBase. Data is moved from UB to the register for computation, and intermediate results are operated directly in the register without writing back to UB. | Reg Vector Computation Programming | Reg Vector Computation API List | VF Fusion Optimization, VF Loop Optimization |
| 2 | SIMT programming model: A new SIMT hardware unit (DCache, Warp Scheduler, 128 KB Register File) is added to support thread-level parallel programming. | AI Core SIMT Programming | SIMT API List | SIMT Operator Implementation, SIMT Operator Performance Optimization |
| 3 | SIMD and SIMT hybrid programming: SIMD and SIMT code work together in the same kernel. | SIMD and SIMT Hybrid Programming | Hybrid Programming API List, Built-in Variables | Hybrid Programming Operator Implementation, Hybrid Programming Performance Optimization |
| 4 | HiF8 (hifloat8_t) data type: The Cube computation unit supports matrix multiplication with the HiF8 data type. | Data types supported by Cube in 3510 Architecture Specifications | Built-in Data Type Description, Cast Type Conversion, asc_float2hif8 (deprecated) | Under development |
| 5 | UB-to-L1 Buffer path: Data can be moved directly from UB to L1 Buffer without going through GM. | 3510 Architecture Changes - Move Unit | Newly supported UB-to-L1 Buffer Data Move | Under development |
| 6 | L0C-to-UB path: Data can be moved directly from L0C Buffer to UB without going through GM. | 3510 Architecture Changes - Move Unit | asc_copy_l0c2ub | Matrix Multiplication Result Accumulation |
| 7 | ND-DMA move instruction: Extends the DataCopy capability to freely configure the dimension information and stride of the data to be moved in. | 3510 Architecture Changes - Move Unit | Multi-dimensional Data Move ISASI, asc_ndim_copy_gm2ub | Reducing Move Count in Non-contiguous Move Scenarios |
| 8 | SSBuffer inter-core storage: A new intra-core storage unit that supports access by AIC cores and AIV cores through Scalar. | Under development | Not applicable | Under development |
| 9 | Mutex synchronization: Synchronization between intra-core asynchronous pipeline instructions, similar to the lock mechanism in CPUs. | Under development | Mutex ISASI, asc_lock | Under development |
| 10 | CrossCore inter-core synchronization: AIV0 and AIV1 can independently trigger AIC waiting. | Under development | CrossCoreSetFlag, CrossCoreWaitFlag | CV Fusion Operator Implementation |
| 11 | MX (MicroScaling) data type: Supports FP8_E4M3/MXFP4/8 low-bit matrix operations, halving memory usage and doubling compute throughput. | LoadData extension in 3510 Architecture Changes - Move Unit | asc_mmad_mx, asc_copy_l12l0a_mx, asc_copy_l12l0b_mx | Matmul Feature Introduction, MxMatmul Scenario, Matrix Multiplication Quantization/Dequantization |
| 12 | Fixpipe enhancement: Adds NZ2DN in-flight conversion, enabling Fixpipe to convert NZ-format data to DN format in flight. | 3510 Architecture Changes - Move Unit | Fixpipe API, asc_copy_l0c2gm, asc_copy_l0c2l1 | Matrix Multiplication Result Accumulation |
| 13 | UB interconnect/bank structure change: In the 3510 architecture, the UB changes from 16 bank groups (each with three 4 KB banks) to 8 bank groups (each with two 16 KB banks). | 3510 Architecture Specifications - Storage Unit | Not applicable | Avoiding UB Bank Conflicts Overview, 2201 Bank Conflict, 3510 Bank Conflict, SIMT Avoiding Bank Conflicts |
Material Status Description
| Status Label | Description |
|---|---|
| (With link) | The material for this feature already exists in the docs directory. |
| Under development | No dedicated material is available for this feature yet. It will be added later. |
| Not applicable | This feature does not involve related material, and no material is planned. |