| [CI][1/N] Add hardware-awared test gating and CI routing (#8557)
## What this PR do?
This PR introduces an npu_test decorator for hardware-based test gating
and CI routing, alongside new unit tests for NPUModelRunner. Feedback
highlights the need for more robust torch_npu mocking to prevent
errors in non-NPU environments and suggests that the @npu_test
decorator should verify the specific NPU chip type at runtime.
We've long been plagued by excessively long end-to-end testing
durations, which is extremely detrimental to community health and
developer well-being. We aim to implement selective testing based on
developer pull requests (PRs):
This will be addressed from two main perspectives:
1. Intelligently selecting test cases to trigger based on developer
modifications. This is easily achievable; we simply need to ensure a
one-to-one correspondence between the test directory (tests/ut) and the
modules in the src directory. Furthermore, for some common, fundamental
modules, we will allow them to be unconditionally tested in every PR
(this is meaningful because certain modules...).
2. Stateful test cases that developers are aware of. Developers only
need to add a @npu_test decorator to specify the required NPU device
type and number of chips. The system will automatically route this test
case to an appropriate node for testing.
## What's next?
1. Fill in more non-e2e cases that can run on the NPU to have some real
verification.
2. Once the cases above are complete enough, we try to reduce the
existing e2e cases until they can reach a healthy duration.
**This is a massive undertaking, and anyone who is interested can get
involved.**
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Signed-off-by: wangli <wangli858794774@gmail.com> | 1 个月前 |