AscendNPU-IR:基于MLIR的昇腾亲和算子编译中间表示项目

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AscendNPU-IR是基于MLIR（Multi-Level Intermediate Representation）构建的，面向昇腾亲和算子编译时使用的中间表示，提供昇腾完备表达能力，通过编译优化提升昇腾AI处理器计算效率，支持通过生态框架使能昇腾AI处理器与深度调优

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bishengir
!2035 merge feat/mixcv-vector-multibuffer-default into dev/regbase [AscendNPU IR][CV][MultiBuffer] feat: default-enable MixCV vector multi-buffer Created-by: huangyujun123 Commit-by: huangyujun123 Merged-by: ascend-robot Description: [AscendNPU IR][CV][MultiBuffer] feat: default-enable MixCV vector multi-buffer Motivation: MixCV kernels previously defaulted limit-mix-auto-multi-buffer-buffer to only-cube, so vector-side UB load/store candidates were left single-buffered unless users explicitly passed no-limit. Enabling vector multi-buffer by default unlocks the intended MixCV latency-hiding path and matches the A5 precision issues that only appear when vector multi-buffer is engaged. Design: Change the compile option / pass / AVE pipeline default from ONLY_CUBE to NO_LIMIT. Keep only-cube available as an explicit opt-in for cube-only MixCV multi-buffer. Extend mark-multi-buffer.mlir with an Ascend950 AIV+part_of_mix case that checks default marking versus only-cube, and extend multi-buffer-while-pipeline.mlir with an Ascend950 Mark→PlanMemory→GSS→Enable pipeline that covers vector multi-buffer slot selection plus PlanMemory address reuse across two non-overlapping phases. Risks: More MixCV kernels will allocate N× UB for vector buffers, increasing PlanMemory pressure and exposing cross-core sync/reuse edge cases that were previously hidden behind cube-only multi-buffer. Users can revert with --limit-mix-auto-multi-buffer-buffer=only-cube or --disable-multi-buffer-on-ub=true. Assisted-by: Cursor Grok 4.5 See merge request: Ascend/AscendNPU-IR!2035
3 天前
build-tools
fix: remove unhandled --build-bishengir-template option Remove unused and redundant option --build-bishengir-template. Also, getopt rejects unknown options before the loop runs, so the only way to reach *) is an option declared in LONG_OPTS with no case arm, which is a bug in this script. We produce an fatal message in this case. Signed-off-by: Hu Xiaowen <hu.xiaowen@huawei.com>
18 天前
third-party
chore: bump llvm-project submodule to 2f203398 Update third-party/llvm-project to 2f203398 on Ascend/AscendNPU-IR/llvmorg-19.1.7 (latest tip: PDLL lit skip and post-!22 TableGen BSPUB fixes). Co-authored-by: Cursor <cursoragent@cursor.com>
24 天前
.clang-format
Initialize A5 AscendNPUIR
5 个月前
.gitignore
[Huawei][AscendNPU IR] feat: Support ssbuf address space and related operations for Triton-level integration ## 1. Overview / 概述 ### English This PR integrates the ssbuf address space (ID 11) into the A5 compilation flow of the HIVM dialect. It enables manual memory mapping and address management via hivm.hir.pointer_cast and standard memref.load/memref.store operations. This implementation bypasses standard MLIR memory allocation (memref.alloc) to satisfy the custom scalar-to-vector interaction pipeline required by Triton-Ascend. ### 中文 本 PR 在 HIVM 方言的 A5 编译流程中集成了对 ssbuf 地址空间（ID 11）的支持。它通过 hivm.hir.pointer_cast 以及标准的 memref.load/memref.store 操作实现了手动的内存映射与地址管理。该实现绕过了标准的 MLIR 内存分配（memref.alloc），以满足 Triton-Ascend 所需的自定义标量与向量交互流水线。 ## 2. Key Changes / 关键变更 ### English - **bishengir/include/bishengir/Dialect/HIVM/IR/HIVMAttrs.td**: - Registered HIVM_AddressSpace_SSBUF mapping to address space ID 11. - Updated the description of HIVM_AddressSpaceAttr to officially cover SSBUF. - **bishengir/lib/Dialect/Analysis/Initializer.cpp**: - Added hivm::PointerCastOp to the list of recognized head operations in DimensionAnalyzerBase::isHeadOperation. - **bishengir/lib/Dialect/HIVM/Utils/Utils.cpp & PlanMemory.cpp**: - Added the isSsbuffer helper function to verify if an address space corresponds to SSBUF. - Modified isLocalBuffer to classify SSBUF as non-local, ensuring its behavior aligns with global memory (GM). - Added an explicit compile-time safety assertion in PlanMemory (GenerateBufferInfo) to throw a compile error (llvm_unreachable) if any allocation-like operation (such as alloc) is attempted on SSBUF. ### 中文 - **bishengir/include/bishengir/Dialect/HIVM/IR/HIVMAttrs.td**: - 注册了映射至地址空间 ID 11 的 HIVM_AddressSpace_SSBUF。 - 更新了 HIVM_AddressSpaceAttr 的描述，使其正式涵盖 SSBUF。 - **bishengir/lib/Dialect/Analysis/Initializer.cpp**: - 在 DimensionAnalyzerBase::isHeadOperation 中将 hivm::PointerCastOp 添加到已识别的 Head 操作列表中。 - **bishengir/lib/Dialect/HIVM/Utils/Utils.cpp & PlanMemory.cpp**: - 增加了 isSsbuffer 辅助函数以验证地址空间是否对应 SSBUF。 - 修改了 isLocalBuffer 逻辑，将 SSBUF 判定为非 Local 空间（行为与 GM 保持一致）。 - 在 PlanMemory 阶段（GenerateBufferInfo）中增加了显式的编译期安全断言：若在 SSBUF 上尝试进行类似分配的操作（如 alloc），将触发编译报错（llvm_unreachable）。 ## 3. Technical Deep-Dive / 技术细节剖析 ### English 1. **Dimension Analysis Integration**: Registering hivm::PointerCastOp as a head operation in DimensionAnalyzerBase is critical for correct dimension flattening. When FlattenOp evaluates load/store operations on manually casted pointers, it can now properly track and identify collapse groups instead of failing on assertions. 2. **Allocation Restriction**: Since ssbuf addresses are explicitly mapped using pointer_cast before the memory planning phase, no memory allocator is expected to provision memory for it. The check inside PlanMemory.cpp enforces this model by preventing any standard MLIR alloc-like semantics on the SSBUF address space. ### 中文 1. **维度分析集成**：在 DimensionAnalyzerBase 中将 hivm::PointerCastOp 注册为 Head 操作，对于保证维度平坦化（Flattening）的正确性至关重要。当 FlattenOp 处理作用在手动转换指针之上的 load/store 时，它现在可以正常跟踪并识别折叠组（Collapse Groups），而不会因找不到折叠组而触发断言失败。 2. **分配限制**：由于 ssbuf 的地址在内存规划阶段前已被用户通过 pointer_cast 明确手动映射，因此无需内存分配器为其分配空间。PlanMemory.cpp 内部的校验强制执行了该模型，阻止在 SSBUF 地址空间上进行任何标准的 MLIR alloc 语义分配。 ## 4. Impact & Risk Assessment / 影响与风险评估 ### English - **Breaking Changes**: No. - **Performance Impact**: Positive. Bypassing manual synchronization on the hardware-synchronized scalar pipe prevents redundant performance overhead. - **Backward Compatibility**: Fully backward compatible; existing GM and local buffer allocation policies remain unchanged. ### 中文 - **破坏性变更**: 否。 - **性能影响**: 积极。绕过硬件已同步的标量流水线上的手动同步，避免了额外的性能开销。 - **向后兼容性**: 完全向后兼容；现有的 GM 和 Local 缓存分配策略保持不变。 ## 5. Verification & Testing / 测试与验证方法 ### English - **Unit Tests Added/Modified**: - Added mark-stride-align-ssbuf.mlir to verify that SSBUF memory operations are correctly marked and bypassed. - Added verification test cases to plan-memory.mlir, inject-sync.mlir, hivm-insert-cv-tight-coupled-buffer.mlir, hivm-mark-disable-load.mlir, and hivm-flatten-ops.mlir to assert that ssbuf operations are processed properly without undergoing local buffer transformations. ### 中文 - **单元测试新增/修改**： - 新增了 mark-stride-align-ssbuf.mlir 测试，以验证 SSBUF 内存操作被正确识别并被相关 Pass 安全绕过。 - 在 plan-memory.mlir、inject-sync.mlir、hivm-insert-cv-tight-coupled-buffer.mlir、hivm-mark-disable-load.mlir 和 hivm-flatten-ops.mlir 中添加了验证性测试用例，断言 ssbuf 操作能够被正常解析，且不参与任何 Local 空间的优化转换。
16 天前
.gitmessage
[Huawei][AscendNPU IR] update commit message Co-authored-by: gguo<ge.guo@huawei.com> # message auto-generated for no-merge-commit merge: !1352 merge gguo/new_commit_message into A5/dev [Huawei][AscendNPU IR] update commit message Created-by: gitbaiyu Commit-by: gguo Merged-by: ascend-robot Description: [Huawei][AscendNPU IR] update commit message See merge request: Ascend/AscendNPU-IR-Dev!1352
2 个月前
.gitmodules
chore: point llvm-project submodule branch to llvmorg-19.1.7 Update .gitmodules branch from Ascend/AscendNPU-IR-Dev/llvmorg-19.1.7 to Ascend/AscendNPU-IR/llvmorg-19.1.7 for dev/regbase. Co-authored-by: Cursor <cursoragent@cursor.com>
25 天前
.pre-commit-config.yaml
Initialize A5 AscendNPUIR
5 个月前
CODE_OF_CONDUCT.md
Initialize A5 AscendNPUIR
5 个月前
CONTRIBUTING.md
Initialize A5 AscendNPUIR
5 个月前
LICENSE.TXT
Initialize A5 AscendNPUIR
5 个月前
README.md
Initialize A5 AscendNPUIR
5 个月前
SECURITY.md
Initialize A5 AscendNPUIR
5 个月前
Third_Party_Open_Source_Software_Notice
[Huawei][AscendNPU IR] add notice for open source software
3 个月前
pyproject.toml
Initialize A5 AscendNPUIR
5 个月前

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项目介绍

AscendNPU-IR是基于MLIR（Multi-Level Intermediate Representation）构建的，面向昇腾亲和算子编译时使用的中间表示，提供昇腾完备表达能力，通过编译优化提升昇腾AI处理器计算效率，支持通过生态框架使能昇腾AI处理器与深度调优

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