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[Huawei][AscendNPU-IR] Merge A5 options into shared Options.td with generator refactor Annotate each option with optionScope (A3_ONLY / A5_ONLY / SHARED) and refactor the tablegen backend to emit scope-aware code. A5 options are now managed in the same Options.td as A3 ones instead of a separate file. Key changes: - Options.h/cpp: add scope helpers (isA3OnlyOption, isA5OnlyOption, etc.) and new option classes (ExternalStateOption, InternalStateOption). - Options.td: add optionScope, externalStateObject/Field fields. - bishengir-compile/Options.td: merge all A5 options with scope annotations; unported A5 types are recorded as A5UnmigratedOptionStub. - CompileOptionsGen.cpp / CompileConfigGen.cpp: update to new accessor API. - BiShengIRCompileConfig.cpp: set scope flags in collectHIVMCArgs(); add TargetDevice handler. - PassPipeline.cpp: replace manual setter chain with generated mappings; | 1 个月前 | |
!1470 merge dev/timing-a3 into master [Huawei][AscendNPU IR] Add compile timing scopes Created-by: shijingchang Commit-by: s00653124 Merged-by: ascend-robot Description: ## Summary - Add compile-level MLIR timing context for bishengir-compile. - Enable nested timing scopes around retriable BiShengHIR pipeline execution. - Profile external tool execution through the same timing context. - Register MLIR default timing manager CLI options in bishengir-compile. - Add LLVM patch to support --mlir-timing-display=sort, sorted by self time with timer paths. ## Motivation This change makes bishengir-compile timing output more useful for locating compile-time bottlenecks across internal pipelines and external compiler invocations. The new timing context allows individual pipeline runs and external tools to appear under one compile timing tree, while the added sort display mode helps identify high self-time regions without losing nesting context. See merge request: Ascend/AscendNPU-IR!1470 | 11 天前 | |
[Huawei][AscendNPU IR][Timing] add mlir-timing support | 12 天前 | |
[AscendNPU IR]: refactor version control | 6 个月前 | |
!2583 merge flatten-perf into master [AscendNPU-IR] Reapply "enable flatten by default" (!2326) & fix performance degradation caused by this patch Created-by: kiansitov Commit-by: kiansitov;Roman Rusyaev Merged-by: ascend-robot Description: --- title: "[AscendNPU IR]: Reapply "enable flatten by default" (!2326) and fix performance degradation caused this patch" --- ## 描述 Description 1. Revert "Revert "!2326 merge migration into master"". Reapply previously reverted commit "[AscendNPU-IR] enable flatten by default" (af7a256c8d3e7e3cdbe4153b18a9fc747a07b2a8) 2. Fix performance degradation. hfusion\FlattenOp pass is applied only to MIX kernels, while the pre-flattening PropagateReshape pass is also applied to AIV kernels. PropagateReshape and hfusion\FlattenOp should be applied consistently: PropagateReshape should be applied only when hfusion\FlattenOp is also applicable. Applying PropagateReshape without hfusion\FlattenOp leads to performance degradation because PropagateReshape pass can affect operation fusion. Skip PropagateReshape pass for AIV kernels (when flattening is not applicable) ## 类型 Category - [ ] Bug修复 Bugfix - [ ] 新功能 New feature - [ ] 代码风格更新（格式化，局部变量）Style changes - [ ] 重构（即不是新增功能，也不是修改bug的代码变动）Refactor - [ ] 构建过程或辅助工具的变动 Build-related - [ ] 文档内容更新 Docs ## Checklist - [ ] 我的代码遵循这个项目的代码风格 My code follows the project's code style - [ ] 我已经自己测试过我的代码 I have self-tested my code - [ ] 我已经更新了相应的文档 I have updated the relevant documentation - [ ] 我已经根据需要更新了对应的变更日志 I have updated the changelog as needed - [ ] 我已经在标题中正确使用了类型标签（例如：feat:, fix:）I have correctly used type labels in the title (e.g., feat:, fix:) See merge request: Ascend/AscendNPU-IR!2583 | 5 小时前 | |
[Huawei][AscendNPU IR][build] fix proton build | 9 天前 | |
[SIMT] Fix compilation problems | 24 天前 |
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