[Huawei][AscendNPU IR] fix PDLL regbase lit gating for A3/A5 builds-llvm-project-AtomGit

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[Huawei][AscendNPU IR] fix PDLL regbase lit gating for A3/A5 builds #27

[Huawei][AscendNPU IR] fix PDLL regbase lit gating for A3/A5 builds #27

已开启

gguo创建于 7月15日

共 8 个文件变更+37-22

Mllvm/include/llvm/TableGen/Parser.h+4-1

	@@ -13,6 +13,8 @@
13	#ifndef LLVM_TABLEGEN_PARSER_H	13	#ifndef LLVM_TABLEGEN_PARSER_H
14	#define LLVM_TABLEGEN_PARSER_H	14	#define LLVM_TABLEGEN_PARSER_H
15		15
		16	+#include "llvm/ADT/ArrayRef.h"
		17	+
16	namespace llvm {	18	namespace llvm {
17	class RecordKeeper;	19	class RecordKeeper;
18	class SourceMgr;	20	class SourceMgr;
	@@ -23,7 +25,8 @@ class SourceMgr;
23	///	25	///
24	/// NOTE: TableGen currently relies on global state within a given parser	26	/// NOTE: TableGen currently relies on global state within a given parser
25	/// invocation, so this function is not thread-safe.	27	/// invocation, so this function is not thread-safe.
26	-bool TableGenParseFile(SourceMgr &InputSrcMgr, RecordKeeper &Records);	28	+bool TableGenParseFile(SourceMgr &InputSrcMgr, RecordKeeper &Records,
		29	+ ArrayRef<std::string> Macros = {});
27		30
28	} // end namespace llvm	31	} // end namespace llvm
29		32

Mllvm/lib/TableGen/Parser.cpp+3-2

	@@ -13,7 +13,8 @@
13		13
14	using namespace llvm;	14	using namespace llvm;
15		15
16	-bool llvm::TableGenParseFile(SourceMgr &InputSrcMgr, RecordKeeper &Records) {	16	+bool llvm::TableGenParseFile(SourceMgr &InputSrcMgr, RecordKeeper &Records,
		17	+ ArrayRef<std::string> Macros) {
17	// Initialize the global TableGen source manager by temporarily taking control	18	// Initialize the global TableGen source manager by temporarily taking control
18	// of the input buffer in `SrcMgr`. This is kind of a hack, but allows for	19	// of the input buffer in `SrcMgr`. This is kind of a hack, but allows for
19	// preserving TableGen's current awkward diagnostic behavior. If we can remove	20	// preserving TableGen's current awkward diagnostic behavior. If we can remove
	@@ -28,7 +29,7 @@ bool llvm::TableGenParseFile(SourceMgr &InputSrcMgr, RecordKeeper &Records) {
28	auto *MainFileBuffer = SrcMgr.getMemoryBuffer(SrcMgr.getMainFileID());	29	auto *MainFileBuffer = SrcMgr.getMemoryBuffer(SrcMgr.getMainFileID());
29	Records.saveInputFilename(MainFileBuffer->getBufferIdentifier().str());	30	Records.saveInputFilename(MainFileBuffer->getBufferIdentifier().str());
30		31
31	- TGParser Parser(SrcMgr, /Macros=/std::nullopt, Records,	32	+ TGParser Parser(SrcMgr, Macros, Records,
32	/NoWarnOnUnusedTemplateArgs=/false,	33	/NoWarnOnUnusedTemplateArgs=/false,
33	/TrackReferenceLocs=/true);	34	/TrackReferenceLocs=/true);
34	bool ParseResult = Parser.ParseFile();	35	bool ParseResult = Parser.ParseFile();

Mmlir/lib/Tools/PDLL/Parser/Parser.cpp+7-1

	@@ -850,7 +850,13 @@ LogicalResult Parser::parseTdInclude(StringRef filename, llvm::SMRange fileLoc,
850		850
851	// Parse the tablegen file.	851	// Parse the tablegen file.
852	llvm::RecordKeeper tdRecords;	852	llvm::RecordKeeper tdRecords;
853	- if (llvm::TableGenParseFile(tdSrcMgr, tdRecords))	853	+#ifdef BSPUB_DAVINCI_BISHENGIR_A5
		854	+ static const std::string tdMacro = "BSPUB_DAVINCI_BISHENGIR_A5";
		855	+ llvm::ArrayRef<std::string> tdMacros(&tdMacro, 1);
		856	+#else
		857	+ llvm::ArrayRef<std::string> tdMacros;
		858	+#endif
		859	+ if (llvm::TableGenParseFile(tdSrcMgr, tdRecords, tdMacros))
854	return failure();	860	return failure();
855		861
856	// Process the parsed records.	862	// Process the parsed records.

Mmlir/test/CMakeLists.txt+1-0

	@@ -83,6 +83,7 @@ llvm_canonicalize_cmake_booleans(
83	MLIR_RUN_CUDA_SM80_TESTS	83	MLIR_RUN_CUDA_SM80_TESTS
84	MLIR_RUN_CUDA_SM80_LT_TESTS	84	MLIR_RUN_CUDA_SM80_LT_TESTS
85	MLIR_RUN_CUDA_SM90_TESTS	85	MLIR_RUN_CUDA_SM90_TESTS
		86	+ LLVM_BSPUB_DAVINCI_BISHENGIR_A5
86	)	87	)
87		88
88	configure_lit_site_cfg(	89	configure_lit_site_cfg(

Mmlir/test/lib/Tools/PDLL/TestPDLL.pdll+8-8

	@@ -6,11 +6,11 @@
6	//	6	//
7	//===----------------------------------------------------------------------===//	7	//===----------------------------------------------------------------------===//
8		8
9	-// #include "TestOps.td"	9	+#include "TestOps.td"
10	-// #include "mlir/Interfaces/CastInterfaces.td"	10	+#include "mlir/Interfaces/CastInterfaces.td"
11	-//	11	+
12	-// /// A simple pattern that matches and replaces an operation.	12	+/// A simple pattern that matches and replaces an operation.
13	-// Pattern TestSimplePattern => replace op<test.simple> with op<test.success>;	13	+Pattern TestSimplePattern => replace op<test.simple> with op<test.success>;
14	-//	14	+
15	-// // Test the import of interfaces.	15	+// Test the import of interfaces.
16	-// Pattern TestInterface => replace _: CastOpInterface with op<test.success>;	16	+Pattern TestInterface => replace _: CastOpInterface with op<test.success>;

Mmlir/test/lib/Transforms/TestDialectConversion.pdll+10-10

	@@ -6,13 +6,13 @@
6	//	6	//
7	//===----------------------------------------------------------------------===//	7	//===----------------------------------------------------------------------===//
8		8
9	-// #include "TestOps.td"	9	+#include "TestOps.td"
10	-// #include "mlir/Transforms/DialectConversion.pdll"	10	+#include "mlir/Transforms/DialectConversion.pdll"
11	-//	11	+
12	-// /// Change the result type of a producer.	12	+/// Change the result type of a producer.
13	-// Pattern => replace op<test.cast> -> (results: TypeRange)	13	+Pattern => replace op<test.cast> -> (results: TypeRange)
14	-// with op<test.cast> -> (convertTypes(results));	14	+ with op<test.cast> -> (convertTypes(results));
15	-//	15	+
16	-// /// Pass through test.return conversion.	16	+/// Pass through test.return conversion.
17	-// Pattern => replace op<test.return>(args: ValueRange)	17	+Pattern => replace op<test.return>(args: ValueRange)
18	-// with op<test.return>(convertValues(args));	18	+ with op<test.return>(convertValues(args));

Mmlir/test/lit.cfg.py+3-0

	@@ -258,3 +258,6 @@ if config.arm_emulator_executable:
258		258
259	if config.bspub_davinci_bishengir:	259	if config.bspub_davinci_bishengir:
260	config.available_features.add("bspub_davinci_bishengir")	260	config.available_features.add("bspub_davinci_bishengir")
		261	+
		262	+if config.bspub_davinci_bishengir_a5:
		263	+ config.available_features.add("regbase")

Mmlir/test/lit.site.cfg.py.in+1-0

	@@ -67,6 +67,7 @@ config.riscv_vector_emulator_options = "@RISCV_VECTOR_EMULATOR_OPTIONS@"
67	config.riscv_emulator_lli_executable = "@RISCV_EMULATOR_LLI_EXECUTABLE@"	67	config.riscv_emulator_lli_executable = "@RISCV_EMULATOR_LLI_EXECUTABLE@"
68	config.riscv_emulator_utils_lib_dir = "@RISCV_EMULATOR_UTILS_LIB_DIR@"	68	config.riscv_emulator_utils_lib_dir = "@RISCV_EMULATOR_UTILS_LIB_DIR@"
69	config.bspub_davinci_bishengir = @BSPUB_DAVINCI_BISHENGIR@	69	config.bspub_davinci_bishengir = @BSPUB_DAVINCI_BISHENGIR@
		70	+config.bspub_davinci_bishengir_a5 = @LLVM_BSPUB_DAVINCI_BISHENGIR_A5@
70		71
71	import lit.llvm	72	import lit.llvm
72	lit.llvm.initialize(lit_config, config)	73	lit.llvm.initialize(lit_config, config)