| 文件 | 最后提交记录 | 最后更新时间 |
|---|---|---|
[mlir][ArmSME] Use liveness information in the tile allocator (#90448) This patch rewrites the ArmSME tile allocator to use liveness information to make better tile allocation decisions and improve the correctness of the ArmSME dialect. This algorithm used here is a linear scan over live ranges, where live ranges are assigned to tiles as they appear in the program (chronologically). Live ranges release their assigned tile ID when the current program point is passed their end. This is a greedy algorithm (which is mainly to keep the implementation relatively straightforward), and because it seems to be sufficient for most kernels (e.g. matmuls) that use ArmSME. The general steps of this are roughly from https://link.springer.com/content/pdf/10.1007/3-540-45937-5_17.pdf, though there have been a few simplifications and assumptions made for our use case. Hopefully, the only changes needed for a user of the ArmSME dialect is that: - -allocate-arm-sme-tiles will no longer be a standalone pass - -test-arm-sme-tile-allocation is only for unit tests - -convert-arm-sme-to-llvm must happen after -convert-scf-to-cf - SME tile allocation is now part of the LLVM conversion By integrating this into the ArmSME -> LLVM conversion we can allow high-level (value-based) ArmSME operations to be side-effect-free, as we can guarantee nothing will rearrange ArmSME operations before we emit intrinsics (which could invalidate the tile allocation). The hope is for ArmSME operations to have no hidden state/side effects and allow easily lowering dialects such as vector and arith to SME, without making assumptions about how the input IR looks, as the semantics of the operations will be the same. That is no (new) side effects and the IR follows the rules of SSA (a value will never change). The aim is correctness, so we have a base for working on optimizations. | 2 年前 | |
[mlir][ArmSME] Use liveness information in the tile allocator (#90448) This patch rewrites the ArmSME tile allocator to use liveness information to make better tile allocation decisions and improve the correctness of the ArmSME dialect. This algorithm used here is a linear scan over live ranges, where live ranges are assigned to tiles as they appear in the program (chronologically). Live ranges release their assigned tile ID when the current program point is passed their end. This is a greedy algorithm (which is mainly to keep the implementation relatively straightforward), and because it seems to be sufficient for most kernels (e.g. matmuls) that use ArmSME. The general steps of this are roughly from https://link.springer.com/content/pdf/10.1007/3-540-45937-5_17.pdf, though there have been a few simplifications and assumptions made for our use case. Hopefully, the only changes needed for a user of the ArmSME dialect is that: - -allocate-arm-sme-tiles will no longer be a standalone pass - -test-arm-sme-tile-allocation is only for unit tests - -convert-arm-sme-to-llvm must happen after -convert-scf-to-cf - SME tile allocation is now part of the LLVM conversion By integrating this into the ArmSME -> LLVM conversion we can allow high-level (value-based) ArmSME operations to be side-effect-free, as we can guarantee nothing will rearrange ArmSME operations before we emit intrinsics (which could invalidate the tile allocation). The hope is for ArmSME operations to have no hidden state/side effects and allow easily lowering dialects such as vector and arith to SME, without making assumptions about how the input IR looks, as the semantics of the operations will be the same. That is no (new) side effects and the IR follows the rules of SSA (a value will never change). The aim is correctness, so we have a base for working on optimizations. | 2 年前 | |
[mlir][ArmSME] Disallow streaming mode for gathers/scatters (#96209) Ideally, this would be based on target information (but we don't really have that), so this currently errs on the side of caution. If possible gathers/scatters should be lowered regular vector loads/stores before using invoking enable-arm-streaming. | 2 年前 | |
[mlir][ArmSME] Disallow streaming mode for gathers/scatters (#96209) Ideally, this would be based on target information (but we don't really have that), so this currently errs on the side of caution. If possible gathers/scatters should be lowered regular vector loads/stores before using invoking enable-arm-streaming. | 2 年前 | |
[mlir][ArmSME][test] Prepare tests for tile allocation changes (#91358) This patch: 1. Removes some duplicate test cases 2. Removes unnecessary uses of -convert-arm-sme-to-llvm 3. Ensures tile values have uses via test.some_use() 1 and 2 will make these tests easier to update. 3 will be needed as ArmSME operations will be pure. | 2 年前 | |
[mlir][ArmSME] Audit ArmSME load/store ops (#139573) This patch updates the following ArmSME ops to require that input and output element types match: * arm_sme.tile_load, arm_sme.tile_store, arm_sme.tile_load_slice, arm_sme.tile_store_slice. In addition, it ensures that the base memref operand for tile_load and tile_store is always rank-2, aligning with the semantics of Arm SME tiles (always rank-2). This change is effectively a follow-up to #135151: * "[mlir][vector] Tighten the semantics of vector.{load|store}" The patch also updates createLoadStoreForOverTileSlices in ArmSMEToSCF.cpp to fail when processing invalid tile stores like the following: mlir arm_sme.tile_store %arg0, %arg1[%c0] : memref<?x4xi8>, vector<[4]x[4]xi32> This particular change fixes #118769. As noted in the TODO, we should further extend op verification logic — I plan to address that in a follow-up patch. | 1 年前 | |
[mlir][ArmSME] Update OuterProductFusion to account for recent changes (#102125) - Use vector.interleave rather than the LLVM intrinsic - Remove dependency on LLVM dialect - Remove manual outerproduct erases (these are now trivially dead) - Remove comment explaining issues with previous tile allocator - Update pipeline in multi-tile-matmul-mixed-types.mlir Recent changes: #90448, #80965 | 2 年前 | |
[mlir][ArmSME] Rename slice move operations to insert/extract_tile_slice (#106755) This renames: - arm_sme.move_tile_slice_to_vector to arm_sme.extract_tile_slice - arm_sme.move_vector_to_tile_slice to arm_sme.insert_tile_slice The new names are more consistent with the rest of MLIR and should be easier to understand. The current names (to me personally) are hard to parse and easy to mix up when skimming through code. Additionally, the syntax for insert_tile_slice has changed from: mlir %4 = arm_sme.insert_tile_slice %0, %1, %2 : vector<[16]xi8> into vector<[16]x[16]xi8> To: mlir %4 = arm_sme.insert_tile_slice %0, %1[%2] : vector<[16]xi8> into vector<[16]x[16]xi8> This is for consistency with extract_tile_slice, but also helps with readability as it makes it clear which operand is the index. | 1 年前 | |
[mlir][ArmSME] Rename slice move operations to insert/extract_tile_slice (#106755) This renames: - arm_sme.move_tile_slice_to_vector to arm_sme.extract_tile_slice - arm_sme.move_vector_to_tile_slice to arm_sme.insert_tile_slice The new names are more consistent with the rest of MLIR and should be easier to understand. The current names (to me personally) are hard to parse and easy to mix up when skimming through code. Additionally, the syntax for insert_tile_slice has changed from: mlir %4 = arm_sme.insert_tile_slice %0, %1, %2 : vector<[16]xi8> into vector<[16]x[16]xi8> To: mlir %4 = arm_sme.insert_tile_slice %0, %1[%2] : vector<[16]xi8> into vector<[16]x[16]xi8> This is for consistency with extract_tile_slice, but also helps with readability as it makes it clear which operand is the index. | 1 年前 | |
[mlir][ArmSME] Use liveness information in the tile allocator (#90448) This patch rewrites the ArmSME tile allocator to use liveness information to make better tile allocation decisions and improve the correctness of the ArmSME dialect. This algorithm used here is a linear scan over live ranges, where live ranges are assigned to tiles as they appear in the program (chronologically). Live ranges release their assigned tile ID when the current program point is passed their end. This is a greedy algorithm (which is mainly to keep the implementation relatively straightforward), and because it seems to be sufficient for most kernels (e.g. matmuls) that use ArmSME. The general steps of this are roughly from https://link.springer.com/content/pdf/10.1007/3-540-45937-5_17.pdf, though there have been a few simplifications and assumptions made for our use case. Hopefully, the only changes needed for a user of the ArmSME dialect is that: - -allocate-arm-sme-tiles will no longer be a standalone pass - -test-arm-sme-tile-allocation is only for unit tests - -convert-arm-sme-to-llvm must happen after -convert-scf-to-cf - SME tile allocation is now part of the LLVM conversion By integrating this into the ArmSME -> LLVM conversion we can allow high-level (value-based) ArmSME operations to be side-effect-free, as we can guarantee nothing will rearrange ArmSME operations before we emit intrinsics (which could invalidate the tile allocation). The hope is for ArmSME operations to have no hidden state/side effects and allow easily lowering dialects such as vector and arith to SME, without making assumptions about how the input IR looks, as the semantics of the operations will be the same. That is no (new) side effects and the IR follows the rules of SSA (a value will never change). The aim is correctness, so we have a base for working on optimizations. | 2 年前 | |
[mlir][ArmSME] Rename slice move operations to insert/extract_tile_slice (#106755) This renames: - arm_sme.move_tile_slice_to_vector to arm_sme.extract_tile_slice - arm_sme.move_vector_to_tile_slice to arm_sme.insert_tile_slice The new names are more consistent with the rest of MLIR and should be easier to understand. The current names (to me personally) are hard to parse and easy to mix up when skimming through code. Additionally, the syntax for insert_tile_slice has changed from: mlir %4 = arm_sme.insert_tile_slice %0, %1, %2 : vector<[16]xi8> into vector<[16]x[16]xi8> To: mlir %4 = arm_sme.insert_tile_slice %0, %1[%2] : vector<[16]xi8> into vector<[16]x[16]xi8> This is for consistency with extract_tile_slice, but also helps with readability as it makes it clear which operand is the index. | 1 年前 | |
[mlir][ArmSME] Remove empty line in test (NFC) (#92404) | 2 年前 | |
[mlir][ArmSME] Merge consecutive arm_sme.intr.zero ops (#106215) This merges consecutive SME zero intrinsics within a basic block, which avoids the backend eventually emitting multiple zero instructions when it could just use one. Note: This kind of peephole optimization could be implemented in the backend too. | 1 年前 | |
[mlir][ArmSME] Remove ConvertIllegalShapeCastOpsToTransposes (#139706) As a follow-up to PR #135841 (see discussion for background), this patch removes the ConvertIllegalShapeCastOpsToTransposes pattern from the SME legalization pass. This change unblocks folding for ShapeCastOp involving scalable vectors. Originally, the ConvertIllegalShapeCastOpsToTransposes pattern was introduced to rewrite certain vector.shape_cast ops that could not be lowered otherwise. Based on local end-to-end testing, this workaround is no longer required, and the pattern can now be safely removed. This patch also removes a special case from ShapeCastOp::fold, simplifying the fold logic. As a side effect of removing ConvertIllegalShapeCastOpsToTransposes, we lose the mechanism that enabled lowering of certain ops like: mlir %res = vector.transfer_read %mem[%a, %b] (...) : memref<?x?xf32>, vector<[4]x1xf32> Previously, such cases were handled by: * Rewriting a nearby vector.shape_cast to a vector.transpose (via ConvertIllegalShapeCastOpsToTransposes) * Then lowering the result with LiftIllegalVectorTransposeToMemory. This patch introduces a new dedicated pattern, LowerColumnTransferReadToLoops, that directly handles illegal vector.transfer_read ops involving leading scalable dimensions. | 1 年前 |
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