| 文件 | 最后提交记录 | 最后更新时间 |
|---|---|---|
[mlir][amdgpu] Add lowerings for ScaledExtPacked816 (#168123) * Adds lowerings for amdgpy.scaled_ext_packed816 * updates verifiers | 8 个月前 | |
[mlir][amx] Optional stride for tile load and store (#159569) Adds an optional stride argument to amx.tile_load and amx.tile_store operations. The stride argument aligns ops closer to the hardware intrinsics. However, stride remains optional to preserve current op behavior. Explicit stride allows greater flexibility in terms of the base buffer shapes and allows different read and write memory patterns. When stride is not provided, it is inferred from the buffer shape as before. Operations documentation is expanded to make ops easier to use. | 9 个月前 | |
[MLIR][Affine] Extend getVectorReductionOp to support xor/maxnumf/minnumf (#163310) This PR extends the getVectorReductionOp function, which is used by the affine vectorizer, to also recognize and support xor/maxnumf/minnumf reduction operations. | 8 个月前 | |
Add 'exact' flag to arith.shrui/shrsi/divsi/divui operations (#165923) This MR adds support for the exact flag to the arith.shrui/shrsi/divsi/divui operations. The semantics are identical to those of the LLVM dialect and the LLVM language reference. This MR also modifies the mechanism for converting arith dialect **attributes** to corresponding **properties** in the LLVM dialect. (As a specific example, the integer overflow flags nsw/nuw are **properties** in the LLVM dialect, as opposed to attributes.) Previously, attribute converter classes were required to have a specific method to support integer overflow flags: C++ template <typename SourceOp, typename TargetOp> class AttrConvertPassThrough { public: ... LLVM::IntegerOverflowFlags getOverflowFlags() const { return LLVM::IntegerOverflowFlags::none; } }; This method was required, even for arith source operations that did not use integer overflow flags (e.g. AttrConvertFastMathToLLVM). This MR modifies the interface required by arith dialect attribute converters to instead provide a (possibly NULL) properties attribute: C++ template <typename SourceOp, typename TargetOp> class AttrConvertPassThrough { public: ... Attribute getPropAttr() const { return {}; } }; For arith operations with attributes that map to LLVM dialect **properties**, the attribute converter can create a DictionaryAttr containing target properties and return that attribute from the attribute converter's getPropAttr() method. The arith attribute conversion framework will set the propertiesAttr of an OperationState, and the target operation's setPropertiesFromAttr() method will be invoked to set the properties when the target operation is created. The AttrConvertOverflowToLLVM class in this MR uses the new approach. | 8 个月前 | |
[MLIR][AArch64] Lower vector.contract to Neon FEAT_BF16 operations (#148198) This builds upon the framework established by https://github.com/llvm/llvm-project/pull/149810 to add lowering to bfmmla. | 1 年前 | |
[mlir][ArmSME] Remove ConvertIllegalShapeCastOpsToTransposes (#139706) As a follow-up to PR #135841 (see discussion for background), this patch removes the ConvertIllegalShapeCastOpsToTransposes pattern from the SME legalization pass. This change unblocks folding for ShapeCastOp involving scalable vectors. Originally, the ConvertIllegalShapeCastOpsToTransposes pattern was introduced to rewrite certain vector.shape_cast ops that could not be lowered otherwise. Based on local end-to-end testing, this workaround is no longer required, and the pattern can now be safely removed. This patch also removes a special case from ShapeCastOp::fold, simplifying the fold logic. As a side effect of removing ConvertIllegalShapeCastOpsToTransposes, we lose the mechanism that enabled lowering of certain ops like: mlir %res = vector.transfer_read %mem[%a, %b] (...) : memref<?x?xf32>, vector<[4]x1xf32> Previously, such cases were handled by: * Rewriting a nearby vector.shape_cast to a vector.transpose (via ConvertIllegalShapeCastOpsToTransposes) * Then lowering the result with LiftIllegalVectorTransposeToMemory. This patch introduces a new dedicated pattern, LowerColumnTransferReadToLoops, that directly handles illegal vector.transfer_read ops involving leading scalable dimensions. | 1 年前 | |
[mlir][vector] Avoid setting padding by default to 0 in vector.transfer_read prefer ub.poison (#146088) Context: vector.transfer_read always requires a padding value. Most of its builders take no padding value and assume the safe value of 0. However, this should be a conscious choice by the API user, as it makes it easy to introduce bugs. For example, I found several occasions while making this patch that the padding value was not getting propagated (vector.transfer_read was transformed into another vector.transfer_read). These bugs, were always caused because of constructors that don't require specifying padding. Additionally, using ub.poison as a possible default value is better, as it indicates the user "doesn't care" about the actual padding value, forcing users to specify the actual padding semantics they want. With that in mind, this patch changes the builders in vector.transfer_read to always having a std::optional<Value> padding argument. This argument is never optional, but for convenience users can pass std::nullopt, padding the transfer read with ub.poison. --------- Signed-off-by: Fabian Mora <fabian.mora-cordero@amd.com> | 1 年前 | |
[mlir][async]: Make async.execute operation with RecursiveMemoryEffects trait (#116544) | 11 个月前 | |
[mlir][bufferization] Refine tensor-buffer compatibility checks (#167705) Generally, to_tensor and to_buffer already perform sufficient verification. However, there are some unnecessarily strict constraints: * builtin tensor requires its buffer counterpart to always be memref * to_buffer on ranked tensor requires to always return memref These checks are assertions (i.e. preconditions), however, they actually prevent an apparently useful bufferization where builtin tensors could become custom buffers. Lift these assertions, maintaining the verification procedure unchanged, to allow builtin -> custom bufferizations at operation boundary level. | 8 个月前 | |
[mlir] Add a builtin distinct attribute A distinct attribute associates a referenced attribute with a unique identifier. Every call to its create function allocates a new distinct attribute instance. The address of the attribute instance temporarily serves as its unique identifier. Similar to the names of SSA values, the final unique identifiers are generated during pretty printing. Examples: #distinct = distinct[0]<42.0 : f32> #distinct1 = distinct[1]<42.0 : f32> #distinct2 = distinct[2]<array<i32: 10, 42>> This mechanism is meant to generate attributes with a unique identifier, which can be used to mark groups of operations that share a common properties such as if they are aliasing. The design of the distinct attribute ensures minimal memory footprint per distinct attribute since it only contains a reference to another attribute. All distinct attributes are stored outside of the storage uniquer in a thread local store that is part of the context. It uses one bump pointer allocator per thread to ensure distinct attributes can be created in-parallel. Reviewed By: rriddle, Dinistro, zero9178 Differential Revision: https://reviews.llvm.org/D153360 | 3 年前 | |
[MLIR] Add new complex.powi op (#158722) This PR adds a new complex.powi operation to MLIR's complex dialect for computing complex numbers raised to integer powers. Key changes include: - Addition of the new PowiOp operation definition in the Complex dialect - Integration with algebraic simplification passes for optimization - Support for conversion to ROCDL library calls - Updates to Flang frontend to generate the new operation This depends on #158642. | 10 个月前 | |
[MLIR][CF] Avoid collapsing blocks which participate in cycles (#160783) Previously, collapseBranch did not return failure for successor blocks which were part of a cycle. mlir-opt --canonicalize would run indefinitely for any N-block cycle which is kicked off with an unconditional jump. The simplifyPassThroughBr transform would continue alternating which block was targeted in ^bb0, resulting in an infinite loop. collapseBranch will not result in any useful transformation on blocks which participate in cycles, since the block is aliased by a different block. To avoid this, we can check for cycles in collapseBranch and abort when one is detected. Simplification of the cycle is left for other transforms. Fixes #159743. | 9 个月前 | |
[MLIR][DLTI] Pretty parsing and printing for DLTI attrs (#113365) Unifies parsing and printing for DLTI attributes. Introduces a format of #dlti.attr<key1 = val1, ..., keyN = valN> syntax for all queryable DLTI attributes similar to that of the DictionaryAttr, while retaining support for specifying key-value pairs with #dlti.dl_entry (whether to retain this is TBD). As the new format does away with most of the boilerplate, it is much easier to parse for humans. This makes an especially big difference for nested attributes. Updates the DLTI-using tests and includes fixes for misc error checking/ error messages. | 1 年前 | |
| 8 个月前 | ||
[MLIR] Fix FileCheck annotations and add 32-bit coverage (#167149) Addresses #93154 by ensuring the test RUN/FILECHECK prefixes across mlir/test/Conversion/FuncToLLVM/ and related files match their expected outputs, and adds an index-bitwidth=32 variant of expand-then-convert-to-llvm.mlir that exercises @collapse_shape_dynamic_with_non_identity_layout through the same MemRef-to-LLVM pipeline so the 32-bit layout descriptors are verified. | 8 个月前 | |
| 8 个月前 | ||
[MLIR][IRDL] Support camelCase segment size attributes in IRDL verifier (#168836) Two years ago, operand_segment_sizes and result_segment_sizes were renamed to operandSegmentSizes and resultSegmentSizes (check related commits, e.g. https://github.com/llvm/llvm-project/commit/363b655920c49a4bcb0869f820ed40aac834eebd). However, the op verifiers in IRDL loading phase is still using old attributes like operand_segment_sizes and result_segment_sizes, which causes some conflict, e.g. it is not compatible with the OpView builder in MLIR python bindings (which generates camelCase segment attributes). This PR is to support to use camelCase segment size attributes in IRDL verifier. Note that support of operand_segment_sizes and result_segment_sizes is dropped. I found this issue since I'm working on a new IRDL wrapper in the MLIR python bindings. | 8 个月前 | |
[MLIR] Add canonicalizations to all eligible index binary ops (#114000) Generalizes the following canonicalization pattern to all associative and commutative binary ops in the index dialect. x = v + c1 y = x + c2 --> y = x + (c1 + c2) This includes: - AddOp - MulOp - MaxSOp - MaxUOp - MinSOp - MinUOp - AndOp - OrOp - XOrOp The operation folding is implemented using the existing folders since createAndFold is used in the canonicalization. | 1 年前 | |
[mlir][LLVM] Switch undef for poison for uninitialized values (#125629) LLVM itself is generally moving away from using undef and towards using poison, to the point of having a lint that caches new uses of undef in tests. In order to not trip the lint on new patterns and to conform to the evolution of LLVM - Rename valious ::undef() methods on StructBuilder subclasses to ::poison() - Audit the uses of UndefOp in the MLIR libraries and replace almost all of them with PoisonOp The remaining uses of undef are initializing uninitialized memrefs, explicit conversions to undef from SPIR-V, and a few cases in AMDGPUToROCDL where usage like %v = insertelement <M x iN> undef, iN %v, i32 0 %arg = bitcast <M x iN> %v to i(M * N) is used to handle "i32" arguments that are are really packed vectors of smaller types that won't always be fully initialized. | 1 年前 | |
[mlir][ROCDL] Adds wmma scaled intrinsics for gfx1250 (#165915) Signed-off-by: Muzammiluddin Syed <muzasyed@amd.com> | 8 个月前 | |
[mlir][SCF] Add scf::tileAndFuseConsumer that tiles a consumer into a given tiled loop nest. (#167634) The existing scf::tileAndFuseConsumerOfSlices takes a list of slices (and loops they are part of), tries to find the consumer of these slices (all slices are expected to be the same consumer), and then tiles the consumer into the loop nest using the TilingInterface. A more natural way of doing consumer fusion is to just start from the consumer, look for operands that are produced by the loop nest passed in as loops (presumably these loops are generated by tiling, but that is not a requirement for consumer fusion). Using the consumer you can find the slices of the operands that are accessed within the loop which you can then use to tile and fuse the consumer (using TilingInterface). This handles more naturally the case where multiple operands of the consumer come from the loop nest. The scf::tileAndFuseConsumerOfSlices was implemented as a mirror of scf::tileAndFuseProducerOfSlice. For the latter, the slice has a single producer for the source of the slice, which makes it a natural way of specifying producer fusion. But for consumers, the result might have multiple users, resulting in multiple candidates for fusion, as well as a fusion candidate using multiple results from the tiled loop nest. This means using slices (tensor.insert_slice/tensor.parallel_insert_slice) as a hook for consumer fusion turns out to be quite hard to navigate. The use of the consumer directly avoids all those pain points. In time the scf::tileAndFuseConsumerOfSlices should be deprecated in favor of scf::tileAndFuseConsumer. There is a lot of tech-debt that has accumulated in scf::tileAndFuseConsumerOfSlices that needs to be cleanedup. So while that gets cleaned up, and required functionality is moved to scf::tileAndFuseConsumer, the old path is still maintained. The test for scf::tileAndFuseConsumerUsingSlices is copied to tile-and-fuse-consumer.mlir to tile-and-fuse-consumer-using-slices.mlir. All the tests that were there in this file are now using the tileAndFuseConsumer method. The test op test.tile_and_fuse_consumer is modified to call scf::tileAndFuseConsumer, while a new op test.tile_and_fuse_consumer_of_slice is used to keep the old path tested while it is deprecated. --------- Signed-off-by: MaheshRavishankar <mahesh.ravishankar@gmail.com> | 8 个月前 | |
[mlir] Make the ml_program dialect allow all of its operations to be inlined. (#85479) | 2 年前 | |
| 1 年前 | ||
[MLIR][Vector] Remove vector.splat (#162167) vector.splat has been deprecated (user: please use the very similar vector.broadcast instead) with the last PR landing about 6 weeks ago. The discourse discussion is at https://discourse.llvm.org/t/rfc-mlir-vector-deprecate-then-remove-vector-splat/87143/1 The last PR was #152230 This PR completely removes vector.splat. In addition to removing vector.splat from VectorOps.td, it - Updates the few remaining places where vector::SplatOp is created (now vector::BroadcastOp is created) - Removes temporary patterns where vector.splat is replaced by vector.broadcast The only place 'vector.splat' appears is now the files https://github.com/llvm/llvm-project/blob/main/mlir/utils/tree-sitter-mlir/test/corpus/op.txt and https://github.com/llvm/llvm-project/blob/main/mlir/utils/tree-sitter-mlir/dialect/vector.js --------- Signed-off-by: James Newling <james.newling@gmail.com> | 9 个月前 | |
[MemRef] Remove memref.dim OffsetSizeAndStrideOpInterface folding (#169327) OffsetSizeAndStrideOpInterface does not specify whether it's operating on the input or output shape and in fact different ops implement this in different ways, which is also why SubviewOp is special cased here. This "marked as dynamic but not really dynamic" folding is better handled by shape inference, so just remove the bad fold. | 8 个月前 | |
[mlir][nvgpu] Add tma last dim bytes check (#153451) Add the check the number of bytes in the last dimension of Tma must be a multiple of 16. | 11 个月前 | |
[mlir][acc] Adds attr to acc.present to identify default clause origin (#169114) The acc.present Op as generated by ACCImplicitData does not provide a way to differentiate between acc.present ops that are generated implicitly and the ones that are generated as result of an explicit default(present) clause in the source code. This differentiation would allow for better communication to the user on the decisions made by the compiler while managing data automatically between the host and the device. This commit adds this information as a discardable attribute on the acc.present op. | 8 个月前 | |
[Flang][mlir] - Translation of delayed privatization for deferred target-tasks (#155348) This PR adds support for translation of the private clause on deferred target tasks - that is omp.target operations with the nowait clause. An offloading call for a deferred target-task is not blocking - the offloading (target-generating) host task continues its execution after issuing the offloading call. Therefore, the key problem we need to solve is to ensure that the data needed for private variables to be initialized in the target task persists even after the host task has completed. We do this in a new pass called PrepareForOMPOffloadPrivatizationPass. For a privatized variable that needs its host counterpart for initialization (such as the shape of the data from the descriptor when an allocatable is privatized or the value of the data when an allocatable is firstprivatized), - the pass allocates memory on the heap. - it then initializes this memory by using the init and copy (for firstprivate) regions of the corresponding omp::PrivateClauseOp. - Finally the memory allocated on the heap is freed using the dealloc region of the same omp::PrivateClauseOp instance. This step is not straightforward though, because we cannot simply free the memory that's going to be used by another thread without any synchronization. So, for deallocation, we create a omp.task after the omp.target and synchronize the two with a dummy dependency (using the depend clause). In this newly created omp.task we do the deallocation. | 9 个月前 | |
Reapply "[mlir][PDL] Add support for native constraints with results (#82760)" with a small stack-use-after-scope fix in getConstraintPredicates() This reverts commit c80e6edba4a9593f0587e27fa0ac825ebe174afd. | 2 年前 | |
Finish renaming getOperandSegmentSizeAttr() from operand_segment_sizes to operandSegmentSizes This renaming started with the native ODS support for properties, this is completing it. A mass automated textual rename seems safe for most codebases. Drop also the ods prefix to keep the accessors the same as they were before this change: properties.odsOperandSegmentSizes reverts back to: properties.operandSegementSizes The ODS prefix was creating divergence between all the places and make it harder to be consistent. Reviewed By: jpienaar Differential Revision: https://reviews.llvm.org/D157173 | 2 年前 | |
[mlir][ptr] Add ptr.ptr_diff operation (#157354) Thi patch introduces the ptr.ptr_diff operation for computing pointer differences. The semantics of the operation are given by: `` The ptr_diff operation computes the difference between two pointers, returning an integer or index value representing the number of bytes between them. The operation supports both scalar and shaped types with value semantics: - When both operands are scalar: produces a single difference value - When both are shaped: performs element-wise subtraction, shapes must be the same The operation also supports the following flags: - none: No flags are set. - nuw: No Unsigned Wrap, if the subtraction causes an unsigned overflow, the result is a poison value. - nsw: No Signed Wrap, if the subtraction causes a signed overflow, the result is a poison value. NOTE: The pointer difference is calculated using an integer type specified by the data layout. The final result will be sign-extended or truncated to fit the result type as necessary. ` This patch also adds translation to LLVM IR hooks for the ptr_diff op. This translation uses the ptrtoaddr builder to compute only index bits difference. Example: mlir llvm.func @ptr_diff_vector_i32(%ptrs1: vector<8x!ptr.ptr<#llvm.address_space<0>>>, %ptrs2: vector<8x!ptr.ptr<#llvm.address_space<0>>>) -> vector<8xi32> { %diffs = ptr.ptr_diff %ptrs1, %ptrs2 : vector<8x!ptr.ptr<#llvm.address_space<0>>> -> vector<8xi32> llvm.return %diffs : vector<8xi32> } Translation to LLVM IR: llvm define <8 x i32> @ptr_diff_vector_i32(<8 x ptr> %0, <8 x ptr> %1) { %3 = ptrtoint <8 x ptr> %0 to <8 x i64> %4 = ptrtoint <8 x ptr> %1 to <8 x i64> %5 = sub <8 x i64> %3, %4 %6 = trunc <8 x i64> %5 to <8 x i32> ret <8 x i32> %6 } ` --------- Co-authored-by: Mehdi Amini <joker.eph@gmail.com> | 10 个月前 | |
Sub-channel quantized type implementation (#120172) This is an implementation for [RFC: Supporting Sub-Channel Quantization in MLIR](https://discourse.llvm.org/t/rfc-supporting-sub-channel-quantization-in-mlir/82694). In order to make the review process easier, the PR has been divided into the following commit labels: 1. **Add implementation for sub-channel type:** Includes the class design for UniformQuantizedSubChannelType, printer/parser and bytecode read/write support. The existing types (per-tensor and per-axis) are unaltered. 2. **Add implementation for sub-channel type:** Lowering of quant.qcast and quant.dcast operations to Linalg operations. 3. **Adding C/Python Apis:** We first define he C-APIs and build the Python-APIs on top of those. 4. **Add pass to normalize generic ....:** This pass normalizes sub-channel quantized types to per-tensor per-axis types, if possible. A design note: - **Explicitly storing the quantized_dimensions, even when they can be derived for ranked tensor.** While it's possible to infer quantized dimensions from the static shape of the scales (or zero-points) tensor for ranked data tensors ([ref](https://discourse.llvm.org/t/rfc-supporting-sub-channel-quantization-in-mlir/82694/3) for background), there are cases where this can lead to ambiguity and issues with round-tripping. Consider the example: tensor<2x4x!quant.uniform<i8:f32:{0:2, 0:2}, {{s00:z00, s01:z01}}>> The shape of the scales tensor is [1, 2], which might suggest that only axis 1 is quantized. While this inference is technically correct, as the block size for axis 0 is a degenerate case (equal to the dimension size), it can cause problems with round-tripping. Therefore, even for ranked tensors, we are explicitly storing the quantized dimensions. Suggestions welcome! PS: I understand that the upcoming holidays may impact your schedule, so please take your time with the review. There's no rush. | 1 年前 | |
[MLIR] Revamp RegionBranchOpInterface (#165429) This is still somehow a WIP, we have some issues with this interface that are not trivial to solve. This patch tries to make the concepts of RegionBranchPoint and RegionSuccessor more robust and aligned with their definition: - A RegionBranchPoint is either the parent (RegionBranchOpInterface) op or a RegionBranchTerminatorOpInterface operation in a nested region. - A RegionSuccessor is either one of the nested region or the parent RegionBranchOpInterface Some new methods with reasonnable default implementation are added to help resolving the flow of values across the RegionBranchOpInterface. It is still not trivial in the current state to walk the def-use chain backward with this interface. For example when you have the 3rd block argument in the entry block of a for-loop, finding the matching operands requires to know about the hidden loop iterator block argument and where the iterargs start. The API is designed around forward-tracking of the chain unfortunately. Try to reland #161575 ; I suspect a buildbot incremental build issue. | 8 个月前 | |
[mlir][SMT] upstream SMT dialect (#131480) This PR upstreams the SMT dialect from the CIRCT project. Here we only check in the dialect/op/types/attributes and lit tests. Follow up PRs will add conversions in and out and etc. Co-authored-by: Bea Healy <beahealy22@gmail.com> Co-authored-by: Martin Erhart <maerhart@outlook.com> Co-authored-by: Mike Urbach <mikeurbach@gmail.com> Co-authored-by: Will Dietz <will.dietz@sifive.com> Co-authored-by: fzi-hielscher <hielscher@fzi.de> Co-authored-by: Fehr Mathieu <mathieu.fehr@gmail.com> | 1 年前 | |
[mlir][spirv] Add support for SwitchOp (#168713) The dialect implementation mostly copies the one of cf.switch, but aligns naming to the SPIR-V spec. | 8 个月前 | |
[mlir][bufferization][NFC] Rename to_memref to to_buffer (#137180) As part of the work on transitioning bufferization dialect, ops, and associated logic to operate on newly added type interfaces (see 00eaff3e9c897c263a879416d0f151d7ca7eeaff), rename the bufferization.to_memref to highlight the generic nature of the op. Bufferization process produces buffers while memref is a builtin type rather than a generic term. Preserve the current API (to_buffer still produces a memref), however, as the new type interfaces are not used yet. | 1 年前 | |
[NFC][mlir][mesh,shard] Fixing misnomers in mesh dialect, renaming 'mesh' dialect to 'shard' (#150177) Dialect to 'shard' (discourse 87053) - dialect name mesh -> shard - (device) mesh -> (device) grid - spmdize -> partition A lot of diffs, but simple renames only. @tkarna @yaochengji | 1 年前 | |
[mlir][SCF] Add scf.index_switch support for populateSCFStructuralTypeConversionsAndLegality (#160344) In a downstream project, there is a need for a type conversion pattern for scf.index_switch operation. A test is added into mlir/test/Dialect/SparseTensor/scf_1_N_conversion.mlir (not sure this functionality is really required for sparse tensors, but the test showcase that the new conversion pattern is functional) | 10 个月前 | |
[mlir][linalg] Genericize MapOp (#162742) This PR modifies the definition of linalg::MapOp so that it has the same structure of linalg::GenericOp and all other linalg ops. Mainly, it adds an out bbarg for the body of the op. Although the out arg is never used in the body, there doesn't seem to be much benefit in specializing the op to exclude it. In fact it only makes things more complicated because it doesn't align with the GenericOp structure. For example, linalg-generalize-named-ops avoided converting linalg.map purely because it didn't have the structure to do so. Moreover, although some fusion patterns are applied explicitly to GenericOp, we can change them to be applied to the base LinalgOp which will enable fusion for any fusion-compatible linalg op, but that requires the op having a generic structure. So these changes will enable us to use existing generic transformation patterns on MapOp that weren't possible before. They can either be applied to MapOp directly or applied after converting to GenericOp. | 8 个月前 | |
[mlir][tosa] Fix select folder when operands are broadcast (#165481) This commit addresses a crash in the dialects folder. The currently folder assumes no broadcasting of the input operand happens and therefore the folder can complain that the returned value was not the same shape as the result. For now, this commit ensures no folding happens when broadcasting is involved. In the future, folding with a broadcast could likely be supported by inserting a tosa.tile operation before returning the operand. This type of transformation is likely better suited for a canonicalization pass. This commit only aims to avoid the crash. | 8 个月前 | |
[mlir][Pass] Fix crash when applying a pass to an optional interface (#169262) Interfaces can be optional: whether an op implements an interface or not can depend on the state of the operation. `` // An optional code block for adding additional "classof" logic. This can // be used to better enable "optional" interfaces, where an entity only // implements the interface if some dynamic characteristic holds. // $_attr/$_op/$_type may be used to refer to an instance of the // interface instance being checked. code extraClassOf = ""; ` The current Pass::canScheduleOn(RegisteredOperationName) is insufficient. This commit adds an additional overload to inspect Operation *. This commit fixes a crash when scheduling an InterfacePass` for an optional interface on an operation that does not actually implement the interface. This is a re-upload of #168499, which was reverted. | 8 个月前 | |
[MLIR][UB] Add inliner interface for UB dialect (#67115) This revision adds an inliner interface to the UB dialect that allows inlining of ub.poison operations. | 2 年前 | |
[mlir][Vector] Add support for scalable vectors to ScanToArithOps (#123117) Note, scalable reductions dims are left as a TODO. | 8 个月前 | |
[MLIR][WASM] Control flow, conversion and comparison in Wasm importer (#154674) This is the following of PR #154452. It extend Wasm binary to Wasm SSA importer with support of control flow operations, comparison operations and conversion operations. --------- Co-authored-by: Ferdinand Lemaire <ferdinand.lemaire@woven-planet.global> Co-authored-by: Jessica Paquette <jessica.paquette@woven-planet.global> Co-authored-by: Luc Forget <luc.forget@woven.toyota> | 9 个月前 | |
[mlir][x86vector] Lower vector.contract to FMA or packed type dot-product (#168074) A transform pass to lower vector.contract to (a) vector.fma for F32, (b) x86vector.avx512.dot for BF16, (c) x86vector.avx.dot.i8 for Int8 packed types. The lowering works on condition with m, batch, k dims to be one and vnni dim should be 2 for bf16; 4 for int8. **The lowering pattern**: batch_reduce.matmul (input) -> register-tiling(M, N) -> Vectorization (to vector.contract) -> unroll vector.contract (unit dims) -> hoisting transformation (move C loads/store outside batch/k loop) -> apply licm, canonicalization, and bufferize. | 8 个月前 | |
[MLIR][XeGPU] Disable block count usage in layout propagation (#168504) | 8 个月前 | |
[MLIR] Allow constFoldBinaryOp to fold (T1, T1) -> T2 (#151410) The constFoldBinaryOp helper function had limited support for different input and output types, but the static type of the underlying value (e.g. APInt) had to match between the inputs and the output. This worked fine for int comparisons of the form (intN, intN) -> int1, as the static type signature was (APInt, APInt) -> APInt. However, float comparisons map (floatN, floatN) -> int1, with a static type signature of (APFloat, APFloat) -> APInt. This use case wasn't supported by constFoldBinaryOp. constFoldBinaryOp now accepts an optional template argument overriding the return type in case it differs from the input type. If the new template argument isn't provided, the default behavior is unchanged (i.e. the return type will be assumed to match the input type). constFoldUnaryOp received similar changes in order to support folding non-cast ops of the form (T1) -> T2 (e.g. a sign op mapping (floatN) -> sint32). | 11 个月前 | |
Released restriction that prevented implicit dynamic-to-static dimension type cast in TOSA ops. Reviewed By: jpienaar, gflegar Differential Revision: https://reviews.llvm.org/D156714 | 2 年前 |
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