| 文件 | 最后提交记录 | 最后更新时间 |
|---|---|---|
Reland "[mlir][gpu] Align reduction operations with vector combining kinds (#73423)" This reverts commit dd09221a29506031415cad8a1308998358633d48 and relands https://github.com/llvm/llvm-project/pull/73423. * Updated gpu.all_reduce min/max in CUDA integration tests. | 2 年前 | |
[mlir][vector][gpu] Align minf/maxf reduction kind names with arith (#75901) This is to avoid confusion when dealing with reduction/combining kinds. For example, see a recent PR comment: https://github.com/llvm/llvm-project/pull/75846#discussion_r1430722175. Previously, they were picked to mostly mirror the names of the llvm vector reduction intrinsics: https://llvm.org/docs/LangRef.html#llvm-vector-reduce-fmin-intrinsic. In isolation, it was not clear if <maxf> has arith.maxnumf or arith.maximumf semantics. The new reduction kind names map 1:1 to arith ops, which makes it easier to tell/look up their semantics. Because both the vector and the gpu dialect depend on the arith dialect, it's more natural to align names with those in arith than with the lowering to llvm intrinsics. Issue: https://github.com/llvm/llvm-project/issues/72354 | 2 年前 | |
[mlir][GPU] Prevent adding duplicate async tokens If, in the GPU async transformation, the operation being given an async dependency already depended on the token in question, we would add duplicate tokens, creating issues in GPU to LLVM lowering. To resolve this issue, add a check to addAsyncDependency() to ensure that duplicate tokens are not present in the token list. (I'm open to a different approach here, this is just what I went with initially) Reviewed By: Mogball Differential Revision: https://reviews.llvm.org/D136105 | 3 年前 | |
[mlir] fix memory effects in GPU barrier elimination (#117432) Existing implementation may trigger infinite cycles when collecting effects above or below the current block after wrapping around a loop-like construct. Limit this case to only looking at the immediate block (loop body). This is correct because wrap around is intended to consider effects of different iterations of the same loop and shouldn't be existing the loop block. Reported-by: Fabian Mora <fmora.dev@gmail.com> Co-authored-by: Fabian Mora <fmora.dev@gmail.com> | 1 年前 | |
[mlir][gpu] Revert gpu.subgroup_broadcast with any_lane (#157373) This partially reverts https://github.com/llvm/llvm-project/pull/152808. Post-commit comments revealed that the any_lane variant hasn't been fully agreed upon at the time of landing. | 10 个月前 | |
[mlir][bufferization] Buffer deallocation: Make op preconditions stricter (#75127) The buffer deallocation pass checks the IR ("operation preconditions") to make sure that there is no IR that is unsupported. In such a case, the pass signals a failure. The pass now rejects all ops with unknown memory effects. We do not know whether such an op allocates memory or not. Therefore, the buffer deallocation pass does not know whether a deallocation op should be inserted or not. Memory effects are queried from the MemoryEffectOpInterface interface. Ops that do not implement this interface but have the RecursiveMemoryEffects trait do not have any side effects (apart from the ones that their nested ops may have). Unregistered ops are now rejected by the pass because they do not implement the MemoryEffectOpInterface and neither do we know if they have RecursiveMemoryEffects or not. All test cases that currently have unregistered ops are updated to use registered ops. | 2 年前 | |
| 1 年前 | ||
[mlir] [memref] add more checks to the memref.reinterpret_cast (#112669) Operation memref.reinterpret_cast was accept input like: %out = memref.reinterpret_cast %in to offset: [%offset], sizes: [10], strides: [1] : memref<?xf32> to memref<10xf32> A problem arises: while lowering, the true offset of %out is %offset, but its data type indicates an offset of 0. Permitting this inconsistency can result in incorrect outcomes, as certain pass might erroneously extract the offset from the data type of %out. This patch fixes this by enforcing that the return value's data type aligns with the input parameter. | 1 年前 | |
[mlir][LLVM] Switch undef for poison for uninitialized values (#125629) LLVM itself is generally moving away from using undef and towards using poison, to the point of having a lint that caches new uses of undef in tests. In order to not trip the lint on new patterns and to conform to the evolution of LLVM - Rename valious ::undef() methods on StructBuilder subclasses to ::poison() - Audit the uses of UndefOp in the MLIR libraries and replace almost all of them with PoisonOp The remaining uses of undef are initializing uninitialized memrefs, explicit conversions to undef from SPIR-V, and a few cases in AMDGPUToROCDL where usage like %v = insertelement <M x iN> undef, iN %v, i32 0 %arg = bitcast <M x iN> %v to i(M * N) is used to handle "i32" arguments that are are really packed vectors of smaller types that won't always be fully initialized. | 1 年前 | |
[mlir][gpu] Add a pattern for transforming gpu.global_id to thread + blockId * blockDim This patch implements a rewrite pattern for transforming gpu.global_id x to gpu.thread_id + gpu.block_id * gpu.block_dim. Reviewed By: makslevental Differential Revision: https://reviews.llvm.org/D148978 | 3 年前 | |
[MLIR][GPU] Fix gpu.printf (#121940) | 1 年前 | |
[mlir][gpu] Revert gpu.subgroup_broadcast with any_lane (#157373) This partially reverts https://github.com/llvm/llvm-project/pull/152808. Post-commit comments revealed that the any_lane variant hasn't been fully agreed upon at the time of landing. | 10 个月前 | |
| 8 个月前 | ||
[mlir][gpu] Add innermost-first policy when mapping loops to GPU IDs (#160634) | 10 个月前 | |
Create function declaration in the proper module (#161281) Using memref.dealloc in the gpu module would add a function definition for @free in the the top level module instead of the gpu module. The fix is to do what is already done for memref.alloc which is to use op->getParentWithTrait<OpTrait::SymbolTable>() instead of op->getParentOfType<ModuleOp>() to create the call in the proper module. | 9 个月前 | |
| 2 年前 | ||
[mlir][target][nvvm] Perf by stage and store into properties (#126178) Implement the feature about perf by stage(llvm-ir -> isa, isa->binary). The results will be stored into the properties, then users can use them after using GpuModuleToBinary Pass. | 1 年前 | |
[MLIR][LLVM] Remove last typed pointer remnants from tests (#71232) This commit removes all LLVM dialect typed pointers from the lit tests. Typed pointers have been deprecated for a while now and it's planned to soon remove them from the LLVM dialect. Related PSA: https://discourse.llvm.org/t/psa-removal-of-typed-pointers-from-the-llvm-dialect/74502 | 2 年前 | |
[mlir][spirv] Implement gpu::TargetAttrInterface (#69949) This commit implements gpu::TargetAttrInterface for SPIR-V target attribute. The plan is to use this to enable GPU compilation pipeline for OpenCL kernels later. The changes do not impact Vulkan shaders using milr-vulkan-runner. New GPU Dialect transform pass spirv-attach-target is implemented for attaching attribute from CLI. gpu-module-to-binary pass now works with GPU module that has SPIR-V module with OpenCL kernel functions inside. | 2 年前 | |
[mlir][gpu] Add uniform flag to gpu reduction ops Differential Revision: https://reviews.llvm.org/D138758 | 3 年前 | |
[MLIR][NVVM] Add ptxas-cmd-options to pass flags to the downstream compiler (#127457) This PR adds cmd-options to the gpu-lower-to-nvvm-pipeline pipeline and the nvvm-attach-target pass, allowing users to pass flags to the downstream compiler, *ptxas*. Example: mlir-opt -gpu-lower-to-nvvm-pipeline="cubin-chip=sm_80 ptxas-cmd-options='-v --register-usage-level=8'" | 1 年前 | |
[MLIR] Fix gpu.launch attribution argument printing (#161408) This was broken and never tested. Not only this could crash for stack-use-after-scope, but it also would have printed something like: value <block argument> of type 'memref<7x8xf64, #gpu.address_space<workgroup>>' at index: 12 insted of the SSA value. It turns out the gpu.func already have a very similar helper that we can reuse here. Fixes #161394 | 9 个月前 | |
| 11 个月前 | ||
[mlir][amdgpu] Promote gpu.shuffle to amdgpu.permlane_swap (#154933) - promote gpu.shuffle %src xor {16,32} 64 to amdgpu.permlane_swap %src {16,32} | 11 个月前 | |
[mlir][Linalg]: Optimize linalg generic in transform::PromoteOp to avoid unnecessary copies (#68555) If the operands are not used in the payload of linalg generic operations, there is no need to copy them before the operation. | 2 年前 | |
[mlir] GPUToROCDL: Fix crashes with unsupported shuffle datatypes (#135504) Calling getIntOrFloatBitWidth on non-int/float types (gpu.shuffle also accepts vectors) will crash. | 1 年前 | |
[mlir][NFC] Update textual references of func to func.func in Bufferization/Complex/EmitC/CF/Func/GPU tests The special case parsing of func operations is being removed. | 4 年前 | |
[mlir][sparse][gpu] add CSC and BSR format to cuSparse GPU ops (#67509) This adds two cuSparse formats to the GPU dialect support. Together with proper lowering and runtime cuda support. Also fixes a few minor omissions. | 2 年前 | |
[mlir][gpu] Clean GPU Passes.h from external SPIRV includes (#71331) Removes the SPIRVAttributes.h header from GPU/Transforms/Passes.h | 2 年前 | |
[mlir] use transform-interpreter in test passes (#70040) Update most test passes to use the transform-interpreter pass instead of the test-transform-dialect-interpreter-pass. The new "main" interpreter pass has a named entry point instead of looking up the top-level op with PossibleTopLevelOpTrait, which is arguably a more understandable interface. The change is mechanical, rewriting an unnamed sequence into a named one and wrapping the transform IR in to a module when necessary. Add an option to the transform-interpreter pass to target a tagged payload op instead of the root anchor op, which is also useful for repro generation. Only the test in the transform dialect proper and the examples have not been updated yet. These will be updated separately after a more careful consideration of testing coverage of the transform interpreter logic. | 2 年前 | |
[MLIR][GPU] Ensure all lanes in cluster have final reduction value (#165764) This is a fix for a cluster size of 32 when the subgroup size is 64. Previously, only lanes [16, 32) u [48, 64) contained the correct clusterwise reduction value. This PR adds a swizzle instruction to broadcast the correct value down to lanes [0, 16) u [32, 48). | 8 个月前 | |
[MLIR][GPU] Use arith instead of index for subgroup_id (#137843) Trying to simplify situation by using arith dialect instead of index in the rewriting of gpu.subgroup_id. | 1 年前 | |
[MLIR][GPU] Fix gpu.printf (#121940) | 1 年前 | |
[mlir][SCF][GPU] Add DeviceMaskingAttrInterface (#146943) This revision adds DeviceMaskingAttrInterface and extends DeviceMappingArrayAttr to accept a union of DeviceMappingAttrInterface and DeviceMaskingAttrInterface. Support is added to GPUTransformOps to take advantage of this information and lower to block/warpgroup/warp/thread specialization when mapped to linear ids. The revision also connects to scf::ForallOp and uses the new attribute to implement warp specialization. The implementation is in the form of a GPUMappingMaskAttr, which can be additionally passed to the scf.forall.mapping attribute to specify a mask on compute resources that should be active. In the first implementation the masking is a bitfield that specifies for each processing unit whether it is active or not. In the future, we may want to implement this as a symbol to refer to dynamically defined values. Extending op semantics with an operand is deemed too intrusive at this time. --------- Co-authored-by: Oleksandr "Alex" Zinenko <git@ozinenko.com> | 1 年前 | |
[mlir][SCF][GPU] Add DeviceMaskingAttrInterface (#146943) This revision adds DeviceMaskingAttrInterface and extends DeviceMappingArrayAttr to accept a union of DeviceMappingAttrInterface and DeviceMaskingAttrInterface. Support is added to GPUTransformOps to take advantage of this information and lower to block/warpgroup/warp/thread specialization when mapped to linear ids. The revision also connects to scf::ForallOp and uses the new attribute to implement warp specialization. The implementation is in the form of a GPUMappingMaskAttr, which can be additionally passed to the scf.forall.mapping attribute to specify a mask on compute resources that should be active. In the first implementation the masking is a bitfield that specifies for each processing unit whether it is active or not. In the future, we may want to implement this as a symbol to refer to dynamically defined values. Extending op semantics with an operand is deemed too intrusive at this time. --------- Co-authored-by: Oleksandr "Alex" Zinenko <git@ozinenko.com> | 1 年前 | |
[mlir][GPU] Implement ValueBoundsOpInterface for GPU ID operations (#122190) The GPU ID operations already implement InferIntRangeInterface, which gives constant lower and upper bounds on those IDs when appropriate metadata is prentent on the operations or in the surrounding context. This commit uses that existing code to implement the ValueBoundsOpInterface, which is used when analyzing affine operations (unlike the integer range interface, which is used for arithmetic optimization). It also implements the interface for gpu.launch, where we can use it to express the constraint that block/grid sizes are equal to their value from outside the launch op and that the corresponding IDs are bounded above by that size. As a consequence, the test pass for this inference is updated to work on a FunctionOpInterface and not a func.func, creating minor churn in other tests. | 1 年前 |
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