| 文件 | 最后提交记录 | 最后更新时间 |
|---|---|---|
[MLIR][XeGPU] Allow create mem desc from 2d memref (#167767) This PR relax the create_mem_desc's restriction on source memref, allowing it to be a 2d memref. | 8 个月前 | |
[mlir][xegpu] Add definition of SliceAttr (#150146) --------- Co-authored-by: Charitha Saumya <136391709+charithaintc@users.noreply.github.com> | 11 个月前 | |
[MLIR][XeGPU] Introduce xegpu::uArch usage in target-sensitive passes (#163801) | 8 个月前 | |
[MLIR][XeGPU] Allow create mem desc from 2d memref (#167767) This PR relax the create_mem_desc's restriction on source memref, allowing it to be a 2d memref. | 8 个月前 | |
[mlir][xegpu] Add OptimizeBlockLoads pass. (#165483) This pass rewrites certain xegpu CreateNd and LoadNd operations that feeds into vector.transpose to more optimal form to improve performance. Specifically, low precision (bitwidth < 32) LoadNd ops that feeds into transpose ops are rewritten to i32 loads with a valid transpose layout such that later passes can use the load with transpose HW feature to accelerate such load ops. **Update:** Pass is renamed to OptimizeBlockLoads because later we plan to add the array length optimization into this pass as well. This will break down a larger load (like 32x32xf16) into more DPAS-favorable array length loads (32x16xf16 with array length = 2). Both these optmizations require rewriting CreateNd and LoadNd and it makes sense to have a common pass for both. | 8 个月前 | |
[MLIR][XeGPU] Disable block count usage in layout propagation (#168504) | 8 个月前 | |
[MLIR][XeGPU] Decouple inst_data and lane_layout in propagation (#166941) | 8 个月前 | |
[mlir][xegpu] Add more tests in XeGPU subgroup distribution. (#162543) This PR adds some tests for covering some useful corner cases. 1. more tests for vector.shape_cast distribution. 2. testing for MoveFuncBodyToWarpOp pattern that was not possible before. | 9 个月前 | |
[MLIR][XeGPU] Support order attribute and add pattern for vector.transpose in WgToSg Pass (#165307) This PR does the following: 1. Handle order attribute during the delinearization from linear subgroup Id to multi-dim id. 2. Adds a transformation pattern for vector.transpose in wg to sg pass. 3. Updates CHECKS in the wg to sg tests | 8 个月前 | |
[MLIR][XeGPU][TransformOps] Add insert_prefetch op (#167356) Adds transform.xegpu.insert_prefetch transform op that inserts xegpu.prefetch_nd ops for the given Value in an scf.for loop. | 8 个月前 | |
[MLIR][XeGPU][TransformOps] Add slice_dims argument to set_op_layout_attr and set_desc_layout (#168929) set_op_layout_attr and set_desc_layout transform ops wrap xegpu.layout in an xegpu.slice attribute if slice_dims argument is set. | 8 个月前 | |
[MLIR][XeGPU] Support order attribute and add pattern for vector.transpose in WgToSg Pass (#165307) This PR does the following: 1. Handle order attribute during the delinearization from linear subgroup Id to multi-dim id. 2. Adds a transformation pattern for vector.transpose in wg to sg pass. 3. Updates CHECKS in the wg to sg tests | 8 个月前 | |
[MLIR][XeGPU] Remove leading unit dims from vector ops before unrolling (#165030) This PR uses the upstream populateCastAwayVectorLeadingOneDimPatterns to remove leading unit dims from vector ops and then do the unrolling/blocking | 9 个月前 | |
[mlir][xegpu] XeGPU alias ops folder pass (#88886) Adds a pass that folds aliasing ops into XeGPU ops. | 2 年前 | |
[mlir][XeGPU][XeGPUUnroll] Support new syntax with offsets moved to load_nd/store_nd/prefetch_nd (#160323) Adds support for new syntax in XeGPUUnroll for: 1. create_nd_desc without offsets 2. load_nd with offsets 3. store_nd with offsets 4. prefetch_nd with offsets create_nd_desc with offsets + load_nd with offsets won't be lowered correctly. In this case the IR would still have two unrealized conversions that will fail later in the pipeline. The offsets computation for the unrolled tile is now moved from descriptors to load/store/prefetch operations. The resulted IR now has one single descriptor that is being iterated in load/store/prefetch ops. <details><summary>old/new behavior examples</summary> mlir // before unroll pass: gpu.func @load_nd(%src: memref<256x318xf32>) -> vector<24x32xf32> { %tdesc = xegpu.create_nd_tdesc %src : memref<256x318xf32> -> !xegpu.tensor_desc<24x32xf32, #xegpu.layout<inst_data = [8, 16]>> %ld = xegpu.load_nd %tdesc[8, 16]: !xegpu.tensor_desc<24x32xf32, #xegpu.layout<inst_data = [8, 16]>> -> vector<24x32xf32> gpu.return %ld : vector<24x32xf32> } // after unroll pass (offsets in create_nd_desc): gpu.func @create_nd_tdesc2(%arg0: memref<256x318xf32>) -> vector<24x32xf32> { %cst = arith.constant dense<0.000000e+00> : vector<24x32xf32> %c24 = arith.constant 24 : index %c32 = arith.constant 32 : index %c8 = arith.constant 8 : index %c16 = arith.constant 16 : index // create 6 descriptors for each tile %0 = xegpu.create_nd_tdesc %arg0[%c8, %c16] : memref<256x318xf32> -> !xegpu.tensor_desc<8x16xf32> %1 = xegpu.create_nd_tdesc %arg0[%c8, %c32] : memref<256x318xf32> -> !xegpu.tensor_desc<8x16xf32> %2 = xegpu.create_nd_tdesc %arg0[%c16, %c16] : memref<256x318xf32> -> !xegpu.tensor_desc<8x16xf32> %3 = xegpu.create_nd_tdesc %arg0[%c16, %c32] : memref<256x318xf32> -> !xegpu.tensor_desc<8x16xf32> %4 = xegpu.create_nd_tdesc %arg0[%c24, %c16] : memref<256x318xf32> -> !xegpu.tensor_desc<8x16xf32> %5 = xegpu.create_nd_tdesc %arg0[%c24, %c32] : memref<256x318xf32> -> !xegpu.tensor_desc<8x16xf32> %6 = xegpu.load_nd %0 : !xegpu.tensor_desc<8x16xf32> -> vector<8x16xf32> %7 = xegpu.load_nd %1 : !xegpu.tensor_desc<8x16xf32> -> vector<8x16xf32> %8 = xegpu.load_nd %2 : !xegpu.tensor_desc<8x16xf32> -> vector<8x16xf32> %9 = xegpu.load_nd %3 : !xegpu.tensor_desc<8x16xf32> -> vector<8x16xf32> %10 = xegpu.load_nd %4 : !xegpu.tensor_desc<8x16xf32> -> vector<8x16xf32> %11 = xegpu.load_nd %5 : !xegpu.tensor_desc<8x16xf32> -> vector<8x16xf32> ... } // after unroll pass (offsets in load_nd): gpu.func @load_nd(%arg0: memref<256x318xf32>) -> vector<24x32xf32> { %cst = arith.constant dense<0.000000e+00> : vector<24x32xf32> %c24 = arith.constant 24 : index %c32 = arith.constant 32 : index %c16 = arith.constant 16 : index %c8 = arith.constant 8 : index // create only one descriptor with proper tile shape %0 = xegpu.create_nd_tdesc %arg0 : memref<256x318xf32> -> !xegpu.tensor_desc<8x16xf32> // compute tile offsets at the operation (using only one descriptor) %1 = xegpu.load_nd %0[%c8, %c16] : !xegpu.tensor_desc<8x16xf32> -> vector<8x16xf32> %2 = xegpu.load_nd %0[%c8, %c32] : !xegpu.tensor_desc<8x16xf32> -> vector<8x16xf32> %3 = xegpu.load_nd %0[%c16, %c16] : !xegpu.tensor_desc<8x16xf32> -> vector<8x16xf32> %4 = xegpu.load_nd %0[%c16, %c32] : !xegpu.tensor_desc<8x16xf32> -> vector<8x16xf32> %5 = xegpu.load_nd %0[%c24, %c16] : !xegpu.tensor_desc<8x16xf32> -> vector<8x16xf32> %6 = xegpu.load_nd %0[%c24, %c32] : !xegpu.tensor_desc<8x16xf32> -> vector<8x16xf32> ... } </details> --------- Signed-off-by: dchigarev <dmitry.chigarev@intel.com> | 10 个月前 | |
[MLIR][XeGPU] Add unroll pattern for load_gather and store_scatter with offsets (#159453) This PR adds unrolling/blocking patterns for load_gather and store_scatter ops with offsets. | 10 个月前 | |
[mlir][XeGPU][Transform] Add vectorlinearize transform pass. (#158084) Use upstream patterns to create a vectorlinearize pass needed for lowering to XeVM. Linearizes n-D vectors to 1-D vectors. This is needed because, vector-to-llvm does not linearize all the vectors. | 10 个月前 | |
[MLIR][XeGPU] Support order attribute and add pattern for vector.transpose in WgToSg Pass (#165307) This PR does the following: 1. Handle order attribute during the delinearization from linear subgroup Id to multi-dim id. 2. Adds a transformation pattern for vector.transpose in wg to sg pass. 3. Updates CHECKS in the wg to sg tests | 8 个月前 | |
[MLIR][XeGPU] Support order attribute and add pattern for vector.transpose in WgToSg Pass (#165307) This PR does the following: 1. Handle order attribute during the delinearization from linear subgroup Id to multi-dim id. 2. Adds a transformation pattern for vector.transpose in wg to sg pass. 3. Updates CHECKS in the wg to sg tests | 8 个月前 | |
[MLIR] [XeGPU] Add distribution pattern for vector.constant_mask from Wg To Sg (#168118) | 8 个月前 | |
[MLIR] [XeGPU] Add distribution pattern for vector.constant_mask from Wg To Sg (#168118) | 8 个月前 | |
[MLIR][XeGPU] Support order attribute and add pattern for vector.transpose in WgToSg Pass (#165307) This PR does the following: 1. Handle order attribute during the delinearization from linear subgroup Id to multi-dim id. 2. Adds a transformation pattern for vector.transpose in wg to sg pass. 3. Updates CHECKS in the wg to sg tests | 8 个月前 |
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