[feature] 统一寄存器打印顺序-MindStudio-Debugger-AtomGit

Mlldb/include/lldb/Utility/MessageDefines.h+7-1

	@@ -58,7 +58,8 @@ enum class MemType : uint32_t {
58	enum class InterruptPosType : uint8_t {	58	enum class InterruptPosType : uint8_t {
59	SU_INTERRUPT = 0,	59	SU_INTERRUPT = 0,
60	VEC_INTERRUPT_SIMD = 1,	60	VEC_INTERRUPT_SIMD = 1,
61	VEC_INTERRUPT_SIMT = 2	61	VEC_INTERRUPT_SIMT = 2,
		62	UNKNOWN_INTERRUPT_TYPE = 200
62	};	63	};
63		64
64	struct CoreInfo {	65	struct CoreInfo {
	@@ -227,6 +228,11 @@ constexpr uint8_t VF_MASK = SIMD_VF_MASK \| SIMT_VF_MASK;
227		228
228	inline bool IsRegisterSupport(CoreType core_type, InterruptPosType pos_type,	229	inline bool IsRegisterSupport(CoreType core_type, InterruptPosType pos_type,
229	uint8_t mask) {	230	uint8_t mask) {
		231	// use by coredump when we don't detect error register
		232	// we maybe just show all registers
		233	if (pos_type == InterruptPosType::UNKNOWN_INTERRUPT_TYPE) {
		234	return true;
		235	}
230	// if mask not belong to simd/simt, only consider core_type	236	// if mask not belong to simd/simt, only consider core_type
231	if ((mask & AIC_MASK) \|\| (mask & AIV_MASK)) {	237	if ((mask & AIC_MASK) \|\| (mask & AIV_MASK)) {
232	return mask & (1U << static_cast<int>(core_type));	238	return mask & (1U << static_cast<int>(core_type));

Mlldb/source/Commands/CommandObjectRegister.cpp+11-84

	@@ -128,6 +128,10 @@ public:
128	if (reg_set) {	128	if (reg_set) {
129	strm.Printf("%s:\n", (reg_set->name ? reg_set->name : "unknown"));	129	strm.Printf("%s:\n", (reg_set->name ? reg_set->name : "unknown"));
130	strm.IndentMore();	130	strm.IndentMore();
		131	#ifdef MS_DEBUGGER
		132	DeviceStopInfo stop_info{};
		133	m_exe_ctx.GetProcessPtr()->GetDeviceStopInfoCached(stop_info);
		134	#endif
131	const size_t num_registers = reg_set->num_registers;	135	const size_t num_registers = reg_set->num_registers;
132	for (size_t reg_idx = 0; reg_idx < num_registers; ++reg_idx) {	136	for (size_t reg_idx = 0; reg_idx < num_registers; ++reg_idx) {
133	const uint32_t reg = reg_set->registers[reg_idx];	137	const uint32_t reg = reg_set->registers[reg_idx];
	@@ -135,6 +139,13 @@ public:
135	// Skip the dumping of derived register if primitive_only is true.	139	// Skip the dumping of derived register if primitive_only is true.
136	if (primitive_only && reg_info && reg_info->value_regs)	140	if (primitive_only && reg_info && reg_info->value_regs)
137	continue;	141	continue;
		142	#ifdef MS_DEBUGGER
		143	if (stop_info.core_id != UINT32_MAX &&
		144	!IsRegisterSupport(stop_info.core_type, stop_info.pos_type,
		145	reg_info->scenarios_mask)) {
		146	continue;
		147	}
		148	#endif
138	if (reg_info && DumpRegister(exe_ctx, strm, reg_ctx, reg_info,	149	if (reg_info && DumpRegister(exe_ctx, strm, reg_ctx, reg_info,
139	/print_flags=/false))	150	/print_flags=/false))
140	++available_count;	151	++available_count;
	@@ -150,83 +161,7 @@ public:
150	}	161	}
151	return available_count > 0;	162	return available_count > 0;
152	}	163	}
153	#ifdef MS_DEBUGGER
154	bool DumpRegisterSetWithSort(const ExecutionContext &exe_ctx, Stream &strm,
155	RegisterContext *reg_ctx, size_t set_idx,
156	bool primitive_only = false) {
157	// 按照长度和字母序进行排序输出
158	uint32_t unavailable_count = 0;
159	uint32_t available_count = 0;
160		164
161	if (!reg_ctx)
162	return false; // thread has no registers (i.e. core files are corrupt,
163	// incomplete crash logs...)
164	const RegisterSet *const reg_set = reg_ctx->GetRegisterSet(set_idx);
165	if (!reg_set) {
166	return false;
167	}
168
169	strm.Printf("%s:\n", (reg_set->name ? reg_set->name : "unknown"));
170	strm.IndentMore();
171
172	std::vector<uint32_t> reg_indices;
173	const size_t num_registers = reg_set->num_registers;
174
175	DeviceStopInfo stop_info{};
176	m_exe_ctx.GetProcessPtr()->GetDeviceStopInfoCached(stop_info);
177	for (size_t reg_idx = 0; reg_idx < num_registers; ++reg_idx) {
178	const uint32_t reg = reg_set->registers[reg_idx];
179	const RegisterInfo *reg_info = reg_ctx->GetRegisterInfoAtIndex(reg);
180	if (!reg_info) {
181	continue;
182	}
183	if (primitive_only && reg_info->value_regs) {
184	continue;
185	}
186
187	if (stop_info.core_id != UINT32_MAX &&
188	!IsRegisterSupport(stop_info.core_type, stop_info.pos_type,
189	reg_info->scenarios_mask)) {
190	continue;
191	}
192	reg_indices.push_back(reg);
193	}
194
195	// 按照名称和长度对寄存器索引排序
196	std::sort(reg_indices.begin(), reg_indices.end(),
197	[reg_ctx](uint32_t a, uint32_t b) {
198	const RegisterInfo *info_a = reg_ctx->GetRegisterInfoAtIndex(a);
199	const RegisterInfo *info_b = reg_ctx->GetRegisterInfoAtIndex(b);
200	const char *name_a = info_a->name? info_a->name: "";
201	const char *name_b = info_b->name? info_b->name: "";
202	size_t len_a = strlen(name_a);
203	size_t len_b = strlen(name_b);
204
205	if (len_a == len_b){
206	return strcmp(name_a, name_b) < 0;
207	}
208	return len_a < len_b;
209	});
210
211	for (uint32_t reg : reg_indices) {
212	const RegisterInfo *reg_info = reg_ctx->GetRegisterInfoAtIndex(reg);
213	if (reg_info && DumpRegister(exe_ctx, strm, reg_ctx, reg_info,
214	/print_flags=/false))
215	++available_count;
216	else
217	++unavailable_count;
218	}
219
220	strm.IndentLess();
221	if (unavailable_count) {
222	strm.Indent();
223	strm.Printf("%u registers were unavailable.\n", unavailable_count);
224	}
225	strm.EOL();
226
227	return available_count > 0;
228	}
229	#endif
230	protected:	165	protected:
231	void DoExecute(Args &command, CommandReturnObject &result) override {	166	void DoExecute(Args &command, CommandReturnObject &result) override {
232	Stream &strm = result.GetOutputStream();	167	Stream &strm = result.GetOutputStream();
	@@ -269,14 +204,6 @@ protected:
269	num_register_sets = reg_ctx->GetRegisterSetCount();	204	num_register_sets = reg_ctx->GetRegisterSetCount();
270		205
271	for (set_idx = 0; set_idx < num_register_sets; ++set_idx) {	206	for (set_idx = 0; set_idx < num_register_sets; ++set_idx) {
272	#ifdef MS_DEBUGGER
273	if (process->IsStopInDevice()) {
274	DumpRegisterSetWithSort(
275	m_exe_ctx, strm, reg_ctx, set_idx,
276	!m_command_options.dump_all_sets.GetCurrentValue());
277	continue;
278	}
279	#endif
280	// When dump_all_sets option is set, dump primitive as well as	207	// When dump_all_sets option is set, dump primitive as well as
281	// derived registers.	208	// derived registers.
282	DumpRegisterSet(m_exe_ctx, strm, reg_ctx, set_idx,	209	DumpRegisterSet(m_exe_ctx, strm, reg_ctx, set_idx,

Mlldb/source/Commands/CommandObjectThread.cpp+1-4

Mlldb/source/Plugins/Process/Utility/RegisterInfoPOSIX_ascend310P.cpp+5-2

	@@ -9,6 +9,7 @@ using namespace lldb;
9		9
10	namespace {	10	namespace {
11	enum LLDB_ASCEND_RENUM {	11	enum LLDB_ASCEND_RENUM {
		12	lldb_pc_ascend,
12	k_first_gpr_ascend,	13	k_first_gpr_ascend,
13	lldb_x0_ascend = k_first_gpr_ascend,	14	lldb_x0_ascend = k_first_gpr_ascend,
14	lldb_x1_ascend,	15	lldb_x1_ascend,
	@@ -43,7 +44,6 @@ enum LLDB_ASCEND_RENUM {
43	lldb_x30_ascend,	44	lldb_x30_ascend,
44	lldb_x31_ascend,	45	lldb_x31_ascend,
45	k_last_gpr_ascend = lldb_x31_ascend,	46	k_last_gpr_ascend = lldb_x31_ascend,
46	lldb_pc_ascend,
47	lldb_blockid_ascend,	47	lldb_blockid_ascend,
48	lldb_status_ascend,	48	lldb_status_ascend,
49	lldb_ctrl_ascend,	49	lldb_ctrl_ascend,
	@@ -113,7 +113,9 @@ enum LLDB_ASCEND_RENUM {
113	};	113	};
114	} // namespace	114	} // namespace
115		115
		116	// clang-format off
116	static const uint32_t g_regnums_ascend310p[] = {	117	static const uint32_t g_regnums_ascend310p[] = {
		118	lldb_pc_ascend,
117	lldb_x0_ascend, lldb_x1_ascend, lldb_x2_ascend, lldb_x3_ascend,	119	lldb_x0_ascend, lldb_x1_ascend, lldb_x2_ascend, lldb_x3_ascend,
118	lldb_x4_ascend, lldb_x5_ascend, lldb_x6_ascend, lldb_x7_ascend,	120	lldb_x4_ascend, lldb_x5_ascend, lldb_x6_ascend, lldb_x7_ascend,
119	lldb_x8_ascend, lldb_x9_ascend, lldb_x10_ascend, lldb_x11_ascend,	121	lldb_x8_ascend, lldb_x9_ascend, lldb_x10_ascend, lldb_x11_ascend,
	@@ -122,7 +124,7 @@ static const uint32_t g_regnums_ascend310p[] = {
122	lldb_x20_ascend, lldb_x21_ascend, lldb_x22_ascend, lldb_x23_ascend,	124	lldb_x20_ascend, lldb_x21_ascend, lldb_x22_ascend, lldb_x23_ascend,
123	lldb_x24_ascend, lldb_x25_ascend, lldb_x26_ascend, lldb_x27_ascend,	125	lldb_x24_ascend, lldb_x25_ascend, lldb_x26_ascend, lldb_x27_ascend,
124	lldb_x28_ascend, lldb_x29_ascend, lldb_x30_ascend, lldb_x31_ascend,	126	lldb_x28_ascend, lldb_x29_ascend, lldb_x30_ascend, lldb_x31_ascend,
125	lldb_pc_ascend, lldb_blockid_ascend, lldb_status_ascend, lldb_ctrl_ascend,	127	lldb_blockid_ascend, lldb_status_ascend, lldb_ctrl_ascend,
126	lldb_para_base_ascend, lldb_data_main_base_ascend, lldb_data_ub_base_ascend,	128	lldb_para_base_ascend, lldb_data_main_base_ascend, lldb_data_ub_base_ascend,
127	lldb_data_size_ascend, lldb_lpcnt_ascend, lldb_blockdim_ascend,	129	lldb_data_size_ascend, lldb_lpcnt_ascend, lldb_blockdim_ascend,
128	lldb_fmatrix_ascend, lldb_condition_flag_ascend, lldb_deqscale_ascend,	130	lldb_fmatrix_ascend, lldb_condition_flag_ascend, lldb_deqscale_ascend,
	@@ -144,6 +146,7 @@ static const uint32_t g_regnums_ascend310p[] = {
144	lldb_varf2_ascend, lldb_varf3_ascend, lldb_varf4_ascend, lldb_varf5_ascend,	146	lldb_varf2_ascend, lldb_varf3_ascend, lldb_varf4_ascend, lldb_varf5_ascend,
145	lldb_varf6_ascend, lldb_varf7_ascend, lldb_mask_ascend, lldb_cmpmask_ascend,	147	lldb_varf6_ascend, lldb_varf7_ascend, lldb_mask_ascend, lldb_cmpmask_ascend,
146	LLDB_INVALID_REGNUM};	148	LLDB_INVALID_REGNUM};
		149	// clang-format on
147		150
148	static const RegisterSet g_reg_sets_ascend310p[] = {	151	static const RegisterSet g_reg_sets_ascend310p[] = {
149	{"Registers", "register", lldb_cmpmask_ascend - lldb_x0_ascend + 1,	152	{"Registers", "register", lldb_cmpmask_ascend - lldb_x0_ascend + 1,

Mlldb/source/Plugins/Process/Utility/RegisterInfoPOSIX_ascend910B.cpp+41-22

	@@ -15,6 +15,7 @@ constexpr uint8_t UINT32_BIT_NUM = 32U;
15		15
16	namespace {	16	namespace {
17	enum LLDB_ASCEND_RENUM {	17	enum LLDB_ASCEND_RENUM {
		18	lldb_pc_ascend,
18	k_first_gpr_ascend,	19	k_first_gpr_ascend,
19	lldb_x0_ascend = k_first_gpr_ascend,	20	lldb_x0_ascend = k_first_gpr_ascend,
20	lldb_x1_ascend,	21	lldb_x1_ascend,
	@@ -49,7 +50,6 @@ enum LLDB_ASCEND_RENUM {
49	lldb_x30_ascend,	50	lldb_x30_ascend,
50	lldb_x31_ascend,	51	lldb_x31_ascend,
51	k_last_gpr_ascend = lldb_x31_ascend,	52	k_last_gpr_ascend = lldb_x31_ascend,
52	lldb_pc_ascend,
53	lldb_status_ascend,	53	lldb_status_ascend,
54	lldb_ctrl_ascend,	54	lldb_ctrl_ascend,
55	lldb_lpcnt_ascend,	55	lldb_lpcnt_ascend,
	@@ -126,7 +126,10 @@ enum {
126	k_num_register_sets = 3	126	k_num_register_sets = 3
127	};	127	};
128		128
		129	// clang-format off
129	static const uint32_t g_dbg_regnums[] = {	130	static const uint32_t g_dbg_regnums[] = {
		131	// show pc first
		132	lldb_pc_ascend,
130	lldb_x0_ascend, lldb_x1_ascend, lldb_x2_ascend, lldb_x3_ascend,	133	lldb_x0_ascend, lldb_x1_ascend, lldb_x2_ascend, lldb_x3_ascend,
131	lldb_x4_ascend, lldb_x5_ascend, lldb_x6_ascend, lldb_x7_ascend,	134	lldb_x4_ascend, lldb_x5_ascend, lldb_x6_ascend, lldb_x7_ascend,
132	lldb_x8_ascend, lldb_x9_ascend, lldb_x10_ascend, lldb_x11_ascend,	135	lldb_x8_ascend, lldb_x9_ascend, lldb_x10_ascend, lldb_x11_ascend,
	@@ -135,7 +138,7 @@ static const uint32_t g_dbg_regnums[] = {
135	lldb_x20_ascend, lldb_x21_ascend, lldb_x22_ascend, lldb_x23_ascend,	138	lldb_x20_ascend, lldb_x21_ascend, lldb_x22_ascend, lldb_x23_ascend,
136	lldb_x24_ascend, lldb_x25_ascend, lldb_x26_ascend, lldb_x27_ascend,	139	lldb_x24_ascend, lldb_x25_ascend, lldb_x26_ascend, lldb_x27_ascend,
137	lldb_x28_ascend, lldb_x29_ascend, lldb_x30_ascend, lldb_x31_ascend,	140	lldb_x28_ascend, lldb_x29_ascend, lldb_x30_ascend, lldb_x31_ascend,
138	lldb_pc_ascend, lldb_status_ascend, lldb_ctrl_ascend, lldb_lpcnt_ascend,	141	lldb_status_ascend, lldb_ctrl_ascend, lldb_lpcnt_ascend,
139	lldb_condition_flag_ascend, lldb_cond_ascend, lldb_sys_cnt_ascend,	142	lldb_condition_flag_ascend, lldb_cond_ascend, lldb_sys_cnt_ascend,
140	lldb_safety_crc_en_ascend, lldb_call_depth_cnt_ascend,	143	lldb_safety_crc_en_ascend, lldb_call_depth_cnt_ascend,
141	lldb_icache_prl_st_ascend, lldb_st_atomic_cfg_ascend,	144	lldb_icache_prl_st_ascend, lldb_st_atomic_cfg_ascend,
	@@ -151,6 +154,7 @@ static const uint32_t g_dbg_regnums[] = {
151	lldb_varf0_ascend, lldb_varf1_ascend, lldb_varf2_ascend, lldb_varf3_ascend,	154	lldb_varf0_ascend, lldb_varf1_ascend, lldb_varf2_ascend, lldb_varf3_ascend,
152	lldb_varf4_ascend, lldb_varf5_ascend, lldb_varf6_ascend, lldb_varf7_ascend,	155	lldb_varf4_ascend, lldb_varf5_ascend, lldb_varf6_ascend, lldb_varf7_ascend,
153	LLDB_INVALID_REGNUM};	156	LLDB_INVALID_REGNUM};
		157	// clang-format on
154		158
155	static const uint32_t g_aic_err_regnums[] = {	159	static const uint32_t g_aic_err_regnums[] = {
156	lldb_aic_error_0, lldb_aic_error_1, lldb_aic_error_2,	160	lldb_aic_error_0, lldb_aic_error_1, lldb_aic_error_2,
	@@ -171,6 +175,7 @@ static const RegisterSet g_reg_sets_ascend910b[k_num_register_sets_default] = {
171		175
172	// The array should be POD type.	176	// The array should be POD type.
173	static const DeviceRegisterInfo REGISTER_910B_INFO[] = {	177	static const DeviceRegisterInfo REGISTER_910B_INFO[] = {
		178	{ASCEND_GPR(PC, pc, LLDB_REGNUM_GENERIC_PC), 64, MIX_MASK},
174	{ASCEND_GPR(GPR0, x0, LLDB_INVALID_REGNUM), 0, MIX_MASK},	179	{ASCEND_GPR(GPR0, x0, LLDB_INVALID_REGNUM), 0, MIX_MASK},
175	{ASCEND_GPR(GPR1, x1, LLDB_INVALID_REGNUM), 1, MIX_MASK},	180	{ASCEND_GPR(GPR1, x1, LLDB_INVALID_REGNUM), 1, MIX_MASK},
176	{ASCEND_GPR(GPR2, x2, LLDB_INVALID_REGNUM), 2, MIX_MASK},	181	{ASCEND_GPR(GPR2, x2, LLDB_INVALID_REGNUM), 2, MIX_MASK},
	@@ -203,7 +208,6 @@ static const DeviceRegisterInfo REGISTER_910B_INFO[] = {
203	{ASCEND_GPR_ALT(GPR29, x29, fp, LLDB_REGNUM_GENERIC_FP), 29, MIX_MASK},	208	{ASCEND_GPR_ALT(GPR29, x29, fp, LLDB_REGNUM_GENERIC_FP), 29, MIX_MASK},
204	{ASCEND_GPR_ALT(GPR30, x30, sp, LLDB_REGNUM_GENERIC_SP), 30, MIX_MASK},	209	{ASCEND_GPR_ALT(GPR30, x30, sp, LLDB_REGNUM_GENERIC_SP), 30, MIX_MASK},
205	{ASCEND_GPR_ALT(GPR31, x31, lr, LLDB_REGNUM_GENERIC_RA), 31, MIX_MASK},	210	{ASCEND_GPR_ALT(GPR31, x31, lr, LLDB_REGNUM_GENERIC_RA), 31, MIX_MASK},
206	{ASCEND_GPR(PC, pc, LLDB_REGNUM_GENERIC_PC), 64, MIX_MASK},
207	{ASCEND_REG(STATUS, lldb_status_ascend), 66, MIX_MASK},	211	{ASCEND_REG(STATUS, lldb_status_ascend), 66, MIX_MASK},
208	{ASCEND_REG(CTRL, lldb_ctrl_ascend), 67, MIX_MASK},	212	{ASCEND_REG(CTRL, lldb_ctrl_ascend), 67, MIX_MASK},
209	{ASCEND_REG(LPCNT, lldb_lpcnt_ascend), 68, MIX_MASK},	213	{ASCEND_REG(LPCNT, lldb_lpcnt_ascend), 68, MIX_MASK},
	@@ -218,25 +222,40 @@ static const DeviceRegisterInfo REGISTER_910B_INFO[] = {
218	{ASCEND_REG(VEC_EVENT_TABLE, lldb_vec_event_table_ascend), 131, AIV_MASK},	222	{ASCEND_REG(VEC_EVENT_TABLE, lldb_vec_event_table_ascend), 131, AIV_MASK},
219	{ASCEND_REG(CUBE_EVENT_TABLE, lldb_cube_event_table_ascend), 132, AIC_MASK},	223	{ASCEND_REG(CUBE_EVENT_TABLE, lldb_cube_event_table_ascend), 132, AIC_MASK},
220	{ASCEND_REG(FIXP_EVENT_TABLE, lldb_fixp_event_table_ascend), 133, AIC_MASK},	224	{ASCEND_REG(FIXP_EVENT_TABLE, lldb_fixp_event_table_ascend), 133, AIC_MASK},
221	{ASCEND_REG(SCALAR_EVENT_TABLE, lldb_scalar_event_table_ascend), 134, MIX_MASK},	225	{ASCEND_REG(SCALAR_EVENT_TABLE, lldb_scalar_event_table_ascend), 134,
		226	MIX_MASK},
222	{ASCEND_REG(MTE1_EVENT_TABLE, lldb_mte1_event_table_ascend), 135, AIC_MASK},	227	{ASCEND_REG(MTE1_EVENT_TABLE, lldb_mte1_event_table_ascend), 135, AIC_MASK},
223	{ASCEND_REG(MTE2_EVENT_TABLE, lldb_mte2_event_table_ascend), 136, MIX_MASK},	228	{ASCEND_REG(MTE2_EVENT_TABLE, lldb_mte2_event_table_ascend), 136, MIX_MASK},
224	{ASCEND_REG(MTE3_EVENT_TABLE, lldb_mte3_event_table_ascend), 137, AIV_MASK},	229	{ASCEND_REG(MTE3_EVENT_TABLE, lldb_mte3_event_table_ascend), 137, AIV_MASK},
225	{ASCEND_REG(MASK, lldb_mask_ascend), 256ULL << ADDR_OFFSET \| 0, AIV_MASK},	230	{ASCEND_REG(MASK, lldb_mask_ascend), 256ULL << ADDR_OFFSET \| 0, AIV_MASK},
226	{ASCEND_REG(CMPMASK, lldb_cmpmask_ascend), 256ULL << ADDR_OFFSET \| 1, AIV_MASK},	231	{ASCEND_REG(CMPMASK, lldb_cmpmask_ascend), 256ULL << ADDR_OFFSET \| 1,
227	{ASCEND_REG(DEQSCALE, lldb_deqscale_ascend), 256ULL << ADDR_OFFSET \| 2, AIV_MASK},	232	AIV_MASK},
228	{ASCEND_REG(RPN_COR_IR, lldb_rpn_cor_ir_ascend), 256UL << ADDR_OFFSET \| 3, AIV_MASK},	233	{ASCEND_REG(DEQSCALE, lldb_deqscale_ascend), 256ULL << ADDR_OFFSET \| 2,
229	{ASCEND_REG(VMS4_SR, lldb_vms4_sr_ascend), 256ULL << ADDR_OFFSET \| 4, AIV_MASK},	234	AIV_MASK},
230	{ASCEND_REG(DATA_EXP0, lldb_data_exp0_ascend), 256ULL << ADDR_OFFSET \| 5, AIV_MASK},	235	{ASCEND_REG(RPN_COR_IR, lldb_rpn_cor_ir_ascend), 256UL << ADDR_OFFSET \| 3,
231	{ASCEND_REG(DATA_EXP1, lldb_data_exp1_ascend), 256ULL << ADDR_OFFSET \| 6, AIV_MASK},	236	AIV_MASK},
232	{ASCEND_REG(DATA_EXP2, lldb_data_exp2_ascend), 256ULL << ADDR_OFFSET \| 7, AIV_MASK},	237	{ASCEND_REG(VMS4_SR, lldb_vms4_sr_ascend), 256ULL << ADDR_OFFSET \| 4,
233	{ASCEND_REG(DATA_EXP3, lldb_data_exp3_ascend), 256ULL << ADDR_OFFSET \| 8, AIV_MASK},	238	AIV_MASK},
234	{ASCEND_REG(RPN_OFFSET, lldb_rpn_offset_ascend), 256ULL << ADDR_OFFSET \| 9, AIV_MASK},	239	{ASCEND_REG(DATA_EXP0, lldb_data_exp0_ascend), 256ULL << ADDR_OFFSET \| 5,
235	{ASCEND_REG(RSVD_CNT, lldb_rsvd_cnt_ascend), 256ULL << ADDR_OFFSET \| 11, AIV_MASK},	240	AIV_MASK},
236	{ASCEND_REG(PNT_COE, lldb_pnt_coe_ascend), 256ULL << ADDR_OFFSET \| 12, AIV_MASK},	241	{ASCEND_REG(DATA_EXP1, lldb_data_exp1_ascend), 256ULL << ADDR_OFFSET \| 6,
237	{ASCEND_REG(LRELU_ALPHA, lldb_lrelu_alpha_ascend), 256ULL << ADDR_OFFSET \| 13, AIV_MASK},	242	AIV_MASK},
238	{ASCEND_REG(MAXMIN_CNT, lldb_maxmin_cnt_ascend), 256ULL << ADDR_OFFSET \| 14, AIV_MASK},	243	{ASCEND_REG(DATA_EXP2, lldb_data_exp2_ascend), 256ULL << ADDR_OFFSET \| 7,
239	{ASCEND_REG(ACC_VAL, lldb_acc_val_ascend), 256ULL << ADDR_OFFSET \| 15, AIV_MASK},	244	AIV_MASK},
		245	{ASCEND_REG(DATA_EXP3, lldb_data_exp3_ascend), 256ULL << ADDR_OFFSET \| 8,
		246	AIV_MASK},
		247	{ASCEND_REG(RPN_OFFSET, lldb_rpn_offset_ascend), 256ULL << ADDR_OFFSET \| 9,
		248	AIV_MASK},
		249	{ASCEND_REG(RSVD_CNT, lldb_rsvd_cnt_ascend), 256ULL << ADDR_OFFSET \| 11,
		250	AIV_MASK},
		251	{ASCEND_REG(PNT_COE, lldb_pnt_coe_ascend), 256ULL << ADDR_OFFSET \| 12,
		252	AIV_MASK},
		253	{ASCEND_REG(LRELU_ALPHA, lldb_lrelu_alpha_ascend),
		254	256ULL << ADDR_OFFSET \| 13, AIV_MASK},
		255	{ASCEND_REG(MAXMIN_CNT, lldb_maxmin_cnt_ascend), 256ULL << ADDR_OFFSET \| 14,
		256	AIV_MASK},
		257	{ASCEND_REG(ACC_VAL, lldb_acc_val_ascend), 256ULL << ADDR_OFFSET \| 15,
		258	AIV_MASK},
240	{ASCEND_REG(VARF0, lldb_varf0_ascend), 257ULL << ADDR_OFFSET \| 0, AIV_MASK},	259	{ASCEND_REG(VARF0, lldb_varf0_ascend), 257ULL << ADDR_OFFSET \| 0, AIV_MASK},
241	{ASCEND_REG(VARF1, lldb_varf1_ascend), 257ULL << ADDR_OFFSET \| 1, AIV_MASK},	260	{ASCEND_REG(VARF1, lldb_varf1_ascend), 257ULL << ADDR_OFFSET \| 1, AIV_MASK},
242	{ASCEND_REG(VARF2, lldb_varf2_ascend), 257ULL << ADDR_OFFSET \| 2, AIV_MASK},	261	{ASCEND_REG(VARF2, lldb_varf2_ascend), 257ULL << ADDR_OFFSET \| 2, AIV_MASK},
	@@ -245,7 +264,7 @@ static const DeviceRegisterInfo REGISTER_910B_INFO[] = {
245	{ASCEND_REG(VARF5, lldb_varf5_ascend), 257ULL << ADDR_OFFSET \| 5, AIV_MASK},	264	{ASCEND_REG(VARF5, lldb_varf5_ascend), 257ULL << ADDR_OFFSET \| 5, AIV_MASK},
246	{ASCEND_REG(VARF6, lldb_varf6_ascend), 257ULL << ADDR_OFFSET \| 6, AIV_MASK},	265	{ASCEND_REG(VARF6, lldb_varf6_ascend), 257ULL << ADDR_OFFSET \| 6, AIV_MASK},
247	{ASCEND_REG(VARF7, lldb_varf7_ascend), 257ULL << ADDR_OFFSET \| 7, AIV_MASK},	266	{ASCEND_REG(VARF7, lldb_varf7_ascend), 257ULL << ADDR_OFFSET \| 7, AIV_MASK},
248	// for core file only. if you add new both reg, please insert before	267	// for core file only. if you add new both reg, please insert before
249	{ASCEND_REG_4B(AIC_ERROR_0, lldb_aic_error_0), 0x700, MIX_MASK},	268	{ASCEND_REG_4B(AIC_ERROR_0, lldb_aic_error_0), 0x700, MIX_MASK},
250	{ASCEND_REG_4B(AIC_ERROR_1, lldb_aic_error_1), 0x704, MIX_MASK},	269	{ASCEND_REG_4B(AIC_ERROR_1, lldb_aic_error_1), 0x704, MIX_MASK},
251	{ASCEND_REG_4B(AIC_ERROR_2, lldb_aic_error_2), 0x760, MIX_MASK},	270	{ASCEND_REG_4B(AIC_ERROR_2, lldb_aic_error_2), 0x760, MIX_MASK},
	@@ -265,9 +284,9 @@ static const DeviceRegisterInfo REGISTER_910B_INFO[] = {
265	{ASCEND_REG_4B(VEC_ERR_INFO_0, lldb_vec_err_info_0), 0x738, MIX_MASK},	284	{ASCEND_REG_4B(VEC_ERR_INFO_0, lldb_vec_err_info_0), 0x738, MIX_MASK},
266	{ASCEND_REG_4B(VEC_ERR_INFO_1, lldb_vec_err_info_1), 0x73C, MIX_MASK},	285	{ASCEND_REG_4B(VEC_ERR_INFO_1, lldb_vec_err_info_1), 0x73C, MIX_MASK},
267	{ASCEND_REG_4B(FIXP_ERR_INFO_0, lldb_fixp_err_info_0), 0x78C, MIX_MASK},	286	{ASCEND_REG_4B(FIXP_ERR_INFO_0, lldb_fixp_err_info_0), 0x78C, MIX_MASK},
268	{ASCEND_REG_4B(SU_DC_ECC_1BIT_ERR_INFO, lldb_su_dc_ecc_1bit_err_info), 0x7C4, MIX_MASK},	287	{ASCEND_REG_4B(SU_DC_ECC_1BIT_ERR_INFO, lldb_su_dc_ecc_1bit_err_info),
269	{ASCEND_REG_4B(FIXP_ERR_INFO_1, lldb_fixp_err_info_1), 0x7C8, MIX_MASK}	288	0x7C4, MIX_MASK},
270	};	289	{ASCEND_REG_4B(FIXP_ERR_INFO_1, lldb_fixp_err_info_1), 0x7C8, MIX_MASK}};
271		290
272	static_assert(sizeof(REGISTER_910B_INFO) / sizeof(DeviceRegisterInfo) == k_num_registers_ascend,	291	static_assert(sizeof(REGISTER_910B_INFO) / sizeof(DeviceRegisterInfo) == k_num_registers_ascend,
273	"REGISTER_910B_INFO size is invalid");	292	"REGISTER_910B_INFO size is invalid");

Mlldb/source/Plugins/Process/Utility/RegisterInfoPOSIX_ascend950.cpp+27-18

	@@ -13,6 +13,7 @@ using namespace std;
13	namespace {	13	namespace {
14		14
15	enum LLDB_ASCEND_RENUM {	15	enum LLDB_ASCEND_RENUM {
		16	lldb_pc_ascend,
16	k_first_gpr_ascend,	17	k_first_gpr_ascend,
17	lldb_x0_ascend = k_first_gpr_ascend,	18	lldb_x0_ascend = k_first_gpr_ascend,
18	lldb_x1_ascend,	19	lldb_x1_ascend,
	@@ -47,7 +48,6 @@ enum LLDB_ASCEND_RENUM {
47	lldb_x30_ascend,	48	lldb_x30_ascend,
48	lldb_x31_ascend,	49	lldb_x31_ascend,
49	k_last_gpr_ascend = lldb_x31_ascend,	50	k_last_gpr_ascend = lldb_x31_ascend,
50	lldb_pc_ascend,
51	lldb_status_ascend,	51	lldb_status_ascend,
52	lldb_ctrl_su_ascend,	52	lldb_ctrl_su_ascend,
53	lldb_condition_flag_ascend,	53	lldb_condition_flag_ascend,
	@@ -101,6 +101,10 @@ enum LLDB_ASCEND_RENUM {
101	lldb_pcie_rd_ctrl_ascend,	101	lldb_pcie_rd_ctrl_ascend,
102	lldb_pcie_wr_ctrl_ascend,	102	lldb_pcie_wr_ctrl_ascend,
103	k_last_mte_reg_ascend = lldb_pcie_wr_ctrl_ascend,	103	k_last_mte_reg_ascend = lldb_pcie_wr_ctrl_ascend,
		104	lldb_simt_pc_ascend,
		105	lldb_vthreaddim_x_ascend,
		106	lldb_vthreaddim_y_ascend,
		107	lldb_vthreaddim_z_ascend,
104	lldb_v0_ascend,	108	lldb_v0_ascend,
105	lldb_v1_ascend,	109	lldb_v1_ascend,
106	lldb_v2_ascend,	110	lldb_v2_ascend,
	@@ -405,10 +409,6 @@ enum LLDB_ASCEND_RENUM {
405	lldb_ust_ele_ofs_3_ascend,	409	lldb_ust_ele_ofs_3_ascend,
406	lldb_core_id_ascend,	410	lldb_core_id_ascend,
407	lldb_vec_core_id_ascend,	411	lldb_vec_core_id_ascend,
408	lldb_vthreaddim_x_ascend,
409	lldb_vthreaddim_y_ascend,
410	lldb_vthreaddim_z_ascend,
411	lldb_simt_pc_ascend,
412	lldb_su_pc_ascend,	412	lldb_su_pc_ascend,
413	lldb_simt_p0_ascend,	413	lldb_simt_p0_ascend,
414	lldb_simt_p1_ascend,	414	lldb_simt_p1_ascend,
	@@ -625,7 +625,10 @@ enum {
625	k_num_register_sets = 6	625	k_num_register_sets = 6
626	};	626	};
627		627
		628	// clang-format off
628	static const uint32_t g_su_regnums_ascend950[] = {	629	static const uint32_t g_su_regnums_ascend950[] = {
		630	// show pc register first
		631	lldb_pc_ascend,
629	lldb_x0_ascend, lldb_x1_ascend, lldb_x2_ascend, lldb_x3_ascend,	632	lldb_x0_ascend, lldb_x1_ascend, lldb_x2_ascend, lldb_x3_ascend,
630	lldb_x4_ascend, lldb_x5_ascend, lldb_x6_ascend, lldb_x7_ascend,	633	lldb_x4_ascend, lldb_x5_ascend, lldb_x6_ascend, lldb_x7_ascend,
631	lldb_x8_ascend, lldb_x9_ascend, lldb_x10_ascend, lldb_x11_ascend,	634	lldb_x8_ascend, lldb_x9_ascend, lldb_x10_ascend, lldb_x11_ascend,
	@@ -634,7 +637,7 @@ static const uint32_t g_su_regnums_ascend950[] = {
634	lldb_x20_ascend, lldb_x21_ascend, lldb_x22_ascend, lldb_x23_ascend,	637	lldb_x20_ascend, lldb_x21_ascend, lldb_x22_ascend, lldb_x23_ascend,
635	lldb_x24_ascend, lldb_x25_ascend, lldb_x26_ascend, lldb_x27_ascend,	638	lldb_x24_ascend, lldb_x25_ascend, lldb_x26_ascend, lldb_x27_ascend,
636	lldb_x28_ascend, lldb_x29_ascend, lldb_x30_ascend, lldb_x31_ascend,	639	lldb_x28_ascend, lldb_x29_ascend, lldb_x30_ascend, lldb_x31_ascend,
637	lldb_pc_ascend, lldb_status_ascend, lldb_ctrl_su_ascend, lldb_condition_flag_ascend,	640	lldb_status_ascend, lldb_ctrl_su_ascend, lldb_condition_flag_ascend,
638	lldb_cond_ascend, lldb_sys_cnt_ascend, lldb_safety_crc_excpt_ascend, lldb_call_depth_cnt_ascend,	641	lldb_cond_ascend, lldb_sys_cnt_ascend, lldb_safety_crc_excpt_ascend, lldb_call_depth_cnt_ascend,
639	lldb_icache_prl_st_ascend, lldb_ffts_base_addr_ascend, lldb_kick_start_pc_ascend,	642	lldb_icache_prl_st_ascend, lldb_ffts_base_addr_ascend, lldb_kick_start_pc_ascend,
640	lldb_su_warn_status_0_ascend, lldb_su_warn_status_1_ascend,	643	lldb_su_warn_status_0_ascend, lldb_su_warn_status_1_ascend,
	@@ -644,6 +647,7 @@ static const uint32_t g_su_regnums_ascend950[] = {
644	lldb_glb_get_cnt_ascend, lldb_glb_rel_cnt_ascend, lldb_set_cross_core_cnt_ascend,	647	lldb_glb_get_cnt_ascend, lldb_glb_rel_cnt_ascend, lldb_set_cross_core_cnt_ascend,
645	lldb_set_intra_blk_cnt_ascend, LLDB_INVALID_REGNUM	648	lldb_set_intra_blk_cnt_ascend, LLDB_INVALID_REGNUM
646	};	649	};
		650	// clang-format on
647		651
648	static_assert(sizeof(g_su_regnums_ascend950) / sizeof(uint32_t) - 1 == k_num_su_registers,	652	static_assert(sizeof(g_su_regnums_ascend950) / sizeof(uint32_t) - 1 == k_num_su_registers,
649	"Invalid size of g_su_regnums_ascend950");	653	"Invalid size of g_su_regnums_ascend950");
	@@ -663,7 +667,11 @@ static const uint32_t g_mte_regnums_ascend950[] = {
663	static_assert(sizeof(g_mte_regnums_ascend950) / sizeof(uint32_t) - 1 == k_num_mte_registers,	667	static_assert(sizeof(g_mte_regnums_ascend950) / sizeof(uint32_t) - 1 == k_num_mte_registers,
664	"Invalid size of g_mte_regnums_ascend950");	668	"Invalid size of g_mte_regnums_ascend950");
665		669
		670	// clang-format off
666	static const uint32_t g_vecrb_regnums_ascend950[] = {	671	static const uint32_t g_vecrb_regnums_ascend950[] = {
		672	// show pc and import register first
		673	lldb_simt_pc_ascend, lldb_vthreaddim_x_ascend, lldb_vthreaddim_y_ascend,
		674	lldb_vthreaddim_z_ascend,
667	lldb_v0_ascend, lldb_v1_ascend, lldb_v2_ascend, lldb_v3_ascend,	675	lldb_v0_ascend, lldb_v1_ascend, lldb_v2_ascend, lldb_v3_ascend,
668	lldb_v4_ascend, lldb_v5_ascend, lldb_v6_ascend, lldb_v7_ascend,	676	lldb_v4_ascend, lldb_v5_ascend, lldb_v6_ascend, lldb_v7_ascend,
669	lldb_v8_ascend, lldb_v9_ascend, lldb_v10_ascend, lldb_v11_ascend,	677	lldb_v8_ascend, lldb_v9_ascend, lldb_v10_ascend, lldb_v11_ascend,
	@@ -767,8 +775,7 @@ static const uint32_t g_vecrb_regnums_ascend950[] = {
767	lldb_agu_am_const_63_ascend, lldb_ust_ele_ofs_0_ascend,	775	lldb_agu_am_const_63_ascend, lldb_ust_ele_ofs_0_ascend,
768	lldb_ust_ele_ofs_1_ascend, lldb_ust_ele_ofs_2_ascend,	776	lldb_ust_ele_ofs_1_ascend, lldb_ust_ele_ofs_2_ascend,
769	lldb_ust_ele_ofs_3_ascend, lldb_core_id_ascend, lldb_vec_core_id_ascend,	777	lldb_ust_ele_ofs_3_ascend, lldb_core_id_ascend, lldb_vec_core_id_ascend,
770	lldb_vthreaddim_x_ascend, lldb_vthreaddim_y_ascend,	778	lldb_su_pc_ascend,
771	lldb_vthreaddim_z_ascend, lldb_simt_pc_ascend, lldb_su_pc_ascend,
772	lldb_simt_p0_ascend, lldb_simt_p1_ascend, lldb_simt_p2_ascend,	779	lldb_simt_p0_ascend, lldb_simt_p1_ascend, lldb_simt_p2_ascend,
773	lldb_simt_p3_ascend, lldb_simt_p4_ascend, lldb_simt_p5_ascend,	780	lldb_simt_p3_ascend, lldb_simt_p4_ascend, lldb_simt_p5_ascend,
774	lldb_simt_p6_ascend, lldb_simt_p7_ascend, lldb_execmask_ascend,	781	lldb_simt_p6_ascend, lldb_simt_p7_ascend, lldb_execmask_ascend,
	@@ -805,6 +812,8 @@ static const uint32_t g_vecrb_regnums_ascend950[] = {
805	lldb_r120_ascend, lldb_r121_ascend, lldb_r122_ascend, lldb_r123_ascend,	812	lldb_r120_ascend, lldb_r121_ascend, lldb_r122_ascend, lldb_r123_ascend,
806	lldb_r124_ascend, lldb_r125_ascend, lldb_r126_ascend, LLDB_INVALID_REGNUM};	813	lldb_r124_ascend, lldb_r125_ascend, lldb_r126_ascend, LLDB_INVALID_REGNUM};
807		814
		815	// clang-format on
		816
808	static_assert(sizeof(g_vecrb_regnums_ascend950) / sizeof(uint32_t) - 1 == k_num_vecrb_registers,	817	static_assert(sizeof(g_vecrb_regnums_ascend950) / sizeof(uint32_t) - 1 == k_num_vecrb_registers,
809	"Invalid size of g_vecrb_regnums_ascend950");	818	"Invalid size of g_vecrb_regnums_ascend950");
810		819
	@@ -862,6 +871,8 @@ static constexpr uint64_t ID_OFFSET = 52UL;
862		871
863	// The array should be POD type.	872	// The array should be POD type.
864	static const DeviceRegisterInfo REGISTER_950_INFO[] = {	873	static const DeviceRegisterInfo REGISTER_950_INFO[] = {
		874	{ASCEND_GPR(PC, pc, LLDB_REGNUM_GENERIC_PC), SU_ID << ID_OFFSET \| 64,
		875	MIX_MASK},
865	{ASCEND_GPR(GPR0, x0, LLDB_INVALID_REGNUM), SU_ID << ID_OFFSET \| 0,	876	{ASCEND_GPR(GPR0, x0, LLDB_INVALID_REGNUM), SU_ID << ID_OFFSET \| 0,
866	MIX_MASK},	877	MIX_MASK},
867	{ASCEND_GPR(GPR1, x1, LLDB_INVALID_REGNUM), SU_ID << ID_OFFSET \| 1,	878	{ASCEND_GPR(GPR1, x1, LLDB_INVALID_REGNUM), SU_ID << ID_OFFSET \| 1,
	@@ -926,8 +937,6 @@ static const DeviceRegisterInfo REGISTER_950_INFO[] = {
926	SU_ID << ID_OFFSET \| 30, MIX_MASK},	937	SU_ID << ID_OFFSET \| 30, MIX_MASK},
927	{ASCEND_GPR_ALT(GPR31, x31, lr, LLDB_REGNUM_GENERIC_RA),	938	{ASCEND_GPR_ALT(GPR31, x31, lr, LLDB_REGNUM_GENERIC_RA),
928	SU_ID << ID_OFFSET \| 31, MIX_MASK},	939	SU_ID << ID_OFFSET \| 31, MIX_MASK},
929	{ASCEND_GPR(PC, pc, LLDB_REGNUM_GENERIC_PC), SU_ID << ID_OFFSET \| 64,
930	MIX_MASK},
931	{ASCEND_REG(STATUS, lldb_status_ascend), SU_ID << ID_OFFSET \| 65, MIX_MASK},	940	{ASCEND_REG(STATUS, lldb_status_ascend), SU_ID << ID_OFFSET \| 65, MIX_MASK},
932	{ASCEND_REG(CTRL_SU, lldb_ctrl_su_ascend), SU_ID << ID_OFFSET \| 66,	941	{ASCEND_REG(CTRL_SU, lldb_ctrl_su_ascend), SU_ID << ID_OFFSET \| 66,
933	MIX_MASK},	942	MIX_MASK},
	@@ -1030,6 +1039,14 @@ static const DeviceRegisterInfo REGISTER_950_INFO[] = {
1030	{ASCEND_REG(PCIE_WR_CTRL, lldb_pcie_wr_ctrl_ascend),	1039	{ASCEND_REG(PCIE_WR_CTRL, lldb_pcie_wr_ctrl_ascend),
1031	MTE_ID << ID_OFFSET \| 2UL << 48 \| 30, AIV_MASK},	1040	MTE_ID << ID_OFFSET \| 2UL << 48 \| 30, AIV_MASK},
1032	// Vector Registers	1041	// Vector Registers
		1042	{ASCEND_REG(SIMT_PC, lldb_simt_pc_ascend),
		1043	VEC_ID << ID_OFFSET \| 9UL << 48 \| 16384, AIV_MASK},
		1044	{ASCEND_REG_2B(VTHREADDIM_X, lldb_vthreaddim_x_ascend),
		1045	VEC_ID << ID_OFFSET \| 9UL << 48 \| 2, AIV_MASK},
		1046	{ASCEND_REG_2B(VTHREADDIM_Y, lldb_vthreaddim_y_ascend),
		1047	VEC_ID << ID_OFFSET \| 9UL << 48 \| 3, AIV_MASK},
		1048	{ASCEND_REG_2B(VTHREADDIM_Z, lldb_vthreaddim_z_ascend),
		1049	VEC_ID << ID_OFFSET \| 9UL << 48 \| 4, AIV_MASK},
1033	{ASCEND_GPR_NBYTES_VEC_FORMAT_UINT32(V0, v0, 256),	1050	{ASCEND_GPR_NBYTES_VEC_FORMAT_UINT32(V0, v0, 256),
1034	VEC_ID << ID_OFFSET \| 2UL << 48, SIMD_VF_MASK},	1051	VEC_ID << ID_OFFSET \| 2UL << 48, SIMD_VF_MASK},
1035	{ASCEND_GPR_NBYTES_VEC_FORMAT_UINT32(V1, v1, 256),	1052	{ASCEND_GPR_NBYTES_VEC_FORMAT_UINT32(V1, v1, 256),
	@@ -1538,14 +1555,6 @@ static const DeviceRegisterInfo REGISTER_950_INFO[] = {
1538	VEC_ID << ID_OFFSET \| 9UL << 48, AIV_MASK},	1555	VEC_ID << ID_OFFSET \| 9UL << 48, AIV_MASK},
1539	{ASCEND_REG_2B(VEC_CORE_ID, lldb_vec_core_id_ascend),	1556	{ASCEND_REG_2B(VEC_CORE_ID, lldb_vec_core_id_ascend),
1540	VEC_ID << ID_OFFSET \| 9UL << 48 \| 1, AIV_MASK},	1557	VEC_ID << ID_OFFSET \| 9UL << 48 \| 1, AIV_MASK},
1541	{ASCEND_REG_2B(VTHREADDIM_X, lldb_vthreaddim_x_ascend),
1542	VEC_ID << ID_OFFSET \| 9UL << 48 \| 2, AIV_MASK},
1543	{ASCEND_REG_2B(VTHREADDIM_Y, lldb_vthreaddim_y_ascend),
1544	VEC_ID << ID_OFFSET \| 9UL << 48 \| 3, AIV_MASK},
1545	{ASCEND_REG_2B(VTHREADDIM_Z, lldb_vthreaddim_z_ascend),
1546	VEC_ID << ID_OFFSET \| 9UL << 48 \| 4, AIV_MASK},
1547	{ASCEND_REG(SIMT_PC, lldb_simt_pc_ascend),
1548	VEC_ID << ID_OFFSET \| 9UL << 48 \| 16384, AIV_MASK},
1549	{ASCEND_REG(SU_PC, lldb_su_pc_ascend), SU_ID << ID_OFFSET \| 64, MIX_MASK},	1558	{ASCEND_REG(SU_PC, lldb_su_pc_ascend), SU_ID << ID_OFFSET \| 64, MIX_MASK},
1550	// SIMT P_REGISTER	1559	// SIMT P_REGISTER
1551	{ASCEND_REG_4B(SIMT_P0, lldb_simt_p0_ascend),	1560	{ASCEND_REG_4B(SIMT_P0, lldb_simt_p0_ascend),

Mlldb/source/Plugins/Process/elf-core/device-core/ProcessElfCoreDevice.cpp+6-3

	@@ -301,7 +301,8 @@ ProcessElfCoreDevice::GetPosType(RegisterContextSP reg_ctx_sp) {
301	break;	301	break;
302	}	302	}
303	if (!reg_ctx_sp->ReadRegister(err_reg_info, value)) {	303	if (!reg_ctx_sp->ReadRegister(err_reg_info, value)) {
304	break;	304	// maybe no vector error register, so we show all registers
		305	return InterruptPosType::UNKNOWN_INTERRUPT_TYPE;
305	}	306	}
306	if (value.GetAsUInt32() > 0) {	307	if (value.GetAsUInt32() > 0) {
307	is_vf_err = true;	308	is_vf_err = true;
	@@ -338,9 +339,11 @@ void ProcessElfCoreDevice::UpdateStopInfo(bool focus_named_error_core) {
338	string desc = "Unknown Error";	339	string desc = "Unknown Error";
339	std::shared_ptr<void> defer(nullptr, [this, log, &desc](std::nullptr_t &) {	340	std::shared_ptr<void> defer(nullptr, [this, log, &desc](std::nullptr_t &) {
340	DeviceStopInfo stop_info{};	341	DeviceStopInfo stop_info{};
341	stop_info.core_id = m_summary_info.focus_pos_info.core_id -	342	stop_info.core_id = m_summary_info.focus_pos_info.core_id;
342	GetMaxAicID(m_summary_info.chip_type);
343	stop_info.core_type = m_summary_info.focus_pos_info.core_type;	343	stop_info.core_type = m_summary_info.focus_pos_info.core_type;
		344	if (stop_info.core_type == CoreType::AIV) {
		345	stop_info.core_id -= GetMaxAicID(m_summary_info.chip_type);
		346	}
344	stop_info.pos_type = m_summary_info.focus_pos_info.pos_type;	347	stop_info.pos_type = m_summary_info.focus_pos_info.pos_type;
345	if (stop_info.pos_type == InterruptPosType::VEC_INTERRUPT_SIMT) {	348	if (stop_info.pos_type == InterruptPosType::VEC_INTERRUPT_SIMT) {
346	stop_info.thread_pos = m_summary_info.focus_pos_info.thread_pos;	349	stop_info.thread_pos = m_summary_info.focus_pos_info.thread_pos;

	@@ -128,9 +128,6 @@ public:
128	nullptr,	128	nullptr,
129	eCommandRequiresProcess \| eCommandRequiresThread \|	129	eCommandRequiresProcess \| eCommandRequiresThread \|
130	eCommandTryTargetAPILock \| eCommandProcessMustBeLaunched \|	130	eCommandTryTargetAPILock \| eCommandProcessMustBeLaunched \|
131	#ifdef MS_DEBUGGER
132	eCommandProcessMustNotBeTaskKilled \|
133	#endif
134	eCommandProcessMustBePaused) {}	131	eCommandProcessMustBePaused) {}
135		132
136	~CommandObjectThreadBacktrace() override = default;	133	~CommandObjectThreadBacktrace() override = default;
	@@ -556,7 +553,7 @@ protected:
556	else	553	else
557	new_plan_sp = thread->QueueThreadPlanForStepSingleInstruction(	554	new_plan_sp = thread->QueueThreadPlanForStepSingleInstruction(
558	true, abort_other_plans, bool_stop_other_threads, new_plan_status);	555	true, abort_other_plans, bool_stop_other_threads, new_plan_status);
559		556
560	} else if (m_step_type == eStepTypeTrace) {	557	} else if (m_step_type == eStepTypeTrace) {
561	new_plan_sp = thread->QueueThreadPlanForStepSingleInstruction(	558	new_plan_sp = thread->QueueThreadPlanForStepSingleInstruction(
562	false, abort_other_plans, bool_stop_other_threads, new_plan_status);	559	false, abort_other_plans, bool_stop_other_threads, new_plan_status);