TORCH MAIN SYNC : remove use_const_ref_for_mutable

Mop_plugin/config/op_plugin_functions.yaml+6-2

	@@ -192,10 +192,14 @@ official:
192	op_api: v1.11	192	op_api: v1.11
193		193
194	- func: _conv_depthwise2d.out(Tensor self, Tensor weight, int[2] kernel_size, Tensor? bias, int[2] stride, SymInt[2] padding, int[2] dilation, *, Tensor(a!) out) -> Tensor(a!)	194	- func: _conv_depthwise2d.out(Tensor self, Tensor weight, int[2] kernel_size, Tensor? bias, int[2] stride, SymInt[2] padding, int[2] dilation, *, Tensor(a!) out) -> Tensor(a!)
195	- acl_op: [v2.0, newest]	195	+ acl_op: [v2.0, v2.6]
196	- op_api: [v2.1, newest]	196	+ op_api: [v2.1, v2.6]
197	use_const_ref_for_mutable_tensors: true	197	use_const_ref_for_mutable_tensors: true
198		198
		199	+ - func: _conv_depthwise2d.out(Tensor self, Tensor weight, int[2] kernel_size, Tensor? bias, int[2] stride, SymInt[2] padding, int[2] dilation, *, Tensor(a!) out) -> Tensor(a!)
		200	+ acl_op: [v2.7, newest]
		201	+ op_api: [v2.7, newest]
		202	+
199	- func: _conv_depthwise2d.out(Tensor self, Tensor weight, int[2] kernel_size, Tensor? bias, int[2] stride, int[2] padding, int[2] dilation, *, Tensor(a!) out) -> Tensor(a!)	203	- func: _conv_depthwise2d.out(Tensor self, Tensor weight, int[2] kernel_size, Tensor? bias, int[2] stride, int[2] padding, int[2] dilation, *, Tensor(a!) out) -> Tensor(a!)
200	acl_op: v1.11	204	acl_op: v1.11
201	op_api: v1.11	205	op_api: v1.11

Mop_plugin/ops/aclops/ConvDepthWise2dKernelNpu.cpp+39-0

	@@ -19,6 +19,7 @@
19	namespace acl_op {	19	namespace acl_op {
20	using npu_preparation = at_npu::native::OpPreparation;	20	using npu_preparation = at_npu::native::OpPreparation;
21		21
		22	+#if VERSION_BETWEEN(V2R1, V2R6)
22	const at::Tensor &_conv_depthwise2d_out(const at::Tensor &self, const at::Tensor &weight, c10::IntArrayRef kernel_size,	23	const at::Tensor &_conv_depthwise2d_out(const at::Tensor &self, const at::Tensor &weight, c10::IntArrayRef kernel_size,
23	const c10::optional<at::Tensor> &bias_opt, c10::IntArrayRef stride,	24	const c10::optional<at::Tensor> &bias_opt, c10::IntArrayRef stride,
24	c10::IntArrayRef padding, c10::IntArrayRef dilation, const at::Tensor &result)	25	c10::IntArrayRef padding, c10::IntArrayRef dilation, const at::Tensor &result)
	@@ -53,6 +54,44 @@ const at::Tensor &_conv_depthwise2d_out(const at::Tensor &self, const at::Tensor
53	.Run();	54	.Run();
54	return result;	55	return result;
55	}	56	}
		57	+#endif
		58	+
		59	+#if VERSION_BETWEEN(V2R7, VERSION_NEWEST)
		60	+at::Tensor &_conv_depthwise2d_out(const at::Tensor &self, const at::Tensor &weight, c10::IntArrayRef kernel_size,
		61	+ const c10::optional<at::Tensor> &bias_opt, c10::IntArrayRef stride,
		62	+ c10::IntArrayRef padding, c10::IntArrayRef dilation, at::Tensor &result)
		63	+{
		64	+ TORCH_CHECK(weight.dim() >= 4, "weight has to be more than 4D, but got Tensor of dimension ", weight.dim(),
		65	+ OPS_ERROR(ErrCode::PARAM));
		66	+ TORCH_CHECK(stride.size() >= 2, "stride has to contain more than 2 elements, but got ", stride.size(),
		67	+ OPS_ERROR(ErrCode::PARAM));
		68	+ TORCH_CHECK(padding.size() >= 2, "padding has to contain more than 2 elements, but got ", padding.size(),
		69	+ OPS_ERROR(ErrCode::PARAM));
		70	+ TORCH_CHECK(dilation.size() >= 2, "dilation has to contain more than 2 elements, but got ", dilation.size(),
		71	+ OPS_ERROR(ErrCode::PARAM));
		72	+
		73	+ const at::Tensor &bias = c10::value_or_else(bias_opt, [] { return at::Tensor(); });
		74	+ const at::Tensor &weight_modify = weight.permute({1, 0, 2, 3});
		75	+
		76	+ c10::SmallVector<int64_t, N> strides_size = {1, 1, stride[0], stride[1]};
		77	+ c10::SmallVector<int64_t, N> paddings = {padding[0], padding[0], padding[1], padding[1]};
		78	+ c10::SmallVector<int64_t, N> dilations = {1, 1, dilation[0], dilation[1]};
		79	+ at::Tensor temp_out = result;
		80	+
		81	+ at_npu::native::OpCommand cmd;
		82	+ cmd.Name("DepthwiseConv2D").Input(self, "x").Input(weight_modify, "filter");
		83	+ if (bias.defined()) {
		84	+ cmd.Input(bias);
		85	+ }
		86	+ cmd.Output(temp_out, "y")
		87	+ .Attr("strides", strides_size)
		88	+ .Attr("pads", paddings)
		89	+ .Attr("dilations", dilations)
		90	+ .Attr("data_format", (string) "NCHW")
		91	+ .Run();
		92	+ return result;
		93	+}
		94	+#endif
56		95
57	at::Tensor _conv_depthwise2d(const at::Tensor &self, const at::Tensor &weight, c10::IntArrayRef kernel_size,	96	at::Tensor _conv_depthwise2d(const at::Tensor &self, const at::Tensor &weight, c10::IntArrayRef kernel_size,
58	const c10::optional<at::Tensor> &bias_opt, c10::IntArrayRef stride,	97	const c10::optional<at::Tensor> &bias_opt, c10::IntArrayRef stride,

Mop_plugin/ops/opapi/ConvDepthwise2dKernelNpuOpApi.cpp+29-0

	@@ -20,6 +20,7 @@
20	namespace op_api {	20	namespace op_api {
21	using npu_preparation = at_npu::native::OpPreparation;	21	using npu_preparation = at_npu::native::OpPreparation;
22		22
		23	+#if VERSION_BETWEEN(V2R1, V2R6)
23	const at::Tensor& _conv_depthwise2d_out(	24	const at::Tensor& _conv_depthwise2d_out(
24	const at::Tensor& self,	25	const at::Tensor& self,
25	const at::Tensor& weight,	26	const at::Tensor& weight,
	@@ -43,6 +44,34 @@ const at::Tensor& _conv_depthwise2d_out(
43	EXEC_NPU_CMD(aclnnConvDepthwise2d, self, weight, kernel_size, bias, stride, padding, dilation, out, cube_math_type);	44	EXEC_NPU_CMD(aclnnConvDepthwise2d, self, weight, kernel_size, bias, stride, padding, dilation, out, cube_math_type);
44	return out;	45	return out;
45	}	46	}
		47	+#endif
		48	+
		49	+#if VERSION_BETWEEN(V2R7, VERSION_NEWEST)
		50	+at::Tensor& _conv_depthwise2d_out(
		51	+ const at::Tensor& self,
		52	+ const at::Tensor& weight,
		53	+ at::IntArrayRef kernel_size,
		54	+ const c10::optional<at::Tensor>& bias_opt,
		55	+ at::IntArrayRef stride,
		56	+ at::IntArrayRef padding,
		57	+ at::IntArrayRef dilation,
		58	+ at::Tensor& out)
		59	+{
		60	+ DO_COMPATIBILITY(aclnnConvDepthwise2d, acl_op::_conv_depthwise2d_out(self, weight, kernel_size, bias_opt,
		61	+ stride, padding, dilation, out));
		62	+ bool is_jit_enable = !at_npu::native::env::CheckJitDisable();
		63	+ bool is_allow_internel_format = !at_npu::native::env::CheckForbidInternalFormat();
		64	+ ASCEND_LOGI("_conv_depthwise2d_out exec with jit compile: %d, allow internal format: %d",
		65	+ is_jit_enable, is_allow_internel_format);
		66	+ if (is_allow_internel_format \|\| is_jit_enable) {
		67	+ return acl_op::_conv_depthwise2d_out(self, weight, kernel_size, bias_opt, stride, padding, dilation, out);
		68	+ }
		69	+ const at::Tensor& bias = c10::value_or_else(bias_opt, [] {return at::Tensor();});
		70	+ int8_t cube_math_type = npu_preparation::get_cube_math_type(at_npu::native::env::IsAllowConvHF32());
		71	+ EXEC_NPU_CMD(aclnnConvDepthwise2d, self, weight, kernel_size, bias, stride, padding, dilation, out, cube_math_type);
		72	+ return out;
		73	+}
		74	+#endif
46		75
47	at::Tensor _conv_depthwise2d(	76	at::Tensor _conv_depthwise2d(
48	const at::Tensor& self,	77	const at::Tensor& self,