已合并
fix smoothl1loss blending accuracy #2640
simbaliuxx创建于 2025年6月17日
fix smoothl1loss blending accuracy #2640
已合并
simbaliuxx创建于 2025年6月17日
refs/pull/2640/head合入到master
2 个文件变更+5-2
@@ -36,7 +36,8 @@ at::Tensor smooth_l1_loss(const at::Tensor &self, const at::Tensor &target, int6
36{36{
37 DO_COMPATIBILITY(aclnnSmoothL1Loss, acl_op::smooth_l1_loss(self, target, reduction, beta));37 DO_COMPATIBILITY(aclnnSmoothL1Loss, acl_op::smooth_l1_loss(self, target, reduction, beta));
38 auto outputSize = op_infer::smooth_l1_loss_npu_output_size(self, reduction);38 auto outputSize = op_infer::smooth_l1_loss_npu_output_size(self, reduction);
39- at::Tensor result = npu_preparation::apply_tensor_without_format(self, outputSize);39+ at::ScalarType high_type = at::native::result_type(self, target);
40+ at::Tensor result = npu_preparation::apply_tensor_without_format(outputSize, self.options().dtype(high_type));
40 float sigma = static_cast<float>(beta);41 float sigma = static_cast<float>(beta);
41 EXEC_NPU_CMD(aclnnSmoothL1Loss, self, target, reduction, sigma, result);42 EXEC_NPU_CMD(aclnnSmoothL1Loss, self, target, reduction, sigma, result);
42 return result;43 return result;
@@ -15,6 +15,7 @@
15 15 
16#include <bitset>16#include <bitset>
17#include "torch_npu/csrc/core/npu/NPUException.h"17#include "torch_npu/csrc/core/npu/NPUException.h"
18+#include "torch_npu/csrc/core/npu/NpuVariables.h"
18#include "op_plugin/utils/AdvancedIndex.h"19#include "op_plugin/utils/AdvancedIndex.h"
19#include "op_plugin/utils/OpUtils.h"20#include "op_plugin/utils/OpUtils.h"
20#include "op_plugin/utils/KernelNpuOutputSize.h"21#include "op_plugin/utils/KernelNpuOutputSize.h"
@@ -580,8 +581,9 @@ ctc_loss_npu_output_size(const at::Tensor &log_probs, int64_t max_length)
580 }581 }
581 c10::SmallVector<int64_t, SIZE> neg_log_likelihood_size = {batch_size};582 c10::SmallVector<int64_t, SIZE> neg_log_likelihood_size = {batch_size};
582 int64_t alpha_tail_size = 2 * max_length + 1;583 int64_t alpha_tail_size = 2 * max_length + 1;
584+ static bool isRegBaseSoc = c10_npu::GetSocVersion() >= c10_npu::SocVersion::Ascend910_95;
CL
Cchuboning2025年6月20日

定义加个static

likedislike
Llihang902025年6月26日

定义加个static

已修改

likedislike
583 // Apply for a 32 byte aligned space to avoid address shifting in the OP.585 // Apply for a 32 byte aligned space to avoid address shifting in the OP.
584- int64_t alpha_tail_size_align = (alpha_tail_size + 7) / 8 * 8;586+ int64_t alpha_tail_size_align = isRegBaseSoc ? alpha_tail_size : (alpha_tail_size + 7) / 8 * 8;
585 c10::SmallVector<int64_t, SIZE> log_alpha_size = {batch_size, time_size, alpha_tail_size_align};587 c10::SmallVector<int64_t, SIZE> log_alpha_size = {batch_size, time_size, alpha_tail_size_align};
586 588 
587 if (log_probs.dim() == dim_num_two) {589 if (log_probs.dim() == dim_num_two) {