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TTobias Hieta[ELF] Rewrite R_RISCV_ALIGN nops when r.addend%4 != 0

2eba4dd7创建于 2022年9月28日历史提交

文件	最后提交记录	最后更新时间
AArch64.cpp	[ELF][AArch64] Fix potentially corrupted section content for PAC D74537 introduced a bug: if (config->andFeatures & GNU_PROPERTY_AARCH64_FEATURE_1_PAC) != 0 with -z pac-plt unspecified, we incorrectly use AArch64BtiPac, whose writePlt will make out-of-bounds write after the .plt section. This is often benign because the output section after .plt will usually overwrite the content. This is very difficult to test without D131247 (Parallelize writes of different OutputSections). (cherry picked from commit d7cbfcf36ace575ec90434624279dd3ebce78c47)	3 年前
AMDGPU.cpp	[ELF] Move InputFiles global variables (memoryBuffers, objectFiles, etc) into Ctx. NFC	3 年前
ARM.cpp	[ELF][ARM] Fix unneeded thunk for branches to hidden undefined weak Similar to D123750 for AArch64.	4 年前
AVR.cpp	[ELF] Move InputFiles global variables (memoryBuffers, objectFiles, etc) into Ctx. NFC	3 年前
Hexagon.cpp	[ELF] Move InputFiles global variables (memoryBuffers, objectFiles, etc) into Ctx. NFC	3 年前
MSP430.cpp	[ELF] Clean up headers. NFC	4 年前
Mips.cpp	[ELF] Don't rely on Symbols.h's transitive inclusion of InputFiles.h. NFC	4 年前
MipsArchTree.cpp	[ELF] Move InputFiles global variables (memoryBuffers, objectFiles, etc) into Ctx. NFC	3 年前
PPC.cpp	[ELF] Support some absolute/PC-relative relocation types for REL format ctfconvert seems to use REL-format .rel.SUNW_dof for 32-bit architectures. Binary file usr/ports/lang/perl5.32/work/perl-5.32.1/dtrace_mini.o matches [alfredo.junior@dell-a ~/tmp/llvm-bug]$ readelf -r dtrace_mini.o Relocation section (.rel.SUNW_dof): r_offset r_info r_type st_value st_name 00000184 0000281a R_PPC_REL32 00000000 $dtrace1772974259.Perl_dtrace_probe_load Support R_PPC_REL32 to fix ld.lld: error: drti.c:(.SUNW_dof+0x4E4): internal linker error: cannot read addend for relocation R_PPC_REL32. While here, add some common relocation types for AArch64, PPC, and PPC64. We perform minimum tests. Reviewed By: adalava, arichardson Differential Revision: https://reviews.llvm.org/D120535	4 年前
PPC64.cpp	[ELF] Move InputFiles global variables (memoryBuffers, objectFiles, etc) into Ctx. NFC	3 年前
PPCInsns.def	[LLD][PowerPC] Implement GOT to PC-Rel relaxation This patch implements the handling for the R_PPC64_PCREL_OPT relocation as well as the GOT relocation for the associated R_PPC64_GOT_PCREL34 relocation. On Power10 targets with PC-Relative addressing, the linker can relax GOT-relative accesses to PC-Relative under some conditions. Since the sequence consists of a prefixed load, followed by a non-prefixed access (load or store), the linker needs to replace the first instruction (as the replacement instruction will be prefixed). The compiler communicates to the linker that this optimization is safe by placing the two aforementioned relocations on the GOT load (of the address). The linker then does two things: - Convert the load from the got into a PC-Relative add to compute the address relative to the PC - Find the instruction referred to by the second relocation (R_PPC64_PCREL_OPT) and replace the first with the PC-Relative version of it It is important to synchronize the mapping from legacy memory instructions to their PC-Relative form. Hence, this patch adds a file to be included by both the compiler and the linker so they're always in agreement. Differential revision: https://reviews.llvm.org/D84360	5 年前
RISCV.cpp	[ELF] Rewrite R_RISCV_ALIGN nops when r.addend%4 != 0 For RVC, GNU assembler and LLVM integrated assembler add c.nop followed by a sequence of 4-byte nops. Even if remove % 4 == 0, we have to split one 4-byte nop and therefore need to write the code sequence, otherwise we create an incorrect c.unimp. (cherry picked from commit 78084d9e77b9a2017e2215491b71b37c2671c292)	3 年前
SPARCV9.cpp	[ELF] Clean up headers. NFC	4 年前
X86.cpp	[ELF] Clean up headers. NFC	4 年前
X86_64.cpp	fix comment typos to cycle bots	4 年前