| 文件 | 最后提交记录 | 最后更新时间 |
|---|---|---|
[llvm] Use value instead of getValue (NFC) | 4 年前 | |
Move TargetRegistry.(h|cpp) from Support to MC This moves the registry higher in the LLVM library dependency stack. Every client of the target registry needs to link against MC anyway to actually use the target, so we might as well move this out of Support. This allows us to ensure that Support doesn't have includes from MC/*. Differential Revision: https://reviews.llvm.org/D111454 | 4 年前 | |
Cleanup includes: LLVMTarget Most notably, Pass.h is no longer included by TargetMachine.h before: 1063570306 after: 1063332844 Differential Revision: https://reviews.llvm.org/D121168 | 4 年前 | |
[NFC][regalloc] Separate iteration from AllocationOrder This separates the two concerns - encapsulation of traversal order; and iteration. Differential Revision: https://reviews.llvm.org/D88256 | 5 年前 | |
[MC] De-capitalize SwitchSection. NFC Add SwitchSection to return switchSection. The API will be removed soon. | 4 年前 | |
[reland][Debuginfo][DWARF][NFC] Refactor DwarfStringPoolEntryRef. This review is extracted from D96035. This patch adds possibility to keep not only DwarfStringPoolEntry, but also pointer to it. The DwarfStringPoolEntryRef keeps reference to the string map entry. String map keeps string data and corresponding DwarfStringPoolEntry info. Not all string map entries may be included into the result, and then not all string entries should have DwarfStringPoolEntry info. Currently StringMap keeps DwarfStringPoolEntry for all entries. It leads to extra memory usage. This patch allows to keep DwarfStringPoolEntry info only for entries which really need it. [reland] : make msan happy. Reviewed By: JDevlieghere Differential Revision: https://reviews.llvm.org/D126883 | 4 年前 | |
[DWARF] Add linkagename to hash Originally encountered with RUST, but also there are cases with distributed LTO where debug info dwo units contain structurally the same debug information, with difference in DW_AT_linkage_name. This causes collision on DWO ID. Differential Revision: https://reviews.llvm.org/D129317 | 4 年前 | |
[CodeGen][Debuginfo][NFC] Refactor DIE values SizeOf method to not depend on AsmPrinter. SizeOf() method of DIE values(unsigned SizeOf(const AsmPrinter *AP, dwarf::Form Form) const) depends on AsmPrinter. AsmPrinter is too specific class here. This patch removes dependency on AsmPrinter and use dwarf::FormParams structure instead. It allows calculate DIE values size without using AsmPrinter. That refactoring is useful for D96035([dsymutil][DWARFlinker] implement separate multi-thread processing for compile units.) Differential Revision: https://reviews.llvm.org/D116997 | 4 年前 | |
[reland][Debuginfo][DWARF][NFC] Refactor DwarfStringPoolEntryRef. This review is extracted from D96035. This patch adds possibility to keep not only DwarfStringPoolEntry, but also pointer to it. The DwarfStringPoolEntryRef keeps reference to the string map entry. String map keeps string data and corresponding DwarfStringPoolEntry info. Not all string map entries may be included into the result, and then not all string entries should have DwarfStringPoolEntry info. Currently StringMap keeps DwarfStringPoolEntry for all entries. It leads to extra memory usage. This patch allows to keep DwarfStringPoolEntry info only for entries which really need it. [reland] : make msan happy. Reviewed By: JDevlieghere Differential Revision: https://reviews.llvm.org/D126883 | 4 年前 | |
Reapply D124184, [DebugInfo][InstrRef] Add a size operand to DBG_PHI This was reverted twice, in 987cd7c3ed75b and 13815e8cbf8d4. The latter stemed from not accounting for rare register classes in a pre-allocated array, and the former from an array not being completely initialized, leading to asan complaining. | 4 年前 | |
[Codegen][tablgen][NFC] Allow meta instruction to be target dependent An instruction is a meta-instruction if it doesn't produce any output in the form of executable instructions. So in the concept, a meta-instruction does not have to be target independent. Before this patch, isMetaInstruction is implemented by checking the opcode of the instruction, add we have no way to add target dependent opcode to the list, which does not make sense. After this patch, a bit isMeta is added for class Instruction in tablegen, which is used to indicate whether it's a meta instruction. Reviewed By: pengfei Differential Revision: https://reviews.llvm.org/D121600 | 4 年前 | |
Init project. | 1 年前 | |
[X86][MC][Target] Initial backend support a tune CPU to support -mtune This patch implements initial backend support for a -mtune CPU controlled by a "tune-cpu" function attribute. If the attribute is not present X86 will use the resolved CPU from target-cpu attribute or command line. This patch adds MC layer support a tune CPU. Each CPU now has two sets of features stored in their GenSubtargetInfo.inc tables . These features lists are passed separately to the Processor and ProcessorModel classes in tablegen. The tune list defaults to an empty list to avoid changes to non-X86. This annoyingly increases the size of static tables on all target as we now store 24 more bytes per CPU. I haven't quantified the overall impact, but I can if we're concerned. One new test is added to X86 to show a few tuning features with mismatched tune-cpu and target-cpu/target-feature attributes to demonstrate independent control. Another new test is added to demonstrate that the scheduler model follows the tune CPU. I have not added a -mtune to llc/opt or MC layer command line yet. With no attributes we'll just use the -mcpu for both. MC layer tools will always follow the normal CPU for tuning. Differential Revision: https://reviews.llvm.org/D85165 | 5 年前 | |
Update the file headers across all of the LLVM projects in the monorepo to reflect the new license. We understand that people may be surprised that we're moving the header entirely to discuss the new license. We checked this carefully with the Foundation's lawyer and we believe this is the correct approach. Essentially, all code in the project is now made available by the LLVM project under our new license, so you will see that the license headers include that license only. Some of our contributors have contributed code under our old license, and accordingly, we have retained a copy of our old license notice in the top-level files in each project and repository. llvm-svn: 351636 | 7 年前 | |
Move TargetRegistry.(h|cpp) from Support to MC This moves the registry higher in the LLVM library dependency stack. Every client of the target registry needs to link against MC anyway to actually use the target, so we might as well move this out of Support. This allows us to ensure that Support doesn't have includes from MC/*. Differential Revision: https://reviews.llvm.org/D111454 | 4 年前 | |
Cleanup includes: DebugInfo & CodeGen Discourse thread: https://discourse.llvm.org/t/include-what-you-use-include-cleanup Differential Revision: https://reviews.llvm.org/D121332 | 4 年前 | |
Cleanup codegen includes This is a (fixed) recommit of https://reviews.llvm.org/D121169 after: 1061034926 before: 1063332844 Discourse thread: https://discourse.llvm.org/t/include-what-you-use-include-cleanup Differential Revision: https://reviews.llvm.org/D121681 | 4 年前 | |
Fix MSVC "not all control paths return a value" warning. NFC. | 4 年前 | |
[llvm] Add enum iteration to Sequence This patch allows iterating typed enum via the ADT/Sequence utility. It also changes the original design to better separate concerns: - StrongInt only deals with safe intmax_t operations, - SafeIntIterator presents the iterator and reverse iterator interface but only deals with safe StrongInt internally. - iota_range only deals with SafeIntIterator internally. This design ensures that operations are always valid. In particular, "Out of bounds" assertions fire when: - the value_type is not representable as an intmax_t - iterator operations make internal computation underflow/overflow - the internal representation cannot be converted back to value_type Differential Revision: https://reviews.llvm.org/D106279 | 5 年前 | |
Move TargetRegistry.(h|cpp) from Support to MC This moves the registry higher in the LLVM library dependency stack. Every client of the target registry needs to link against MC anyway to actually use the target, so we might as well move this out of Support. This allows us to ensure that Support doesn't have includes from MC/*. Differential Revision: https://reviews.llvm.org/D111454 | 4 年前 | |
Move TargetRegistry.(h|cpp) from Support to MC This moves the registry higher in the LLVM library dependency stack. Every client of the target registry needs to link against MC anyway to actually use the target, so we might as well move this out of Support. This allows us to ensure that Support doesn't have includes from MC/*. Differential Revision: https://reviews.llvm.org/D111454 | 4 年前 | |
Move TargetRegistry.(h|cpp) from Support to MC This moves the registry higher in the LLVM library dependency stack. Every client of the target registry needs to link against MC anyway to actually use the target, so we might as well move this out of Support. This allows us to ensure that Support doesn't have includes from MC/*. Differential Revision: https://reviews.llvm.org/D111454 | 4 年前 | |
[MC] Lower case the first letter of EmitCOFF* EmitWin* EmitCV*. NFC | 4 年前 | |
Switch from llvm::is_trivially_copyable to std::is_trivially_copyable GCC<5 did not support std::is_trivially_copyable. Now LLVM builds require 5.1 we can migrate to std::is_trivially_copyable. The Optional.h change made MSVC choke (https://buildkite.com/llvm-project/premerge-checks/builds/18587#cd1bb616-ffdc-4581-9795-b42c284196de) so I leave it out for now. Differential Revision: https://reviews.llvm.org/D92514 | 5 年前 |
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