| chore(perf): update gcc 15 checkpoint (#6181) Existing gcc15 checkpoint contains unexpected vector instructions despite V extension is not enabled in the compiler. New checkpoint fixes this problem. --------- Co-authored-by: Copilot Autofix powered by AI <175728472+Copilot@users.noreply.github.com> | 19 小时前 |
| bump difftest & mkdir for wave/perf for local-ci script's run-mode (#1927) * bump difftest, assign empty value to OBJCACHE * local-ci: mkdir for wave/perf at run-mode | 3 年前 |
| docs(xspdb): update some xspdb docs | 3 个月前 |
| docs(readme): update kunminghu architecture graph (#3910) | 1 年前 |
| NewCSR: fix unprivileged CSRs and permission check * Add commit vstart * Fix commit connection * Fix permission check * Fix mstatus.VS/FS initial with off * Add fp/vec.off bundle to decode * Flush when change vxrm * Add more skip condition for mip and hip | 1 年前 |
| update sbt version | 7 年前 |
| refactor: remove TileLink version of XiangShan (#5992) This PR completes the XiangShan cleanup after removing the legacy TileLink-based cache path and consolidating the repo around a single CHI-based config. It removes the remaining TileLink/HuanCun-specific wiring, configs, and build flow dependencies, aligns the codebase with the refactored XSCache submodule, and makes `DefaultConfig` the primary user-facing configuration while keeping `BackendV2Config` available in perf-trigger workflows. In parallel, the CI/test flow is simplified by moving the basic EMU coverage into the dedicated emu-basics workflow and removing redundant coverage from emu.yml. Concretely, this pr removes huancun submodule and its build dependencies, drops the old TL L3 parameter system from SoC/top-level configs, updates imports and package references to the new `xscache.{coupledL2, openLLC, chi, common}` hierarchy, and cleans up scripts, docs, and workflow defaults to reflect the CHI-only world. | 1 个月前 |
| feat(ifu): add a resolve feedback path from the IFU to the BPU for training (#6112) Signed-off-by: ngc7331 <ngc7331@outlook.com> Co-authored-by: ngc7331 <ngc7331@outlook.com> | 21 小时前 |
| misc: update PCL information (#899) XiangShan is jointly released by ICT and PCL. | 4 年前 |
| submodule(ChiselAIA): bump ChiselAIA (#5549) | 5 个月前 |
| fix(IOPMP): Fix IOPMP address with XiangShan MMIO config Signed-off-by: yuanhongtuo <yuanhongtuo@bosc.ac.cn> | 4 个月前 |
| perf(pf): optimize l1 prefetcher training and for training (#5544) | 4 天前 |
| submodule(difftest): expose CPU/MEM AXI for fpgadiff (#6098) Corresponding kunminghu-v2 changes: https://github.com/OpenXiangShan/XiangShan/pull/6026 https://github.com/OpenXiangShan/XiangShan/pull/6049 https://github.com/OpenXiangShan/XiangShan/pull/6055 | 16 天前 |
| submodule(ready-to-run): bump ready-to-run to support tdata3 | 27 天前 |
| feat(mpt): add mpt v0.4 support for Xiangshan (#5915) * This PR adds MPT v0.4 functionality into the KMHv3. Memory Protection Tables (MPT) is a RISC-V hardware extension that enforces fine‑grained access control on physical memory. It is designed for multi‑tenant and multi‑supervisor‑domain environments, where traditional isolation mechanisms (PMP, MMU) are insufficient. MPT allows a root domain security manager (RDSM) to define per‑domain access policies (read, write, execute) for arbitrary physical memory regions, using a multi‑level table structure stored in memory. It works alongside PMP and the virtual memory system: an access is allowed only if all three protection mechanisms permit it. * Added an MptChecker module to perform MPT checks, and modified the MMU (L2TLB and L1TLB) to support the MPT feature during page table walk. * Can be included in Xiangshan via the HasMptcheck flag (default: false). * Cannot be used simultaneously with Bitmap. * Once included, the MPT feature can be enabled through the mmpt CSR. If included but not enabled, MPT does not affect the behavior of the rest of the chip. * Future plans: * Incorporate Bitmap functionality into MPT, making Bitmap a special mode of MPT. * Add MPT CI to test the PR when MPT is enabled. | 25 天前 |
| timing(utility): shorten HwSort compare path for 3 and 4 inputs Adopt the new hwSort algorithm. It has no functional differences from the original one, but it is optimized in terms of timing and reduces the length of comparison paths. | 20 天前 |
| feat(I2F): bump yunsuan to support a new I2F FU | 4 个月前 |
| fix(docker): fix docker image build by moving MILL_OUTPUT_DIR to tmpfs (#4679) Signed-off-by: Jiuyue Ma <majiuyue@bosc.ac.cn> | 1 年前 |
| fix(xspdb): fix docs typo | 3 个月前 |
| refactor: remove TileLink version of XiangShan (#5992) This PR completes the XiangShan cleanup after removing the legacy TileLink-based cache path and consolidating the repo around a single CHI-based config. It removes the remaining TileLink/HuanCun-specific wiring, configs, and build flow dependencies, aligns the codebase with the refactored XSCache submodule, and makes `DefaultConfig` the primary user-facing configuration while keeping `BackendV2Config` available in perf-trigger workflows. In parallel, the CI/test flow is simplified by moving the basic EMU coverage into the dedicated emu-basics workflow and removing redundant coverage from emu.yml. Concretely, this pr removes huancun submodule and its build dependencies, drops the old TL L3 parameter system from SoC/top-level configs, updates imports and package references to the new `xscache.{coupledL2, openLLC, chi, common}` hierarchy, and cleans up scripts, docs, and workflow defaults to reflect the CHI-only world. | 1 个月前 |
| refactor(build): overhaul build scripts (#5010) Mill introduces some breaking changes lately. This PR overhauls build scripts to adapt to these changes. Now `build.sc` becomes `build.mill`. Besides, since we don't support sbt anyway, and `build.sbt` has not been maintained for a long time and will not be maintained in the future, we had better remove it. Mill version stays 0.12.15 instead of 1.0.4 because support for `VcsVersion` plugin in broken in Mill 1.0.0 and above. APIs in 0.12.x is different from that of 1.0.x, but we'll solve them later. Since IDEA 2025.1, scala syntax highlighting is almost broken if the project is built with `build.sc`. Now IDEA supports mill again with `build.mill` through BSP. **Run `make bsp` instead of `make idea` to get indexed!** This PR also remove many unnecessary codes in the original build script. | 9 个月前 |
| refactor(mbtb,Tage): add VecRotate util (#5218) ... for later re-use in ICache also: - fix rotate direction, the original `(j + i) % len` is actually rotating left, `(j + len - i) % len` is right - fix tage base table `io.takenCtrs`, it needs the opposite direction of `startVAddr` to recover original order Though, the above fixes should not have changes in final verilog now, as rotating to left or right behaves the same with `len = 2` and: - add comments in mbtb & Tage for explanation of rotation - remove unused imports | 7 个月前 |
| fix(docker): fix docker image build by moving MILL_OUTPUT_DIR to tmpfs (#4679) Signed-off-by: Jiuyue Ma <majiuyue@bosc.ac.cn> | 1 年前 |
| Add MulanPSL-2.0 License (#824) In this commit, we add License for XiangShan project. | 4 年前 |
| chore: explicitly pass OBJCACHE to difftest/verilator.mk (#5907) In https://github.com/OpenXiangShan/difftest/pull/872, we disabled OBJCACHE by default due to the following reason: 1. it does not help XiangShan's build performance in most cases, as slight change in chisel result in significant change in cpp code 2. it introduces too much IO overhead In this PR we allow using 'make emu OBJCACHE=ccache' to enable it Signed-off-by: ngc7331 <ngc7331@outlook.com> | 15 天前 |
| test: add example of chiseltest's unit-test and generating verilog for xs' module (#1890) * test: add example to genenrate verilog for a small module Just use Parameters from DefaultConfig(& Argparser) like XSTop/SimTop * test: add DecodeUnitTest as an example for xs' chiseltest * ctrlblock: <> usage has changed, unidirection should use := * bump huancun * makefile: mv new makefile cmd into Makefile.test | 3 年前 |
| refactor: remove TileLink version of XiangShan (#5992) This PR completes the XiangShan cleanup after removing the legacy TileLink-based cache path and consolidating the repo around a single CHI-based config. It removes the remaining TileLink/HuanCun-specific wiring, configs, and build flow dependencies, aligns the codebase with the refactored XSCache submodule, and makes `DefaultConfig` the primary user-facing configuration while keeping `BackendV2Config` available in perf-trigger workflows. In parallel, the CI/test flow is simplified by moving the basic EMU coverage into the dedicated emu-basics workflow and removing redundant coverage from emu.yml. Concretely, this pr removes huancun submodule and its build dependencies, drops the old TL L3 parameter system from SoC/top-level configs, updates imports and package references to the new `xscache.{coupledL2, openLLC, chi, common}` hierarchy, and cleans up scripts, docs, and workflow defaults to reflect the CHI-only world. | 1 个月前 |
| refactor: remove TileLink version of XiangShan (#5992) This PR completes the XiangShan cleanup after removing the legacy TileLink-based cache path and consolidating the repo around a single CHI-based config. It removes the remaining TileLink/HuanCun-specific wiring, configs, and build flow dependencies, aligns the codebase with the refactored XSCache submodule, and makes `DefaultConfig` the primary user-facing configuration while keeping `BackendV2Config` available in perf-trigger workflows. In parallel, the CI/test flow is simplified by moving the basic EMU coverage into the dedicated emu-basics workflow and removing redundant coverage from emu.yml. Concretely, this pr removes huancun submodule and its build dependencies, drops the old TL L3 parameter system from SoC/top-level configs, updates imports and package references to the new `xscache.{coupledL2, openLLC, chi, common}` hierarchy, and cleans up scripts, docs, and workflow defaults to reflect the CHI-only world. | 1 个月前 |
| refactor: remove TileLink version of XiangShan (#5992) This PR completes the XiangShan cleanup after removing the legacy TileLink-based cache path and consolidating the repo around a single CHI-based config. It removes the remaining TileLink/HuanCun-specific wiring, configs, and build flow dependencies, aligns the codebase with the refactored XSCache submodule, and makes `DefaultConfig` the primary user-facing configuration while keeping `BackendV2Config` available in perf-trigger workflows. In parallel, the CI/test flow is simplified by moving the basic EMU coverage into the dedicated emu-basics workflow and removing redundant coverage from emu.yml. Concretely, this pr removes huancun submodule and its build dependencies, drops the old TL L3 parameter system from SoC/top-level configs, updates imports and package references to the new `xscache.{coupledL2, openLLC, chi, common}` hierarchy, and cleans up scripts, docs, and workflow defaults to reflect the CHI-only world. | 1 个月前 |
| chore(scalastyle): allow ([a-z][0-9]|perf|debug)_ prefix (#4838) | 11 个月前 |
| chore(scalastyle): allow ([a-z][0-9]|perf|debug)_ prefix (#4838) | 11 个月前 |