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broadcom/compiler: padding fixes to QPU assembly dumps When there are dst/src modifiers it is pretty common that instructions take too much space and lead to alignment issues that make code a lot harder to read, so align the MUL and SIG columns a bit wider to avoid this: Before: 0x380021828003faa8 fmax rf2, rf42.abs, rf40.abs; nop 0x3800f186c503f0f0 fcmp.pushc -, rf3, rf48; nop 0x380c038b85b83282 fmax rf11, rf10, rf2; mov.ifa rf14, rf46 0x3800219ab503f359 and rf26, rf13, rf25; nop 0x3820f186c503f2f0 fcmp.pushc -, rf11, rf48; nop ; thrsw 0x382c013fb5b8368e and rf63, rf26, rf14; mov.ifa rf4, rf46; thrsw 0x38002185b503ffc4 and rf5, rf63, rf4 ; nop 0x38002186b503f141 and rf6, rf5, rf1 ; nop 0x382031873503f186 vfpack tlb, rf6, rf6; nop ; thrsw 0x380031873503f18f vfpack tlb, rf6, rf15; nop 0x38003186bb03f000 nop ; nop After: 0x380021828003faa8 fmax rf2, rf42.abs, rf40.abs ; nop 0x3800f186c503f0f0 fcmp.pushc -, rf3, rf48 ; nop 0x380c038b85b83282 fmax rf11, rf10, rf2 ; mov.ifa rf14, rf46 0x3800219ab503f359 and rf26, rf13, rf25 ; nop 0x3820f186c503f2f0 fcmp.pushc -, rf11, rf48 ; nop ; thrsw 0x382c013fb5b8368e and rf63, rf26, rf14 ; mov.ifa rf4, rf46 ; thrsw 0x38002185b503ffc4 and rf5, rf63, rf4 ; nop 0x38002186b503f141 and rf6, rf5, rf1 ; nop 0x382031873503f186 vfpack tlb, rf6, rf6 ; nop ; thrsw 0x380031873503f18f vfpack tlb, rf6, rf15 ; nop 0x38003186bb03f000 nop ; nop Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13545> | 1 年前 | |
meson: use gnu_symbol_visibility argument This uses a meson builtin to handle -fvisibility=hidden. This is nice because we don't need to track which languages are used, if C++ is suddenly added meson just does the right thing. Acked-by: Matt Turner <mattst88@gmail.com> Reviewed-by: Eric Engestrom <eric@engestrom.ch> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4740> | 6 年前 | |
broadcom/compiler: padding fixes to QPU assembly dumps When there are dst/src modifiers it is pretty common that instructions take too much space and lead to alignment issues that make code a lot harder to read, so align the MUL and SIG columns a bit wider to avoid this: Before: 0x380021828003faa8 fmax rf2, rf42.abs, rf40.abs; nop 0x3800f186c503f0f0 fcmp.pushc -, rf3, rf48; nop 0x380c038b85b83282 fmax rf11, rf10, rf2; mov.ifa rf14, rf46 0x3800219ab503f359 and rf26, rf13, rf25; nop 0x3820f186c503f2f0 fcmp.pushc -, rf11, rf48; nop ; thrsw 0x382c013fb5b8368e and rf63, rf26, rf14; mov.ifa rf4, rf46; thrsw 0x38002185b503ffc4 and rf5, rf63, rf4 ; nop 0x38002186b503f141 and rf6, rf5, rf1 ; nop 0x382031873503f186 vfpack tlb, rf6, rf6; nop ; thrsw 0x380031873503f18f vfpack tlb, rf6, rf15; nop 0x38003186bb03f000 nop ; nop After: 0x380021828003faa8 fmax rf2, rf42.abs, rf40.abs ; nop 0x3800f186c503f0f0 fcmp.pushc -, rf3, rf48 ; nop 0x380c038b85b83282 fmax rf11, rf10, rf2 ; mov.ifa rf14, rf46 0x3800219ab503f359 and rf26, rf13, rf25 ; nop 0x3820f186c503f2f0 fcmp.pushc -, rf11, rf48 ; nop ; thrsw 0x382c013fb5b8368e and rf63, rf26, rf14 ; mov.ifa rf4, rf46 ; thrsw 0x38002185b503ffc4 and rf5, rf63, rf4 ; nop 0x38002186b503f141 and rf6, rf5, rf1 ; nop 0x382031873503f186 vfpack tlb, rf6, rf6 ; nop ; thrsw 0x380031873503f18f vfpack tlb, rf6, rf15 ; nop 0x38003186bb03f000 nop ; nop Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13545> | 1 年前 | |
broadcom/qpu: rename from VC5 to V3D Get rid of old references to VC5. Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com> Signed-off-by: Juan A. Suarez Romero <jasuarez@igalia.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10402> | 5 年前 | |
broadcom/compiler: rework simultaneous peripheral access checks This was not quite correct in that our checks for the allowed cases were not checking that there were no other peripheral access other than the ones allowed. For example, we allowed wrtmuc signal and TMU write other than TMUC, and we also allowed TMU read and VPM read/write. But we cannot allow wrtmuc with TMU write other than TMUC and at the same time a VPM write for example, so we can't just check if we have a combination of allowed peripherals, we still need to check that those are the only ones in use by the combined instructions. Another example is that even if we allow a TMU write (other than TMUC) with a wrtmuc signal, the resulting instruction must still have just one TMU write other than TMUC, but we were allowing the merge if one instruction signaled wrtmuc and the other wrote to tmu other than tmuc without testing if the combined result would have 2 tmu writes. Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13527> | 1 年前 | |
broadcom/compiler: rework simultaneous peripheral access checks This was not quite correct in that our checks for the allowed cases were not checking that there were no other peripheral access other than the ones allowed. For example, we allowed wrtmuc signal and TMU write other than TMUC, and we also allowed TMU read and VPM read/write. But we cannot allow wrtmuc with TMU write other than TMUC and at the same time a VPM write for example, so we can't just check if we have a combination of allowed peripherals, we still need to check that those are the only ones in use by the combined instructions. Another example is that even if we allow a TMU write (other than TMUC) with a wrtmuc signal, the resulting instruction must still have just one TMU write other than TMUC, but we were allowing the merge if one instruction signaled wrtmuc and the other wrote to tmu other than tmuc without testing if the combined result would have 2 tmu writes. Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13527> | 1 年前 | |
broadcom: drop unused functions Fixes a clang warning about unused static inlined functions Reviewed-by: Juan A. Suarez <jasuarez@igalia.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14790> | 1 年前 | |
broadcom: Add V3D 3.3 QPU instruction pack, unpack, and disasm. Unlike VC4, I've defined an unpacked instruction format with pack/unpack functions to convert to 64-bit encoded instructions. This will let us incrementally put together our instructions and validate them in a more natural way than the QPU_GET_FIELD/QPU_SET_FIELD used to. The pack/unpack unfortuantely are written by hand. While I could define genxml for parts of it, there are many special cases (like operand order of commutative binops choosing which binop is being performed!) and it probably wouldn't come out much cleaner. The disasm unit test ensures that we have the same assembly format as Broadcom's internal tools, other than whitespace changes. v2: Fix automake variable redefinition complaints, add test to .gitignore | 8 年前 |
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