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ir3: Refactor ir3_compiler_create() to take an options struct This will let us add more options without creating too much churn. Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13148> | 1 年前 | |
ir3: Update .editorconfig and .dir-locals.el Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11801> | 1 年前 | |
ir3: Update .editorconfig and .dir-locals.el Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11801> | 1 年前 | |
ir3: Implement and document ldc.k Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13148> | 1 年前 | |
ir3: Implement and document ldc.k Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13148> | 1 年前 | |
ir3: Don't include preamble instructions in stats Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13148> | 1 年前 | |
ir3: Implement and document ldc.k Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13148> | 1 年前 | |
freedreno/ir3: support a4xx in load/store buffer/image emission Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14794> | 1 年前 | |
freedreno/ir3: handle global atomics Only for a6xx since we don't know the instructions for global atomics on previous gens. Per Qualcomm's docs in OpenCL atomics are only supported since a5xx together with Generic memory space. Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8717> | 1 年前 | |
ir3: Reformat source with clang-format Generated using: cd src/freedreno/ir3 && clang-format -i {**,.}/*.c {**,.}/*.h -style=file Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11801> | 1 年前 | |
freedreno/computerator: Fix mergedregs This was getting set *after* ir3_shader_assemble, which was too late. Signed-off-by: Rob Clark <robdclark@chromium.org> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13426> | 1 年前 | |
a4xx/computerator: add initial backend This backend provides very basic a4xx support. It's enough to run kernels with explicit stg/etc ops, but not with stgb/ldgb type access. There is no perfcounter support hooked up yet either. Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12784> | 1 年前 | |
ir3: prohibit folding of half->full conversion into mul.s24/u24 mul.s24/u24 always return 32b result regardless of its sources size, hence we cannot guarantee the high 16b of dst being zero or sign extended. Fixes cts tests on a650: dEQP-VK.spirv_assembly.type.scalar.i16.mul_test_high_part_zero_* Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12471> | 1 年前 | |
ir3, turnip: Use ldc.k to push UBOs This reuses the same UBO analysis to do the pushing in the shader preamble via the ldc.k instruction instead of in the driver via CP_LOAD_STATE6. The const_data UBO is exempted as it uses a different codepath that isn't as critical. Don't do this on gallium because there are some regressions. Aztec Ruins in particular regresses a bit, and nothing I've benchmarked benefits. Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13148> | 1 年前 | |
ir3, turnip: Use ldc.k to push UBOs This reuses the same UBO analysis to do the pushing in the shader preamble via the ldc.k instruction instead of in the driver via CP_LOAD_STATE6. The const_data UBO is exempted as it uses a different codepath that isn't as critical. Don't do this on gallium because there are some regressions. Aztec Ruins in particular regresses a bit, and nothing I've benchmarked benefits. Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13148> | 1 年前 | |
ir3: set local_size for shaders of MESA_SHADER_KERNEL type ir3_compile_shader_nir() should set local_size[] and local_size_variable fields not only for compute shaders, but for the OpenCL kernels too. v2: use gl_shader_stage_is_compute() instead of explicit comparison with MESA_SHADER_[COMPUTE,KERNEL]. Signed-off-by: Andrey Konovalov <andrey.konovalov@linaro.org> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14863> | 1 年前 | |
freedreno/a4xx: extend astc and tg4 workarounds to compute shaders Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15251> | 1 年前 | |
freedreno/a4xx: add swizzles to shader keys for tg4 workaround Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14670> | 1 年前 | |
freedreno/ir3: Don't try re-swapping cat3 srcs This can lead us to endless loops of "progress".. Note fixes commit commit really just exposed an existing problem. Fixes: 9c9e8c33498 ("nir: Reorder ffma and fsub combining") Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/6133 Signed-off-by: Rob Clark <robdclark@chromium.org> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15336> | 1 年前 | |
ir3/cp_postsched: Support multiple destinations Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14107> | 1 年前 | |
ir3/cse: Support mov instructions This doesn't affect shader-db at all, but it will help clean up the mov's emitted in the next commit when there are multiple ldp/stp. Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13307> | 1 年前 | |
ir3/dce: Support multiple destinations Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14107> | 1 年前 | |
ir3: Use (ss) for instructions writing shared regs The blob uses *both* nops and (ss). It turns out that in some rare cases the hardware does take more than 6 cycles, at least for movmsk, but adding nops is unnecessary. I believe the extra nops are only there due to the immaturity of the blob's implementation of subgroup ops, so we don't have to copy them - just handle shared reg producers the same as SFU instructions. Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14246> | 1 年前 | |
ir3: Add wavesize control This allows the wavesize to be controlled per-shader. This will be used by VK_EXT_subgroup_size_control, and freedreno will also need it if legacy ARB_shader_ballot is to be supported (since it forces a wavesize of 64 or less). Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13960> | 1 年前 | |
ir3: Reformat source with clang-format Generated using: cd src/freedreno/ir3 && clang-format -i {**,.}/*.c {**,.}/*.h -style=file Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11801> | 1 年前 | |
freedreno/ir3: fix image-to-tex flags, remove 3d -> array hack The function would return both the 3d and array flags set for 2d array, and would return just 3d for cubes. Fix the flags so that they are appropriate for images. Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13804> | 1 年前 | |
ir3: Reformat source with clang-format Generated using: cd src/freedreno/ir3 && clang-format -i {**,.}/*.c {**,.}/*.h -style=file Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11801> | 1 年前 | |
ir3: Support prefetching with preambles Since the NIR pass runs very late, it needs to be aware of preambles, and when creating the instruction we need to move it to the start block so that RA doesn't overwrite it in the preamble. Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13148> | 1 年前 | |
ir3: Implement and document ldc.k Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13148> | 1 年前 | |
freedreno/ir3: Cleanup liveness lifetime I'm going to want to use this in other passes, so lets let the allocation hang off the pass's context. Also, while we're at it, fix the error path leak in ir3_ra(). Fixes: 0ffcb19b9d9 ("ir3: Rewrite register allocation") Signed-off-by: Rob Clark <robdclark@chromium.org> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12923> | 1 年前 | |
ir3/lower_pcopy: Fix bug with "illegal" copies and swaps If the source and destination were within the same full register, like hr90.x and hr90.y (which both map to r45.x), then we'd perform the swap/copy with the wrong register. This broke dEQP-VK.ssbo.phys.layout.random.16bit.scalar.35 once BDA is enabled. Fixes: 0ffcb19b9d9 ("ir3: Rewrite register allocation") Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13818> | 1 年前 | |
ir3/lower_spill: Fix corner case with oob offsets If the base register is killed, it may be reused as the destination of a ldp. In that case we should just skip resetting it afterwards. Fixes regressions in dEQP-VK.ssbo.layout.random.scalar.38 later. Fixes: 9912c61362b ("ir3/spill: Support larger spill slot offset") Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15288> | 1 年前 | |
ir3: Add support for subgroup arithmetic Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14107> | 1 年前 | |
ir3: Initial support for spilling non-shared registers Support for spilling shared registers to normal registers is still TODO. There are also several improvements to be made, like rematerialization. Note, there is one behavior change to register pressure accounting: we now include half registers in the current full pressure directly in mergedregs mode, rather than adding the max half pressure to the max full pressure afterwards, which might result in lower calculated max pressure in some cases with half registers. This is needed for spilling, since we need to make sure the total pressure including half registers is below the maximum at each instruction. Because the entire pass is rewritten, including the register pressure calculating parts, it didn't seem worth it to separate out this change. Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12033> | 1 年前 | |
ir3: Add preamble optimization pass Now that everything is plumbed through, we can tie it together. Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13148> | 1 年前 | |
ir3: Add preamble optimization pass Now that everything is plumbed through, we can tie it together. Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13148> | 1 年前 | |
ir3, turnip: Use ldc.k to push UBOs This reuses the same UBO analysis to do the pushing in the shader preamble via the ldc.k instruction instead of in the driver via CP_LOAD_STATE6. The const_data UBO is exempted as it uses a different codepath that isn't as critical. Don't do this on gallium because there are some regressions. Aztec Ruins in particular regresses a bit, and nothing I've benchmarked benefits. Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13148> | 1 年前 | |
python: drop python2 support Signed-off-by: Eric Engestrom <eric@engestrom.ch> Acked-by: Jose Fonseca <jfonseca@vmware.com> Reviewed-by: Alyssa Rosenzweig <alyssa@collabora.com> Reviewed-by: Dylan Baker <dylan@pnwbakers.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3674> | 1 年前 | |
freedreno/ir3: handle global atomics Only for a6xx since we don't know the instructions for global atomics on previous gens. Per Qualcomm's docs in OpenCL atomics are only supported since a5xx together with Generic memory space. Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8717> | 1 年前 | |
ir3: Use isam for bindless readonly ssbo loads Since this isn't hooked up in gallium, only do it for bindless for now. Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15288> | 1 年前 | |
ir3: Reformat source with clang-format Generated using: cd src/freedreno/ir3 && clang-format -i {**,.}/*.c {**,.}/*.h -style=file Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11801> | 1 年前 | |
ir3: Reformat source with clang-format Generated using: cd src/freedreno/ir3 && clang-format -i {**,.}/*.c {**,.}/*.h -style=file Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11801> | 1 年前 | |
freedreno/ir3: set proper dst size for {store,load}_{global,shared}_ir3 We want to pass 64b variables. Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com> Signed-off-by: Rob Clark <robdclark@chromium.org> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13300> | 1 年前 | |
ir3: Support prefetching with preambles Since the NIR pass runs very late, it needs to be aware of preambles, and when creating the instruction we need to move it to the start block so that RA doesn't overwrite it in the preamble. Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13148> | 1 年前 | |
freedreno/ir3: Add wide load/store lowering Lower load/store for vectors wider than 4. Signed-off-by: Rob Clark <robdclark@chromium.org> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13300> | 1 年前 | |
ir3: Reformat source with clang-format Generated using: cd src/freedreno/ir3 && clang-format -i {**,.}/*.c {**,.}/*.h -style=file Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11801> | 1 年前 | |
ir3: Add preamble optimization pass Now that everything is plumbed through, we can tie it together. Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13148> | 1 年前 | |
ir3: Make trig replacement expression exact This prevents other optimizations from associating the inner multiply, which can add inaccuracies that can lead to discontinuities around the boundary of the ffract. We should use exactly the sequence that the blob uses to avoid problems. Since fadd + fmul cannot be combined to ffma when exact is specified, we have to use ffma ourselves. Fixes artifacts in PixMark Volplosion with !7458. Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12912> | 1 年前 | |
ir3: Implement and document ldc.k Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13148> | 1 年前 | |
ir3/postsched: Rename tex/sfu to sy/ss Analogous to the previous commit. Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14246> | 1 年前 | |
ir3: Implement and document ldc.k Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13148> | 1 年前 | |
ir3/ra: Add IR3_REG_EARLY_CLOBBER We'll need this to model the subgroup reduction macros. Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14107> | 1 年前 | |
ir3/ra: Fix ra_foreach_dst_n Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14107> | 1 年前 | |
ir3: Reformat source with clang-format Generated using: cd src/freedreno/ir3 && clang-format -i {**,.}/*.c {**,.}/*.h -style=file Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11801> | 1 年前 | |
ir3: Add pass to remove unreachable blocks Rather than continue to add special cases for these, just clean them up. Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12033> | 1 年前 | |
ir3/sched: Support multiple destinations Note: this is a behavior change for arrays, because it will count the entire array instead of just the components written in the register pressure calculation. However this is more accurate since this matches how RA works. Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14107> | 1 年前 | |
freedreno/a4xx: extend astc and tg4 workarounds to compute shaders Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15251> | 1 年前 | |
ir3: Add preamble optimization pass Now that everything is plumbed through, we can tie it together. Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13148> | 1 年前 | |
ir3/spill: Mark reload destination as early-clobber Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14107> | 1 年前 | |
ir3: Implement and document ldc.k Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13148> | 1 年前 | |
ir3: Add preamble optimization pass Now that everything is plumbed through, we can tie it together. Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13148> | 1 年前 |
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