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已合并
UBC_CTP->UB_CTP #176
chen_xu0513创建于 9月14日
UBC_CTP->UB_CTP #176
已合并
chen_xu0513创建于 9月14日
从chen_xu0513/asc-commprotocol合入到cann/asc-commmaster
共 23 个文件变更+152-150
MREADME.md+10-10
@@ -19,10 +19,10 @@
19 19 
20### 🚀 当前能力20### 🚀 当前能力
21 21 
22-- 提供AICore侧Hcomm点对点通信接口，覆盖普通`Init`、`ReadNbi`、`WriteNbi`、`WriteWithNotifyNbi`、`AtomicFAA`、`AtomicCAS`、`Commit`、`Drain`，以及Ascend 950 UBC_CTP路径的`MakeBatchHandle`、批量读写、`BatchCommit`和批量`Drain`。22+- 提供AICore侧Hcomm点对点通信接口，覆盖普通`Init`、`ReadNbi`、`WriteNbi`、`WriteWithNotifyNbi`、`AtomicFAA`、`AtomicCAS`、`Commit`、`Drain`，以及Ascend 950 UB_CTP路径的`MakeBatchHandle`、批量读写、`BatchCommit`和批量`Drain`。
23-- 提供AIV直驱Hcomm RoCE和UBC_CTP/URMA相关实现，主实现位于`src/aicore/hcomm/`。23+- 提供AIV直驱Hcomm RoCE和UB_CTP/URMA相关实现，主实现位于`src/aicore/hcomm/`。
24- 提供AICore侧Ain单边通信接口，覆盖`Put`、`PutValue`、`Get`、`Signal`、`ReadSignal`、`WaitSignal`、`Flush`、`FlushAsync`、`Wait`，以及`AinBarrierSession`集合通信同步原语，主实现位于`src/aicore/ain/`。24- 提供AICore侧Ain单边通信接口，覆盖`Put`、`PutValue`、`Get`、`Signal`、`ReadSignal`、`WaitSignal`、`Flush`、`FlushAsync`、`Wait`，以及`AinBarrierSession`集合通信同步原语，主实现位于`src/aicore/ain/`。
25-- 提供Hcomm UT工程，覆盖`ascend950pr_9599_AIV`的RoCE/URMA普通接口和UBC_CTP批量接口，以及`ascend910B1_AIC`基础接口用例。25+- 提供Hcomm UT工程，覆盖`ascend950pr_9599_AIV`的RoCE/URMA普通接口和UB_CTP批量接口，以及`ascend910B1_AIC`基础接口用例。
26- 提供Ain UT工程，覆盖`ascend950pr_9599_AIV`的URMA路径下`Put`/`Get`/`Signal`/`ReadSignal`/`WaitSignal`/`BarrierSession`接口用例。26- 提供Ain UT工程，覆盖`ascend950pr_9599_AIV`的URMA路径下`Put`/`Get`/`Signal`/`ReadSignal`/`WaitSignal`/`BarrierSession`接口用例。
27- 提供`hcomm_write_read_nbi`样例，演示AIV直驱URMA场景下`WriteNbi`和`ReadNbi`点对点通信流程，并包含运行样例所需的Host侧资源准备流程。27- 提供`hcomm_write_read_nbi`样例，演示AIV直驱URMA场景下`WriteNbi`和`ReadNbi`点对点通信流程，并包含运行样例所需的Host侧资源准备流程。
28- 提供SIMT URMA `WriteNbi`、`WriteValueNbi`、`ReadNbi`、`WriteWithNotifyNbi`、`AtomicFAA`、`AtomicCAS`和`Drain`，以及`simt_urma`功能样例和`simt_urma_perftest`性能样例。28- 提供SIMT URMA `WriteNbi`、`WriteValueNbi`、`ReadNbi`、`WriteWithNotifyNbi`、`AtomicFAA`、`AtomicCAS`和`Drain`，以及`simt_urma`功能样例和`simt_urma_perftest`性能样例。
@@ -39,7 +39,7 @@
39 39 
40asc-comm是面向昇腾AI处理器通信场景的开源仓，当前用于承载AICore侧公开API、AIV直驱设备侧实现、API文档、样例和验证能力。40asc-comm是面向昇腾AI处理器通信场景的开源仓，当前用于承载AICore侧公开API、AIV直驱设备侧实现、API文档、样例和验证能力。
41 41 
42-当前公开能力包括`AscendC::Hcomm`点对点通信和`AscendC::Ain`单边通信，面向算子Kernel侧通信数据路径。Hcomm侧使用方通过`AscendC::Hcomm`模板选择通信协议：普通接口通过`ChannelHandle`逐条提交通信任务；Ascend 950 UBC_CTP路径还可以通过BatchHandle添加多个通信任务，并通过`BatchCommit`统一提交。两种流程分别通过对应的`Drain`重载管理完成等待。Ain侧使用方通过`AscendC::Ain`模板基于对称窗口（Symmetric Window）发起`Put`/`Get`/`Signal`等单边操作，通过`Flush`或`FlushAsync`+`Wait`管理完成等待。42+当前公开能力包括`AscendC::Hcomm`点对点通信和`AscendC::Ain`单边通信，面向算子Kernel侧通信数据路径。Hcomm侧使用方通过`AscendC::Hcomm`模板选择通信协议：普通接口通过`ChannelHandle`逐条提交通信任务；Ascend 950 UB_CTP路径还可以通过BatchHandle添加多个通信任务，并通过`BatchCommit`统一提交。两种流程分别通过对应的`Drain`重载管理完成等待。Ain侧使用方通过`AscendC::Ain`模板基于对称窗口（Symmetric Window）发起`Put`/`Get`/`Signal`等单边操作，通过`Flush`或`FlushAsync`+`Wait`管理完成等待。
43 43 
44### 交付与构建方式44### 交付与构建方式
45 45 
@@ -49,12 +49,12 @@ asc-comm 数据面产物（`libasccomm_ccu_dataplane.so`、CCU DSL 头和其 hco
49 49 
50| 能力 | 当前状态 |50| 能力 | 当前状态 |
51| --- | --- |51| --- | --- |
52-| AICore Hcomm公开接口 | 已提供Kernel侧普通`Init`、读写、写通知、原子、`Commit`和`Drain`接口；Ascend 950 UBC_CTP路径还提供`MakeBatchHandle`、批量`ReadNbi`/`WriteNbi`/`WriteWithNotifyNbi`、`BatchCommit`和批量`Drain`。 |52+| AICore Hcomm公开接口 | 已提供Kernel侧普通`Init`、读写、写通知、原子、`Commit`和`Drain`接口；Ascend 950 UB_CTP路径还提供`MakeBatchHandle`、批量`ReadNbi`/`WriteNbi`/`WriteWithNotifyNbi`、`BatchCommit`和批量`Drain`。 |
53| AICore Ain公开接口 | 已提供Kernel侧`Put`、`PutValue`、`Get`、`Signal`、`ReadSignal`、`WaitSignal`、`Flush`、`FlushAsync`、`Wait`，以及`AinBarrierSession`同步原语。 |53| AICore Ain公开接口 | 已提供Kernel侧`Put`、`PutValue`、`Get`、`Signal`、`ReadSignal`、`WaitSignal`、`Flush`、`FlushAsync`、`Wait`，以及`AinBarrierSession`同步原语。 |
54-| AIV直驱实现 | 已提供Hcomm RoCE和UBC_CTP/URMA相关实现，主实现位于`src/aicore/hcomm/`；Ain实现位于`src/aicore/ain/`。 |54+| AIV直驱实现 | 已提供Hcomm RoCE和UB_CTP/URMA相关实现，主实现位于`src/aicore/hcomm/`；Ain实现位于`src/aicore/ain/`。 |
55| AIV直驱样例配套流程 | `hcomm_write_read_nbi`包含AIV直驱URMA通信所需的通信域创建、通信内存注册、P2P通道创建和远端内存获取流程。 |55| AIV直驱样例配套流程 | `hcomm_write_read_nbi`包含AIV直驱URMA通信所需的通信域创建、通信内存注册、P2P通道创建和远端内存获取流程。 |
56-| 协议能力 | `COMM_PROTOCOL_ROCE`支持普通读写、提交和等待；`COMM_PROTOCOL_UBC_CTP`支持普通读写、写通知、原子操作、提交和等待，Ascend 950还支持批量读写、写通知、提交和等待。 |56+| 协议能力 | `COMM_PROTOCOL_ROCE`支持普通读写、提交和等待；`COMM_PROTOCOL_UB_CTP`支持普通读写、写通知、原子操作、提交和等待，Ascend 950还支持批量读写、写通知、提交和等待。 |
57-| UT验证 | UT覆盖`ascend950pr_9599_AIV`的Hcomm RoCE/URMA普通接口、UBC_CTP批量接口与Ain URMA路径，以及`ascend910B1_AIC`基础接口用例。 |57+| UT验证 | UT覆盖`ascend950pr_9599_AIV`的Hcomm RoCE/URMA普通接口、UB_CTP批量接口与Ain URMA路径，以及`ascend910B1_AIC`基础接口用例。 |
58| AIV直驱样例 | 提供`hcomm_write_read_nbi`样例，覆盖两卡AIV直驱URMA `WriteNbi`/`ReadNbi`对称通信和结果校验流程。 |58| AIV直驱样例 | 提供`hcomm_write_read_nbi`样例，覆盖两卡AIV直驱URMA `WriteNbi`/`ReadNbi`对称通信和结果校验流程。 |
59| SIMT URMA接口 | 提供`WriteNbi`、`WriteValueNbi`、`ReadNbi`、`WriteWithNotifyNbi`、`AtomicFAA`、`AtomicCAS`和`Drain`；延迟任务由后续`commit=true`任务统一发布。 |59| SIMT URMA接口 | 提供`WriteNbi`、`WriteValueNbi`、`ReadNbi`、`WriteWithNotifyNbi`、`AtomicFAA`、`AtomicCAS`和`Drain`；延迟任务由后续`commit=true`任务统一发布。 |
60| SIMT URMA样例 | 提供`simt_urma`功能样例，覆盖全部五个接口的单接口、连续提交和batch-last提交；提供`simt_urma_perftest`性能样例，统计下发时延与完成带宽。 |60| SIMT URMA样例 | 提供`simt_urma`功能样例，覆盖全部五个接口的单接口、连续提交和batch-last提交；提供`simt_urma_perftest`性能样例，统计下发时延与完成带宽。 |
@@ -75,7 +75,7 @@ Hcomm Kernel侧使用时包含如下头文件：
754. 如果提交任务时设置`commit = false`，调用`Commit`显式提交通信任务。754. 如果提交任务时设置`commit = false`，调用`Commit`显式提交通信任务。
765. 调用`Drain`等待通道上的通信任务完成。765. 调用`Drain`等待通道上的通信任务完成。
77 77 
78-Ascend 950 UBC_CTP批量接口调用流程如下：78+Ascend 950 UB_CTP批量接口调用流程如下：
79 79 
801. 准备UB工作区，通过`MakeBatchHandle`创建批量句柄。该流程不依赖`Init`。801. 准备UB工作区，通过`MakeBatchHandle`创建批量句柄。该流程不依赖`Init`。
812. 通过BatchHandle重载的`ReadNbi`、`WriteNbi`或`WriteWithNotifyNbi`向当前批次添加任务，同一批次可以混合三种任务。812. 通过BatchHandle重载的`ReadNbi`、`WriteNbi`或`WriteWithNotifyNbi`向当前批次添加任务，同一批次可以混合三种任务。
@@ -89,7 +89,7 @@ Ascend 950 UBC_CTP批量接口调用流程如下：
89| 协议 | 能力说明 |89| 协议 | 能力说明 |
90| --- | --- |90| --- | --- |
91| `COMM_PROTOCOL_ROCE` | RoCE点对点通信路径，支持普通`ReadNbi`、`WriteNbi`、`Commit`、`Drain`，不支持`WriteWithNotifyNbi`和BatchHandle接口。 |91| `COMM_PROTOCOL_ROCE` | RoCE点对点通信路径，支持普通`ReadNbi`、`WriteNbi`、`Commit`、`Drain`，不支持`WriteWithNotifyNbi`和BatchHandle接口。 |
92-| `COMM_PROTOCOL_UBC_CTP` | UBC CTP/URMA点对点通信路径，支持普通`ReadNbi`、`WriteNbi`、`WriteWithNotifyNbi`、`AtomicFAA`、`AtomicCAS`、`Commit`、`Drain`；Ascend 950还支持BatchHandle批量接口。 |92+| `COMM_PROTOCOL_UB_CTP` | UBC CTP/URMA点对点通信路径，支持普通`ReadNbi`、`WriteNbi`、`WriteWithNotifyNbi`、`AtomicFAA`、`AtomicCAS`、`Commit`、`Drain`；Ascend 950还支持BatchHandle批量接口。 |
93 93 
94详细参数约束和返回值说明请参考[Hcomm使用说明](./docs/zh/guide/hcomm_usage.md)和[API参考](./docs/zh/api/README.md)。94详细参数约束和返回值说明请参考[Hcomm使用说明](./docs/zh/guide/hcomm_usage.md)和[API参考](./docs/zh/api/README.md)。
95 95 
MREADME_en.md+10-10
@@ -19,10 +19,10 @@ English | [简体中文](./README.md)
19 19 
20### 🚀 Current Capabilities20### 🚀 Current Capabilities
21 21 
22-- Exposes AICore-side Hcomm point-to-point communication interfaces, covering ordinary `Init`, `ReadNbi`, `WriteNbi`, `WriteWithNotifyNbi`, `AtomicFAA`, `AtomicCAS`, `Commit`, and `Drain`, as well as `MakeBatchHandle`, batch read/write, `BatchCommit`, and batch `Drain` on the Ascend 950 UBC_CTP path.22+- Exposes AICore-side Hcomm point-to-point communication interfaces, covering ordinary `Init`, `ReadNbi`, `WriteNbi`, `WriteWithNotifyNbi`, `AtomicFAA`, `AtomicCAS`, `Commit`, and `Drain`, as well as `MakeBatchHandle`, batch read/write, `BatchCommit`, and batch `Drain` on the Ascend 950 UB_CTP path.
23-- Provides AIV direct-drive implementations for Hcomm RoCE and UBC_CTP/URMA. Core implementations are located under `src/aicore/hcomm/`.23+- Provides AIV direct-drive implementations for Hcomm RoCE and UB_CTP/URMA. Core implementations are located under `src/aicore/hcomm/`.
24- Exposes AICore-side Ain one-sided communication interfaces, covering `Put`, `PutValue`, `Get`, `Signal`, `ReadSignal`, `WaitSignal`, `Flush`, `FlushAsync`, `Wait`, and the `AinBarrierSession` collective synchronization primitive. Core implementations are located under `src/aicore/ain/`.24- Exposes AICore-side Ain one-sided communication interfaces, covering `Put`, `PutValue`, `Get`, `Signal`, `ReadSignal`, `WaitSignal`, `Flush`, `FlushAsync`, `Wait`, and the `AinBarrierSession` collective synchronization primitive. Core implementations are located under `src/aicore/ain/`.
25-- Delivers Hcomm UT projects covering ordinary RoCE/URMA interfaces and UBC_CTP batch interfaces for `ascend950pr_9599_AIV`, as well as basic interface test cases for `ascend910B1_AIC`.25+- Delivers Hcomm UT projects covering ordinary RoCE/URMA interfaces and UB_CTP batch interfaces for `ascend950pr_9599_AIV`, as well as basic interface test cases for `ascend910B1_AIC`.
26- Delivers Ain UT project covering `Put`/`Get`/`Signal`/`ReadSignal`/`WaitSignal`/`BarrierSession` test cases on the `ascend950pr_9599_AIV` URMA path.26- Delivers Ain UT project covering `Put`/`Get`/`Signal`/`ReadSignal`/`WaitSignal`/`BarrierSession` test cases on the `ascend950pr_9599_AIV` URMA path.
27- Supplies the `hcomm_write_read_nbi` sample, demonstrating the point-to-point communication workflow of `WriteNbi` and `ReadNbi` under the AIV direct-driven URMA scenario, including Host-side resource preparation required to run the sample.27- Supplies the `hcomm_write_read_nbi` sample, demonstrating the point-to-point communication workflow of `WriteNbi` and `ReadNbi` under the AIV direct-driven URMA scenario, including Host-side resource preparation required to run the sample.
28- Provides SIMT URMA `WriteNbi`, `WriteValueNbi`, `ReadNbi`, `WriteWithNotifyNbi`, `AtomicFAA`, `AtomicCAS`, and `Drain`, together with the `simt_urma` functional sample and the `simt_urma_perftest` performance sample.28- Provides SIMT URMA `WriteNbi`, `WriteValueNbi`, `ReadNbi`, `WriteWithNotifyNbi`, `AtomicFAA`, `AtomicCAS`, and `Drain`, together with the `simt_urma` functional sample and the `simt_urma_perftest` performance sample.
@@ -39,18 +39,18 @@ For detailed information on all historical releases and updates, please refer to
39 39 
40asc-comm is an open-source repository targeting communication scenarios on Ascend AI Processors. It hosts publicly exposed AICore APIs, AIV direct-drive device-side implementations, API documentation, samples and verification suites.40asc-comm is an open-source repository targeting communication scenarios on Ascend AI Processors. It hosts publicly exposed AICore APIs, AIV direct-drive device-side implementations, API documentation, samples and verification suites.
41 41 
42-The public capabilities include `AscendC::Hcomm` point-to-point communication and `AscendC::Ain` one-sided communication, targeting communication data paths on the operator Kernel side. For Hcomm, users select a communication protocol through the `AscendC::Hcomm` template. Ordinary interfaces submit tasks individually through a `ChannelHandle`; the Ascend 950 UBC_CTP path can also use a BatchHandle to add multiple communication tasks and submit them together through `BatchCommit`. The corresponding `Drain` overload manages completion for each workflow. For Ain, users issue one-sided `Put`/`Get`/`Signal` operations on symmetric windows via the `AscendC::Ain` template, and manage completion through `Flush` or `FlushAsync` + `Wait`.42+The public capabilities include `AscendC::Hcomm` point-to-point communication and `AscendC::Ain` one-sided communication, targeting communication data paths on the operator Kernel side. For Hcomm, users select a communication protocol through the `AscendC::Hcomm` template. Ordinary interfaces submit tasks individually through a `ChannelHandle`; the Ascend 950 UB_CTP path can also use a BatchHandle to add multiple communication tasks and submit them together through `BatchCommit`. The corresponding `Drain` overload manages completion for each workflow. For Ain, users issue one-sided `Put`/`Get`/`Signal` operations on symmetric windows via the `AscendC::Ain` template, and manage completion through `Flush` or `FlushAsync` + `Wait`.
43 43 
44### Data Plane Capabilities44### Data Plane Capabilities
45 45 
46| Capability | Status |46| Capability | Status |
47| --- | --- |47| --- | --- |
48-| Public AICore Hcomm Interfaces | Ordinary Kernel-side `Init`, read/write, write-with-notify, atomic, `Commit`, and `Drain` interfaces are available. The Ascend 950 UBC_CTP path also provides `MakeBatchHandle`, batch `ReadNbi`/`WriteNbi`/`WriteWithNotifyNbi`, `BatchCommit`, and batch `Drain`. |48+| Public AICore Hcomm Interfaces | Ordinary Kernel-side `Init`, read/write, write-with-notify, atomic, `Commit`, and `Drain` interfaces are available. The Ascend 950 UB_CTP path also provides `MakeBatchHandle`, batch `ReadNbi`/`WriteNbi`/`WriteWithNotifyNbi`, `BatchCommit`, and batch `Drain`. |
49| Public AICore Ain Interfaces | Kernel-side `Put`, `PutValue`, `Get`, `Signal`, `ReadSignal`, `WaitSignal`, `Flush`, `FlushAsync`, `Wait`, and `AinBarrierSession` synchronization primitive available. |49| Public AICore Ain Interfaces | Kernel-side `Put`, `PutValue`, `Get`, `Signal`, `ReadSignal`, `WaitSignal`, `Flush`, `FlushAsync`, `Wait`, and `AinBarrierSession` synchronization primitive available. |
50-| AIV Direct Drive Implementation | Implementations for Hcomm RoCE and UBC_CTP/URMA are provided; core code resides in `src/aicore/hcomm/`. Ain implementation resides in `src/aicore/ain/`. |50+| AIV Direct Drive Implementation | Implementations for Hcomm RoCE and UB_CTP/URMA are provided; core code resides in `src/aicore/hcomm/`. Ain implementation resides in `src/aicore/ain/`. |
51| AIV Direct-drive Sample Supporting Workflow | `hcomm_write_read_nbi` includes communication domain creation, communication memory registration, P2P channel creation and remote memory acquisition required for AIV direct-driven URMA communication. |51| AIV Direct-drive Sample Supporting Workflow | `hcomm_write_read_nbi` includes communication domain creation, communication memory registration, P2P channel creation and remote memory acquisition required for AIV direct-driven URMA communication. |
52-| Protocol Features | `COMM_PROTOCOL_ROCE`: ordinary read/write, commit and wait; `COMM_PROTOCOL_UBC_CTP`: ordinary read/write, write-with-notify, atomic operations, commit and wait, with batch read/write, write-with-notify, commit and wait additionally supported on Ascend 950. |52+| Protocol Features | `COMM_PROTOCOL_ROCE`: ordinary read/write, commit and wait; `COMM_PROTOCOL_UB_CTP`: ordinary read/write, write-with-notify, atomic operations, commit and wait, with batch read/write, write-with-notify, commit and wait additionally supported on Ascend 950. |
53-| UT Verification | UTs cover ordinary Hcomm RoCE/URMA interfaces, UBC_CTP batch interfaces, and the Ain URMA path on `ascend950pr_9599_AIV`, plus basic interface cases for `ascend910B1_AIC`. |53+| UT Verification | UTs cover ordinary Hcomm RoCE/URMA interfaces, UB_CTP batch interfaces, and the Ain URMA path on `ascend950pr_9599_AIV`, plus basic interface cases for `ascend910B1_AIC`. |
54| AIV Direct-drive Samples | `hcomm_write_read_nbi` demonstrates symmetric two-card AIV direct-driven URMA `WriteNbi`/`ReadNbi` communication and result validation. |54| AIV Direct-drive Samples | `hcomm_write_read_nbi` demonstrates symmetric two-card AIV direct-driven URMA `WriteNbi`/`ReadNbi` communication and result validation. |
55| SIMT URMA Interfaces | Provides `WriteNbi`, `WriteValueNbi`, `ReadNbi`, `WriteWithNotifyNbi`, `AtomicFAA`, `AtomicCAS`, and `Drain`; deferred tasks are published by a subsequent `commit=true` task. |55| SIMT URMA Interfaces | Provides `WriteNbi`, `WriteValueNbi`, `ReadNbi`, `WriteWithNotifyNbi`, `AtomicFAA`, `AtomicCAS`, and `Drain`; deferred tasks are published by a subsequent `commit=true` task. |
56| SIMT URMA Samples | `simt_urma` covers isolated operations, serialized submission, and batch-last submission across all five interfaces; `simt_urma_perftest` reports issue latency and completion bandwidth. |56| SIMT URMA Samples | `simt_urma` covers isolated operations, serialized submission, and batch-last submission across all five interfaces; `simt_urma_perftest` reports issue latency and completion bandwidth. |
@@ -69,7 +69,7 @@ Ordinary interface workflow:
694. If `commit = false` is set during task submission, invoke `Commit` to explicitly submit pending communication tasks.694. If `commit = false` is set during task submission, invoke `Commit` to explicitly submit pending communication tasks.
705. Call `Drain` to wait for all communication tasks on the channel to complete.705. Call `Drain` to wait for all communication tasks on the channel to complete.
71 71 
72-Ascend 950 UBC_CTP batch interface workflow:72+Ascend 950 UB_CTP batch interface workflow:
73 73 
741. Prepare a UB workspace and create a batch handle through `MakeBatchHandle`. This workflow does not depend on `Init`.741. Prepare a UB workspace and create a batch handle through `MakeBatchHandle`. This workflow does not depend on `Init`.
752. Use the BatchHandle overloads of `ReadNbi`, `WriteNbi`, or `WriteWithNotifyNbi` to add tasks to the current batch. The three task types can be mixed in one batch.752. Use the BatchHandle overloads of `ReadNbi`, `WriteNbi`, or `WriteWithNotifyNbi` to add tasks to the current batch. The three task types can be mixed in one batch.
@@ -82,7 +82,7 @@ Protocol capability matrix:
82| Protocol | Capability Description |82| Protocol | Capability Description |
83| --- | --- |83| --- | --- |
84| `COMM_PROTOCOL_ROCE` | RoCE point-to-point path. Supports ordinary `ReadNbi`, `WriteNbi`, `Commit`, and `Drain`. `WriteWithNotifyNbi` and BatchHandle interfaces are not supported. |84| `COMM_PROTOCOL_ROCE` | RoCE point-to-point path. Supports ordinary `ReadNbi`, `WriteNbi`, `Commit`, and `Drain`. `WriteWithNotifyNbi` and BatchHandle interfaces are not supported. |
85-| `COMM_PROTOCOL_UBC_CTP` | UBC CTP/URMA point-to-point path. Supports ordinary `ReadNbi`, `WriteNbi`, `WriteWithNotifyNbi`, `AtomicFAA`, `AtomicCAS`, `Commit`, and `Drain`; BatchHandle interfaces are additionally supported on Ascend 950. |85+| `COMM_PROTOCOL_UB_CTP` | UBC CTP/URMA point-to-point path. Supports ordinary `ReadNbi`, `WriteNbi`, `WriteWithNotifyNbi`, `AtomicFAA`, `AtomicCAS`, `Commit`, and `Drain`; BatchHandle interfaces are additionally supported on Ascend 950. |
86 86 
87Refer to [Hcomm Usage Guide](./docs/en/guide/hcomm_usage.md) and [API Reference](./docs/en/api/README.md) for detailed parameter constraints and return value descriptions.87Refer to [Hcomm Usage Guide](./docs/en/guide/hcomm_usage.md) and [API Reference](./docs/en/api/README.md) for detailed parameter constraints and return value descriptions.
88 88 
Mexamples/ain/basic_ring/README.md+2-2
@@ -12,7 +12,7 @@ Host侧负责内存申请/初始化HCCL通信域/创建HCCL Team/注册对称win
12| --- | --- |12| --- | --- |
13| 产品 | `Ascend 950PR / Ascend 950DT` |13| 产品 | `Ascend 950PR / Ascend 950DT` |
14| NPU架构 | `dav-3510` |14| NPU架构 | `dav-3510` |
15-| 通信协议 | `COMM_PROTOCOL_UBC_CTP` |15+| 通信协议 | `COMM_PROTOCOL_UB_CTP` |
16| 通信引擎 | `COMM_ENGINE_AIV` |16| 通信引擎 | `COMM_ENGINE_AIV` |
17| 部署形态 | 单机多卡 |17| 部署形态 | 单机多卡 |
18| CANN包 | 使用当前环境中`set_env.sh`指向的CANN包 |18| CANN包 | 使用当前环境中`set_env.sh`指向的CANN包 |
@@ -38,7 +38,7 @@ basic_ring
382. 通过`HcclGetRootInfo`和`HcclCommInitRootInfo`创建多rank HCCL通信域。382. 通过`HcclGetRootInfo`和`HcclCommInitRootInfo`创建多rank HCCL通信域。
393. 配置`barrierCount`并调用`HcclWorldTeamCreate`创建world team。393. 配置`barrierCount`并调用`HcclWorldTeamCreate`创建world team。
404. 分别将`sendBuf`和`recvBuf`通过`HcclTeamWindowRegister`注册为对称window。404. 分别将`sendBuf`和`recvBuf`通过`HcclTeamWindowRegister`注册为对称window。
41-5. 调用`HcclTeamChannelsCreate`创建AIV + UBC_CTP通信channel。41+5. 调用`HcclTeamChannelsCreate`创建AIV + UB_CTP通信channel。
426. 下发`worldTeam`、`sendWin`、`recvWin`到Kernel。426. 下发`worldTeam`、`sendWin`、`recvWin`到Kernel。
43 43 
44### Kernel侧AIN通信44### Kernel侧AIN通信
Mexamples/ain/basic_ring/README_en.md+2-2
@@ -12,7 +12,7 @@ The Host side allocates memory, initializes the HCCL communicator, creates the H
12| --- | --- |12| --- | --- |
13| Product | `Ascend 950PR / Ascend 950DT` |13| Product | `Ascend 950PR / Ascend 950DT` |
14| NPU architecture | `dav-3510` |14| NPU architecture | `dav-3510` |
15-| Communication protocol | `COMM_PROTOCOL_UBC_CTP` |15+| Communication protocol | `COMM_PROTOCOL_UB_CTP` |
Y
Yyanqingshang9月14日
已过期

改名字的原因？

likedislike
16| Communication engine | `COMM_ENGINE_AIV` |16| Communication engine | `COMM_ENGINE_AIV` |
17| Deployment mode | Single-node multi-card |17| Deployment mode | Single-node multi-card |
18| CANN package | The CANN package selected by the current `set_env.sh` environment |18| CANN package | The CANN package selected by the current `set_env.sh` environment |
@@ -38,7 +38,7 @@ basic_ring
382. Create the multi-rank HCCL communicator through `HcclGetRootInfo` and `HcclCommInitRootInfo`.382. Create the multi-rank HCCL communicator through `HcclGetRootInfo` and `HcclCommInitRootInfo`.
393. Configure `barrierCount` and call `HcclWorldTeamCreate` to create the world team.393. Configure `barrierCount` and call `HcclWorldTeamCreate` to create the world team.
404. Register `sendBuf` and `recvBuf` as symmetric windows through `HcclTeamWindowRegister`.404. Register `sendBuf` and `recvBuf` as symmetric windows through `HcclTeamWindowRegister`.
41-5. Call `HcclTeamChannelsCreate` to create AIV + UBC_CTP communication channels.41+5. Call `HcclTeamChannelsCreate` to create AIV + UB_CTP communication channels.
426. Pass `worldTeam`, `sendWin`, and `recvWin` to the Kernel.426. Pass `worldTeam`, `sendWin`, and `recvWin` to the Kernel.
43 43 
44### Kernel-Side AIN Communication44### Kernel-Side AIN Communication
Mexamples/ain/basic_ring/basic_ring.asc+1-1
@@ -227,7 +227,7 @@ int32_t main(int32_t argc, char* argv[])
227 desc.netLayer = 0;227 desc.netLayer = 0;
228 desc.requirement.barrierCount = 1;228 desc.requirement.barrierCount = 1;
229 desc.engine = COMM_ENGINE_AIV;229 desc.engine = COMM_ENGINE_AIV;
230- desc.protocol = COMM_PROTOCOL_UBC_CTP;230+ desc.protocol = COMM_PROTOCOL_UB_CTP;
231 desc.channelCnt = 1;231 desc.channelCnt = 1;
232 HcommTeamHandle team{nullptr};232 HcommTeamHandle team{nullptr};
233 HCCL_CHECK(HcclTeamCreate(hcclComm, &desc, &team));233 HCCL_CHECK(HcclTeamCreate(hcclComm, &desc, &team));
Mexamples/hcomm_batch_write/hcomm_batch_write.asc+3-3
@@ -281,7 +281,7 @@ int32_t PrepareMemory(RankResources& resources, std::vector<uint64_t>& remoteBuf
281const CommLink* FindUbcCtpLink(const CommLink* links, uint32_t linkNum)281const CommLink* FindUbcCtpLink(const CommLink* links, uint32_t linkNum)
282{282{
283 for (uint32_t index = 0U; index < linkNum; ++index) {283 for (uint32_t index = 0U; index < linkNum; ++index) {
284- if (links[index].linkAttr.linkProtocol == COMM_PROTOCOL_UBC_CTP) {284+ if (links[index].linkAttr.linkProtocol == COMM_PROTOCOL_UB_CTP) {
285 return &links[index];285 return &links[index];
286 }286 }
287 }287 }
@@ -311,7 +311,7 @@ int32_t AddPeerToGroup(
311 HcclChannelDesc desc{};311 HcclChannelDesc desc{};
312 CHECK_RESULT(HcclChannelDescInit(&desc, 1U), HCCL_SUCCESS, resources.rank);312 CHECK_RESULT(HcclChannelDescInit(&desc, 1U), HCCL_SUCCESS, resources.rank);
313 desc.remoteRank = peerRank;313 desc.remoteRank = peerRank;
314- desc.channelProtocol = COMM_PROTOCOL_UBC_CTP;314+ desc.channelProtocol = COMM_PROTOCOL_UB_CTP;
315 desc.localEndpoint = link.srcEndpointDesc;315 desc.localEndpoint = link.srcEndpointDesc;
316 desc.remoteEndpoint = link.dstEndpointDesc;316 desc.remoteEndpoint = link.dstEndpointDesc;
317 desc.memHandles = &resources.memHandle;317 desc.memHandles = &resources.memHandle;
@@ -355,7 +355,7 @@ int32_t BuildEndpointGroups(RankResources& resources, std::vector<EndpointGroup>
355 break;355 break;
356 }356 }
357 if (!found) {357 if (!found) {
358- std::fprintf(stderr, "[ERROR] rank %u: no UBC_CTP link to rank %u\n", resources.rank, peerRank);358+ std::fprintf(stderr, "[ERROR] rank %u: no UB_CTP link to rank %u\n", resources.rank, peerRank);
359 return FAILURE;359 return FAILURE;
360 }360 }
361 }361 }
Mexamples/hcomm_batch_write/hcomm_batch_write_kernel.cpp+1-1
@@ -16,7 +16,7 @@
16namespace HcommBatchWriteExample {16namespace HcommBatchWriteExample {
17 17 
18class KernelHcommBatchWrite {18class KernelHcommBatchWrite {
19- using HcommType = AscendC::Hcomm<AscendC::COMM_PROTOCOL_UBC_CTP>;19+ using HcommType = AscendC::Hcomm<AscendC::COMM_PROTOCOL_UB_CTP>;
20 20 
21public:21public:
22 __aicore__ inline void Init(GM_ADDR context, AscendC::TPipe* pipe)22 __aicore__ inline void Init(GM_ADDR context, AscendC::TPipe* pipe)
Mexamples/hcomm_write_read_nbi/README.md+2-2
@@ -44,7 +44,7 @@
443. **注册通信内存**：调用`HcclCommMemReg`向通信域注册本卡的通信buffer，Channel创建时该内存信息会自动交换给对端。443. **注册通信内存**：调用`HcclCommMemReg`向通信域注册本卡的通信buffer，Channel创建时该内存信息会自动交换给对端。
454. **建立TCP环形拓扑**：每个rank监听`BASE_PORT + rank`，主动连接`next = (rank + 1) % nranks`，同时接受来自`prev = (rank - 1 + nranks) % nranks`的连接。该环形连接用于RootInfo交换后的Host侧barrier，确保各rank在关键阶段同步推进。454. **建立TCP环形拓扑**：每个rank监听`BASE_PORT + rank`，主动连接`next = (rank + 1) % nranks`，同时接受来自`prev = (rank - 1 + nranks) % nranks`的连接。该环形连接用于RootInfo交换后的Host侧barrier，确保各rank在关键阶段同步推进。
465. **获取链路Endpoint**：通过`HcclRankGraphGetLayers`和`HcclRankGraphGetLinks`分别获取本Rank到`prev`和`next`的物理链路Endpoint信息。465. **获取链路Endpoint**：通过`HcclRankGraphGetLayers`和`HcclRankGraphGetLinks`分别获取本Rank到`prev`和`next`的物理链路Endpoint信息。
47-6. **创建P2P通道（AIV直驱）**：调用`HcclChannelAcquire`创建到相邻rank的P2P通道。此处需明确指定引擎为`COMM_ENGINE_AIV`、协议为`COMM_PROTOCOL_UBC_CTP`（URMA协议），并传入待交换的内存句柄。47+6. **创建P2P通道（AIV直驱）**：调用`HcclChannelAcquire`创建到相邻rank的P2P通道。此处需明确指定引擎为`COMM_ENGINE_AIV`、协议为`COMM_PROTOCOL_UB_CTP`（URMA协议），并传入待交换的内存句柄。
487. **获取对端内存地址**：调用`HcclChannelGetRemoteMems`获取相邻rank注册的内存地址，作为Kernel侧`WriteNbi`/`ReadNbi`的远端目标地址。487. **获取对端内存地址**：调用`HcclChannelGetRemoteMems`获取相邻rank注册的内存地址，作为Kernel侧`WriteNbi`/`ReadNbi`的远端目标地址。
498. **下发Context**：Host预初始化seg0（填充基于rankId的伪随机pattern），将`ChannelHandle`和buffer地址封装到`CommContext`并下发到各卡GM。498. **下发Context**：Host预初始化seg0（填充基于rankId的伪随机pattern），将`ChannelHandle`和buffer地址封装到`CommContext`并下发到各卡GM。
50 50 
@@ -63,7 +63,7 @@ HcclRankGraphGetLinks(comm, layerId, rank, peerRank, &links, &linkNum);
63 63 
64// 4. 创建AIV直驱URMA P2P通道64// 4. 创建AIV直驱URMA P2P通道
65channelDesc.remoteRank = peerRank;65channelDesc.remoteRank = peerRank;
66-channelDesc.channelProtocol = COMM_PROTOCOL_UBC_CTP; // URMA协议66+channelDesc.channelProtocol = COMM_PROTOCOL_UB_CTP; // URMA协议
67channelDesc.memHandles = &memHandle;67channelDesc.memHandles = &memHandle;
68channelDesc.memHandleNum = 1;68channelDesc.memHandleNum = 1;
69HcclChannelAcquire(comm, COMM_ENGINE_AIV, &channelDesc, 1, &channel); // 指定COMM_ENGINE_AIV69HcclChannelAcquire(comm, COMM_ENGINE_AIV, &channelDesc, 1, &channel); // 指定COMM_ENGINE_AIV
Mexamples/hcomm_write_read_nbi/README_en.md+2-2
@@ -44,7 +44,7 @@ On the Ascend 950 series, the communication domain must be created in a multi-pr
443. **Register Communication Memory**: Call `HcclCommMemReg` to register the local communication buffer with the communication domain. This memory information is automatically exchanged with the peer during channel creation.443. **Register Communication Memory**: Call `HcclCommMemReg` to register the local communication buffer with the communication domain. This memory information is automatically exchanged with the peer during channel creation.
454. **Build the TCP Ring Topology**: Each rank listens on `BASE_PORT + rank`, actively connects to `next = (rank + 1) % nranks`, and accepts the connection from `prev = (rank - 1 + nranks) % nranks`. This ring is used for Host-side barriers after RootInfo exchange, ensuring that all ranks advance through key phases together.454. **Build the TCP Ring Topology**: Each rank listens on `BASE_PORT + rank`, actively connects to `next = (rank + 1) % nranks`, and accepts the connection from `prev = (rank - 1 + nranks) % nranks`. This ring is used for Host-side barriers after RootInfo exchange, ensuring that all ranks advance through key phases together.
465. **Obtain Link Endpoints**: Use `HcclRankGraphGetLayers` and `HcclRankGraphGetLinks` to obtain physical link endpoint information from the local rank to both `prev` and `next`.465. **Obtain Link Endpoints**: Use `HcclRankGraphGetLayers` and `HcclRankGraphGetLinks` to obtain physical link endpoint information from the local rank to both `prev` and `next`.
47-6. **Acquire P2P Channels (AIV Direct-Drive)**: Call `HcclChannelAcquire` to create P2P channels to neighboring ranks. Specify `COMM_ENGINE_AIV` as the engine and `COMM_PROTOCOL_UBC_CTP` as the URMA protocol, and pass the memory handles to be exchanged.47+6. **Acquire P2P Channels (AIV Direct-Drive)**: Call `HcclChannelAcquire` to create P2P channels to neighboring ranks. Specify `COMM_ENGINE_AIV` as the engine and `COMM_PROTOCOL_UB_CTP` as the URMA protocol, and pass the memory handles to be exchanged.
487. **Obtain Remote Memory Address**: Call `HcclChannelGetRemoteMems` to retrieve the memory addresses registered by neighboring ranks, which serve as remote target addresses for `WriteNbi`/`ReadNbi` in the Kernel.487. **Obtain Remote Memory Address**: Call `HcclChannelGetRemoteMems` to retrieve the memory addresses registered by neighboring ranks, which serve as remote target addresses for `WriteNbi`/`ReadNbi` in the Kernel.
498. **Download Context**: The Host pre-initializes seg0 (filling it with a pseudo-random pattern based on `rankId`), encapsulates the `ChannelHandle` and buffer addresses into `CommContext`, and downloads it to the GM of each card.498. **Download Context**: The Host pre-initializes seg0 (filling it with a pseudo-random pattern based on `rankId`), encapsulates the `ChannelHandle` and buffer addresses into `CommContext`, and downloads it to the GM of each card.
50 50 
@@ -63,7 +63,7 @@ HcclRankGraphGetLinks(comm, layerId, rank, peerRank, &links, &linkNum);
63 63 
64// 4. Acquire AIV Direct-Drive URMA P2P Channel64// 4. Acquire AIV Direct-Drive URMA P2P Channel
65channelDesc.remoteRank = peerRank;65channelDesc.remoteRank = peerRank;
66-channelDesc.channelProtocol = COMM_PROTOCOL_UBC_CTP; // URMA protocol66+channelDesc.channelProtocol = COMM_PROTOCOL_UB_CTP; // URMA protocol
67channelDesc.memHandles = &memHandle;67channelDesc.memHandles = &memHandle;
68channelDesc.memHandleNum = 1;68channelDesc.memHandleNum = 1;
69HcclChannelAcquire(comm, COMM_ENGINE_AIV, &channelDesc, 1, &channel); // Specify COMM_ENGINE_AIV69HcclChannelAcquire(comm, COMM_ENGINE_AIV, &channelDesc, 1, &channel); // Specify COMM_ENGINE_AIV
Mexamples/hcomm_write_read_nbi/hcomm_rw_def.h+2-2
@@ -26,8 +26,8 @@ constexpr uint64_t READ_RESULT_OFFSET = 2U * DATA_SIZE;
26constexpr uint32_t NRANKS = 2U;26constexpr uint32_t NRANKS = 2U;
27constexpr uint16_t BASE_PORT = 29620U;27constexpr uint16_t BASE_PORT = 29620U;
28constexpr uint32_t ROOT_SERVER_RANK = 0U;28constexpr uint32_t ROOT_SERVER_RANK = 0U;
29-constexpr CommProtocol HOST_COMM_PROTOCOL = COMM_PROTOCOL_UBC_CTP;29+constexpr CommProtocol HOST_COMM_PROTOCOL = COMM_PROTOCOL_UB_CTP;
30-constexpr AscendC::CommProtocol KERNEL_COMM_PROTOCOL = AscendC::COMM_PROTOCOL_UBC_CTP;30+constexpr AscendC::CommProtocol KERNEL_COMM_PROTOCOL = AscendC::COMM_PROTOCOL_UB_CTP;
31static_assert(31static_assert(
32 static_cast<int32_t>(HOST_COMM_PROTOCOL) == static_cast<int32_t>(KERNEL_COMM_PROTOCOL),32 static_cast<int32_t>(HOST_COMM_PROTOCOL) == static_cast<int32_t>(KERNEL_COMM_PROTOCOL),
33 "Host and Kernel communication protocols must match");33 "Host and Kernel communication protocols must match");
Mexamples/simt_urma/main.cpp+3-3
@@ -67,8 +67,8 @@ struct PeerRankCtx {
67constexpr uint32_t kBarrierWaitSeconds = 60;67constexpr uint32_t kBarrierWaitSeconds = 60;
68constexpr uint32_t kBarrierPollMs = 100;68constexpr uint32_t kBarrierPollMs = 100;
69 69 
70-// SIMT接口只在UBC_CTP/URMA协议上实现，其余链路协议无对应实现。70+// SIMT接口只在UB_CTP/URMA协议上实现，其余链路协议无对应实现。
71-constexpr CommProtocol kTargetCommProtocol = COMM_PROTOCOL_UBC_CTP;71+constexpr CommProtocol kTargetCommProtocol = COMM_PROTOCOL_UB_CTP;
72 72 
73// 两块内存注册到通信域时使用的tag。两个rank使用相同tag，远端内存才能按tag查回。73// 两块内存注册到通信域时使用的tag。两个rank使用相同tag，远端内存才能按tag查回。
74constexpr const char* kSendBufTag = "simtUrmaSendBuf";74constexpr const char* kSendBufTag = "simtUrmaSendBuf";
@@ -333,7 +333,7 @@ HcclResult AcquirePeerChannel(
333 }333 }
334 }334 }
335 if (!linkFound) {335 if (!linkFound) {
336- std::cout << "[rank " << rank << "] no UBC_CTP link to peer " << peer.rankId336+ std::cout << "[rank " << rank << "] no UB_CTP link to peer " << peer.rankId
337 << ", SIMT URMA interfaces require the URMA path" << std::endl;337 << ", SIMT URMA interfaces require the URMA path" << std::endl;
338 return HCCL_E_NOT_SUPPORT;338 return HCCL_E_NOT_SUPPORT;
339 }339 }
Mexamples/simt_urma_perftest/main.cpp+2-2
@@ -60,7 +60,7 @@ using namespace simt_urma_perftest;
60 60 
61constexpr uint32_t kBarrierWaitSeconds = 60U;61constexpr uint32_t kBarrierWaitSeconds = 60U;
62constexpr uint32_t kBarrierPollMs = 100U;62constexpr uint32_t kBarrierPollMs = 100U;
63-constexpr CommProtocol kTargetCommProtocol = COMM_PROTOCOL_UBC_CTP;63+constexpr CommProtocol kTargetCommProtocol = COMM_PROTOCOL_UB_CTP;
64constexpr const char* kSendBufTag = "simtUrmaPerfSendBuf";64constexpr const char* kSendBufTag = "simtUrmaPerfSendBuf";
65constexpr const char* kRecvBufTag = "simtUrmaPerfRecvBuf";65constexpr const char* kRecvBufTag = "simtUrmaPerfRecvBuf";
66 66 
@@ -270,7 +270,7 @@ HcclResult AcquirePeerChannel(
270 }270 }
271 }271 }
272 if (!found) {272 if (!found) {
273- std::cout << "no UBC_CTP link to peer " << peerRank << ", SIMT requires the URMA path" << std::endl;273+ std::cout << "no UB_CTP link to peer " << peerRank << ", SIMT requires the URMA path" << std::endl;
274 return HCCL_E_NOT_SUPPORT;274 return HCCL_E_NOT_SUPPORT;
275 }275 }
276 HCCLCHECK(HcclChannelAcquire(comm, COMM_ENGINE_AIV, &desc, 1U, &channel));276 HCCLCHECK(HcclChannelAcquire(comm, COMM_ENGINE_AIV, &desc, 1U, &channel));
Minclude/aicore/hcomm/hcomm.h+7-7
@@ -40,10 +40,10 @@ namespace AscendC {
40 * 4) If commit is false when launching task, call the Commit interface to notify the execution of the40 * 4) If commit is false when launching task, call the Commit interface to notify the execution of the
41 * corresponding comm task.41 * corresponding comm task.
42 * 5) Call the Drain interface (blocking) to wait for the server to complete the corresponding comm task.42 * 5) Call the Drain interface (blocking) to wait for the server to complete the corresponding comm task.
43- * @tparam commProtocol: The communication protocol to use. COMM_PROTOCOL_UBC_CTP (implemented through URMA) is used43+ * @tparam commProtocol: The communication protocol to use. COMM_PROTOCOL_UB_CTP (implemented through URMA) is used
44 * by default.44 * by default.
45 */45 */
46-template <CommProtocol commProtocol = COMM_PROTOCOL_UBC_CTP>46+template <CommProtocol commProtocol = COMM_PROTOCOL_UB_CTP>
47class Hcomm {47class Hcomm {
48public:48public:
49 /*!49 /*!
@@ -196,7 +196,7 @@ public:
196 * @param [in] src: The local source address of the reduction.196 * @param [in] src: The local source address of the reduction.
197 * @param [in] count: The number of elements to reduce.197 * @param [in] count: The number of elements to reduce.
198 * @return 0 indicates success and -1 indicates failure.198 * @return 0 indicates success and -1 indicates failure.
199- * @note Only the UBC_CTP/URMA path supports this interface.199+ * @note Only the UB_CTP/URMA path supports this interface.
200 */200 */
201 template <201 template <
202 typename T, HcommUrmaReduceOp reduceOp, bool commit = true, pipe_t commitPipe = PIPE_S,202 typename T, HcommUrmaReduceOp reduceOp, bool commit = true, pipe_t commitPipe = PIPE_S,
@@ -386,7 +386,7 @@ public:
386 * @brief Block Aicore and drain comm tasks submitted on channel until finish processing.386 * @brief Block Aicore and drain comm tasks submitted on channel until finish processing.
387 * @tparam pipe: The pipe type to use for drain, PIPE_MTE3 supported as default.387 * @tparam pipe: The pipe type to use for drain, PIPE_MTE3 supported as default.
388 * @param [in] channel: The handle of the communication channel.388 * @param [in] channel: The handle of the communication channel.
389- * @return 0 indicates success. A non-zero value indicates failure. For COMM_PROTOCOL_UBC_CTP, the underlying389+ * @return 0 indicates success. A non-zero value indicates failure. For COMM_PROTOCOL_UB_CTP, the underlying
390 * CQ polling error code is returned directly.390 * CQ polling error code is returned directly.
391 */391 */
392 template <pipe_t pipe = PIPE_MTE3>392 template <pipe_t pipe = PIPE_MTE3>
@@ -397,7 +397,7 @@ public:
397 * @tparam pipe: The pipe type to use for drain, PIPE_MTE3 supported as default.397 * @tparam pipe: The pipe type to use for drain, PIPE_MTE3 supported as default.
398 * @tparam T: The batch handle type.398 * @tparam T: The batch handle type.
399 * @param [in,out] batchHandle: The batch handle whose generated completion records are awaited.399 * @param [in,out] batchHandle: The batch handle whose generated completion records are awaited.
400- * @return 0 indicates success. A non-zero value indicates failure. For COMM_PROTOCOL_UBC_CTP, 0xFF indicates a400+ * @return 0 indicates success. A non-zero value indicates failure. For COMM_PROTOCOL_UB_CTP, 0xFF indicates a
401 * completion-record polling timeout; other positive values encode status and substatus.401 * completion-record polling timeout; other positive values encode status and substatus.
402 * @note This overload does not require Init. It must be called after all tasks in the current batch are submitted402 * @note This overload does not require Init. It must be called after all tasks in the current batch are submitted
403 * through BatchCommit. Multiple batches may be submitted before one Drain if channel capacity permits.403 * through BatchCommit. Multiple batches may be submitted before one Drain if channel capacity permits.
@@ -409,7 +409,7 @@ public:
409 * @brief Acquire the cross-AI-Core lock of a channel.409 * @brief Acquire the cross-AI-Core lock of a channel.
410 * @param [in] channel: The handle of the communication channel.410 * @param [in] channel: The handle of the communication channel.
411 * @return 0 indicates success and -1 indicates failure.411 * @return 0 indicates success and -1 indicates failure.
412- * @note This interface is supported only by COMM_PROTOCOL_UBC_CTP on Ascend 950. It blocks until the lock is412+ * @note This interface is supported only by COMM_PROTOCOL_UB_CTP on Ascend 950. It blocks until the lock is
413 * acquired and does not guarantee acquisition order among AI Cores. All accesses that update the channel413 * acquired and does not guarantee acquisition order among AI Cores. All accesses that update the channel
414 * state must be protected by Lock and Unlock.414 * state must be protected by Lock and Unlock.
415 */415 */
@@ -419,7 +419,7 @@ public:
419 * @brief Flush the channel state and release its cross-AI-Core lock.419 * @brief Flush the channel state and release its cross-AI-Core lock.
420 * @param [in] channel: The handle of the communication channel.420 * @param [in] channel: The handle of the communication channel.
421 * @return 0 indicates success and -1 indicates failure.421 * @return 0 indicates success and -1 indicates failure.
422- * @note This interface is supported only by COMM_PROTOCOL_UBC_CTP on Ascend 950. It must be called by the AI Core422+ * @note This interface is supported only by COMM_PROTOCOL_UB_CTP on Ascend 950. It must be called by the AI Core
423 * that successfully acquired the channel lock, after the last operation that updates the channel state.423 * that successfully acquired the channel lock, after the last operation that updates the channel state.
424 */424 */
425 __aicore__ inline int32_t Unlock(ChannelHandle channel);425 __aicore__ inline int32_t Unlock(ChannelHandle channel);
Minclude/aicore/hcomm/hcomm_common.h+13-10
@@ -32,16 +32,19 @@ struct BufDesc {
32 * @brief 通信协议类型枚举32 * @brief 通信协议类型枚举
33 */33 */
34typedef enum {34typedef enum {
35- COMM_PROTOCOL_RESERVED = -1, ///< 保留协议类型35+ COMM_PROTOCOL_RESERVED = -1, ///< 保留协议类型
36- COMM_PROTOCOL_HCCS = 0, ///< HCCS协议36+ COMM_PROTOCOL_HCCS = 0, ///< HCCS协议
37- COMM_PROTOCOL_ROCE = 1, ///< RDMA over Converged Ethernet37+ COMM_PROTOCOL_ROCE = 1, ///< RDMA over Converged Ethernet
38- COMM_PROTOCOL_PCIE = 2, ///< PCIE协议38+ COMM_PROTOCOL_PCIE = 2, ///< PCIE协议
39- COMM_PROTOCOL_SIO = 3, ///< SIO协议39+ COMM_PROTOCOL_SIO = 3, ///< SIO协议
40- COMM_PROTOCOL_UBC_CTP = 4, ///< 华为统一总线UBC_CTP40+ COMM_PROTOCOL_UB_CTP = 4, ///< 华为统一总线UB_CTP
41- COMM_PROTOCOL_UBC_TP = 5, ///< 华为统一总线UBC_TP41+ COMM_PROTOCOL_UBC_CTP = COMM_PROTOCOL_UB_CTP, ///< 兼容旧协议名UBC_CTP
42- COMM_PROTOCOL_UB_MEM = 6, ///< UB_MEM42+ COMM_PROTOCOL_UBC_TP = 5, ///< 华为统一总线UBC_TP
43- COMM_PROTOCOL_UBOE = 7, ///< UBoE43+ COMM_PROTOCOL_UB_MEM = 6, ///< UB_MEM
44- COMM_PROTOCOL_HCCS_ONLY = 8, ///< 一卡双DIE使用HCCS44+ COMM_PROTOCOL_UBOE = 7, ///< UBoE
45+ COMM_PROTOCOL_HCCS_ONLY = 8, ///< 一卡双DIE使用HCCS
46+ COMM_PROTOCOL_UB_RTP = 9, ///< UB_RTP
47+ COMM_PROTOCOL_UBG = COMM_PROTOCOL_UB_RTP, ///< 兼容旧协议名UBG
45} CommProtocol;48} CommProtocol;
46 49 
47enum class HcommUrmaReduceOp : uint32_t {50enum class HcommUrmaReduceOp : uint32_t {
Minclude/aicore/hcomm/hcomm_simt.h+3-3
@@ -42,7 +42,7 @@ struct HcommUnboundGroup {};
42 * 1) Create Hcomm object.42 * 1) Create Hcomm object.
43 * 2) Launch comm tasks asynchronously through the corresponding interface.43 * 2) Launch comm tasks asynchronously through the corresponding interface.
44 * 3) Call the Drain interface (blocking) to wait for completion of the comm tasks.44 * 3) Call the Drain interface (blocking) to wait for completion of the comm tasks.
45- * @tparam commProtocol: The communication protocol to use, UBC_CTP supported as default.45+ * @tparam commProtocol: The communication protocol to use, UB_CTP supported as default.
46 * @note Unlike the SIMD path, the doorbell is rung by copying a 128-byte DWQE rather than writing46 * @note Unlike the SIMD path, the doorbell is rung by copying a 128-byte DWQE rather than writing
47 * a scalar register. A deferred Write/Read occupies one SQ basic block, while an immediate47 * a scalar register. A deferred Write/Read occupies one SQ basic block, while an immediate
48 * Write/Read and the two-BB Notify/atomic WQEs occupy two.48 * Write/Read and the two-BB Notify/atomic WQEs occupy two.
@@ -63,7 +63,7 @@ struct HcommUnboundGroup {};
63 * keep their queue state in different places: SIMD uses the counters in ChannelEntity, SIMT63 * keep their queue state in different places: SIMD uses the counters in ChannelEntity, SIMT
64 * packs curHead and wqeCnt into the u64 at SqContext::ubJfs::headAddr.64 * packs curHead and wqeCnt into the u64 at SqContext::ubJfs::headAddr.
65 */65 */
66-template <CommProtocol commProtocol = COMM_PROTOCOL_UBC_CTP, typename Group = detail::HcommUnboundGroup>66+template <CommProtocol commProtocol = COMM_PROTOCOL_UB_CTP, typename Group = detail::HcommUnboundGroup>
67class Hcomm {67class Hcomm {
68public:68public:
69 __simt_callee__ inline Hcomm();69 __simt_callee__ inline Hcomm();
@@ -198,7 +198,7 @@ private:
198};198};
199 199 
200template <typename Group>200template <typename Group>
201-Hcomm(const Group&) -> Hcomm<COMM_PROTOCOL_UBC_CTP, Group>;201+Hcomm(const Group&) -> Hcomm<COMM_PROTOCOL_UB_CTP, Group>;
202 202 
203/*!203/*!
204 * @brief Resolve the base address of a locally registered buffer on the channel.204 * @brief Resolve the base address of a locally registered buffer on the channel.
Msrc/aicore/ain/impl/ain_impl_def.h+1-1
@@ -84,7 +84,7 @@ constexpr CommProtocol MaskToCommProtocol(unsigned commEngineMask)
84{84{
85 switch (commEngineMask) {85 switch (commEngineMask) {
86 case AIN_MASK_DEFAULT:86 case AIN_MASK_DEFAULT:
87- return COMM_PROTOCOL_UBC_CTP;87+ return COMM_PROTOCOL_UB_CTP;
88 default:88 default:
89 return COMM_PROTOCOL_RESERVED;89 return COMM_PROTOCOL_RESERVED;
90 }90 }
Msrc/aicore/hcomm/common/hcomm_simt_base.h+1-1
@@ -26,7 +26,7 @@
26 26 
27namespace AscendC::simt {27namespace AscendC::simt {
28 28 
29-// Primary template: every protocol without a specialization fails. COMM_PROTOCOL_UBC_CTP is29+// Primary template: every protocol without a specialization fails. COMM_PROTOCOL_UB_CTP is
30// specialized in impl/hcomm_simt_urma_def.h.30// specialized in impl/hcomm_simt_urma_def.h.
31template <CommProtocol commProtocol>31template <CommProtocol commProtocol>
32class HcommImpl {32class HcommImpl {
Msrc/aicore/hcomm/impl/hcomm_impl.h+3-3
@@ -49,7 +49,7 @@ template <typename T, typename U>
49__aicore__ inline BatchHandle<T> Hcomm<commProtocol>::MakeBatchHandle(49__aicore__ inline BatchHandle<T> Hcomm<commProtocol>::MakeBatchHandle(
50 T channel, const LocalTensor<U>& buff, uint32_t buffLen, GM_ADDR remoteAddr, GM_ADDR localAddr)50 T channel, const LocalTensor<U>& buff, uint32_t buffLen, GM_ADDR remoteAddr, GM_ADDR localAddr)
51{51{
52- static_assert(commProtocol == COMM_PROTOCOL_UBC_CTP, "BatchHandle only supports COMM_PROTOCOL_UBC_CTP");52+ static_assert(commProtocol == COMM_PROTOCOL_UB_CTP, "BatchHandle only supports COMM_PROTOCOL_UB_CTP");
53 auto batchHandle = impl_.MakeBatchHandle(channel, buff, buffLen, remoteAddr, localAddr);53 auto batchHandle = impl_.MakeBatchHandle(channel, buff, buffLen, remoteAddr, localAddr);
54 using ExpectedType = BatchHandle<T>;54 using ExpectedType = BatchHandle<T>;
55 static_assert(55 static_assert(
@@ -197,14 +197,14 @@ __aicore__ inline int32_t Hcomm<commProtocol>::Drain(T& batchHandle)
197template <CommProtocol commProtocol>197template <CommProtocol commProtocol>
198__aicore__ inline int32_t Hcomm<commProtocol>::Lock(ChannelHandle channel)198__aicore__ inline int32_t Hcomm<commProtocol>::Lock(ChannelHandle channel)
199{199{
200- static_assert(commProtocol == COMM_PROTOCOL_UBC_CTP, "Lock only supports COMM_PROTOCOL_UBC_CTP");200+ static_assert(commProtocol == COMM_PROTOCOL_UB_CTP, "Lock only supports COMM_PROTOCOL_UB_CTP");
201 return impl_.Lock(channel);201 return impl_.Lock(channel);
202}202}
203 203 
204template <CommProtocol commProtocol>204template <CommProtocol commProtocol>
205__aicore__ inline int32_t Hcomm<commProtocol>::Unlock(ChannelHandle channel)205__aicore__ inline int32_t Hcomm<commProtocol>::Unlock(ChannelHandle channel)
206{206{
207- static_assert(commProtocol == COMM_PROTOCOL_UBC_CTP, "Unlock only supports COMM_PROTOCOL_UBC_CTP");207+ static_assert(commProtocol == COMM_PROTOCOL_UB_CTP, "Unlock only supports COMM_PROTOCOL_UB_CTP");
208 return impl_.Unlock(channel);208 return impl_.Unlock(channel);
209}209}
210} // namespace AscendC210} // namespace AscendC
Msrc/aicore/hcomm/impl/platform_v310/hcomm_aiv_urma.h+37-38
@@ -324,11 +324,11 @@ __aicore__ inline void HcommUrmaDumpCqeCtx(__ubuf__ HcommUrmaJfcCqeCtx* cqeCtx)
324 cqeCtx->inlineData[1], cqeCtx->inlineData[2]);324 cqeCtx->inlineData[1], cqeCtx->inlineData[2]);
325}325}
326 326 
327-__aicore__ inline HcommImpl<COMM_PROTOCOL_UBC_CTP>::HcommImpl() {}327+__aicore__ inline HcommImpl<COMM_PROTOCOL_UB_CTP>::HcommImpl() {}
328 328 
329-__aicore__ inline HcommImpl<COMM_PROTOCOL_UBC_CTP>::~HcommImpl() {}329+__aicore__ inline HcommImpl<COMM_PROTOCOL_UB_CTP>::~HcommImpl() {}
330 330 
331-__aicore__ inline int32_t HcommImpl<COMM_PROTOCOL_UBC_CTP>::Init(__ubuf__ uint8_t* buff, uint32_t len)331+__aicore__ inline int32_t HcommImpl<COMM_PROTOCOL_UB_CTP>::Init(__ubuf__ uint8_t* buff, uint32_t len)
332{332{
333 if (len < HCOMM_URMA_TMP_BUF_SIZE) {333 if (len < HCOMM_URMA_TMP_BUF_SIZE) {
334 return HCOMM_FAILED;334 return HCOMM_FAILED;
@@ -348,7 +348,7 @@ __aicore__ inline int32_t HcommImpl<COMM_PROTOCOL_UBC_CTP>::Init(__ubuf__ uint8_
348}348}
349 349 
350template <typename T>350template <typename T>
351-__aicore__ inline int32_t HcommImpl<COMM_PROTOCOL_UBC_CTP>::Init(const LocalTensor<T>& buff, uint32_t len)351+__aicore__ inline int32_t HcommImpl<COMM_PROTOCOL_UB_CTP>::Init(const LocalTensor<T>& buff, uint32_t len)
352{352{
353 if (len < HCOMM_URMA_TMP_BUF_SIZE || len > buff.GetSize()) {353 if (len < HCOMM_URMA_TMP_BUF_SIZE || len > buff.GetSize()) {
354 return HCOMM_FAILED;354 return HCOMM_FAILED;
@@ -384,7 +384,7 @@ __aicore__ inline bool HcommUrmaResolveBatchRemote(
384}384}
385 385 
386template <typename U>386template <typename U>
387-__aicore__ inline UbcBatchHandle HcommImpl<COMM_PROTOCOL_UBC_CTP>::MakeBatchHandle(387+__aicore__ inline UbcBatchHandle HcommImpl<COMM_PROTOCOL_UB_CTP>::MakeBatchHandle(
388 ChannelHandle channel, const LocalTensor<U>& buff, uint32_t buffLen, GM_ADDR remoteAddr, GM_ADDR localAddr)388 ChannelHandle channel, const LocalTensor<U>& buff, uint32_t buffLen, GM_ADDR remoteAddr, GM_ADDR localAddr)
389{389{
390 (void)localAddr;390 (void)localAddr;
@@ -418,7 +418,7 @@ __aicore__ inline UbcBatchHandle HcommImpl<COMM_PROTOCOL_UBC_CTP>::MakeBatchHand
418}418}
419 419 
420template <typename U>420template <typename U>
421-__aicore__ inline UbcMultiBatchHandle HcommImpl<COMM_PROTOCOL_UBC_CTP>::MakeBatchHandle(421+__aicore__ inline UbcMultiBatchHandle HcommImpl<COMM_PROTOCOL_UB_CTP>::MakeBatchHandle(
422 MultiChannelHandle multiChannel, const LocalTensor<U>& buff, uint32_t buffLen, GM_ADDR remoteAddr,422 MultiChannelHandle multiChannel, const LocalTensor<U>& buff, uint32_t buffLen, GM_ADDR remoteAddr,
423 GM_ADDR localAddr)423 GM_ADDR localAddr)
424{424{
@@ -453,7 +453,7 @@ __aicore__ inline UbcMultiBatchHandle HcommImpl<COMM_PROTOCOL_UBC_CTP>::MakeBatc
453 return multiBatchHandle;453 return multiBatchHandle;
454}454}
455 455 
456-__aicore__ inline UbcBatchHandle& HcommImpl<COMM_PROTOCOL_UBC_CTP>::GetHandleRef(456+__aicore__ inline UbcBatchHandle& HcommImpl<COMM_PROTOCOL_UB_CTP>::GetHandleRef(
457 UbcBatchHandle& batchHandle, uint32_t channelIndex, GM_ADDR remoteAddr)457 UbcBatchHandle& batchHandle, uint32_t channelIndex, GM_ADDR remoteAddr)
458{458{
459 (void)channelIndex;459 (void)channelIndex;
@@ -461,7 +461,7 @@ __aicore__ inline UbcBatchHandle& HcommImpl<COMM_PROTOCOL_UBC_CTP>::GetHandleRef
461 return batchHandle;461 return batchHandle;
462}462}
463 463 
464-__aicore__ inline UbcBatchHandle& HcommImpl<COMM_PROTOCOL_UBC_CTP>::GetHandleRef(464+__aicore__ inline UbcBatchHandle& HcommImpl<COMM_PROTOCOL_UB_CTP>::GetHandleRef(
465 UbcMultiBatchHandle& multiBatchHandle, uint32_t channelIndex, GM_ADDR remoteAddr)465 UbcMultiBatchHandle& multiBatchHandle, uint32_t channelIndex, GM_ADDR remoteAddr)
466{466{
467 multiBatchHandle.handle.remoteInfo = BatchRemoteInfo{};467 multiBatchHandle.handle.remoteInfo = BatchRemoteInfo{};
@@ -487,7 +487,7 @@ __aicore__ inline UbcBatchHandle& HcommImpl<COMM_PROTOCOL_UBC_CTP>::GetHandleRef
487}487}
488 488 
489template <HcommUrmaOpCode opCode, auto const& config>489template <HcommUrmaOpCode opCode, auto const& config>
490-__aicore__ inline int32_t HcommImpl<COMM_PROTOCOL_UBC_CTP>::BatchPostSend(490+__aicore__ inline int32_t HcommImpl<COMM_PROTOCOL_UB_CTP>::BatchPostSend(
491 UbcBatchHandle& batchHandle, GM_ADDR remoteAddr, const BufDesc* localDescs, uint32_t sgeNum, GM_ADDR notifyAddr,491 UbcBatchHandle& batchHandle, GM_ADDR remoteAddr, const BufDesc* localDescs, uint32_t sgeNum, GM_ADDR notifyAddr,
492 uint64_t notifyVal)492 uint64_t notifyVal)
493{493{
@@ -548,7 +548,7 @@ __aicore__ inline int32_t HcommImpl<COMM_PROTOCOL_UBC_CTP>::BatchPostSend(
548}548}
549 549 
550template <auto const& config>550template <auto const& config>
551-__aicore__ inline int32_t HcommImpl<COMM_PROTOCOL_UBC_CTP>::WriteNbi(551+__aicore__ inline int32_t HcommImpl<COMM_PROTOCOL_UB_CTP>::WriteNbi(
552 UbcBatchHandle& batchHandle, GM_ADDR dst, GM_ADDR src, uint32_t len)552 UbcBatchHandle& batchHandle, GM_ADDR dst, GM_ADDR src, uint32_t len)
553{553{
554 const BufDesc srcDesc{src, len};554 const BufDesc srcDesc{src, len};
@@ -556,14 +556,14 @@ __aicore__ inline int32_t HcommImpl<COMM_PROTOCOL_UBC_CTP>::WriteNbi(
556}556}
557 557 
558template <auto const& config>558template <auto const& config>
559-__aicore__ inline int32_t HcommImpl<COMM_PROTOCOL_UBC_CTP>::WriteNbi(559+__aicore__ inline int32_t HcommImpl<COMM_PROTOCOL_UB_CTP>::WriteNbi(
560 UbcBatchHandle& batchHandle, GM_ADDR dst, const BufDesc* srcDescs, uint32_t srcNum)560 UbcBatchHandle& batchHandle, GM_ADDR dst, const BufDesc* srcDescs, uint32_t srcNum)
561{561{
562 return BatchPostSend<HcommUrmaOpCode::WRITE, config>(batchHandle, dst, srcDescs, srcNum);562 return BatchPostSend<HcommUrmaOpCode::WRITE, config>(batchHandle, dst, srcDescs, srcNum);
563}563}
564 564 
565template <auto const& config>565template <auto const& config>
566-__aicore__ inline int32_t HcommImpl<COMM_PROTOCOL_UBC_CTP>::ReadNbi(566+__aicore__ inline int32_t HcommImpl<COMM_PROTOCOL_UB_CTP>::ReadNbi(
567 UbcBatchHandle& batchHandle, GM_ADDR dst, GM_ADDR src, uint32_t len)567 UbcBatchHandle& batchHandle, GM_ADDR dst, GM_ADDR src, uint32_t len)
568{568{
569 const BufDesc dstDesc{dst, len};569 const BufDesc dstDesc{dst, len};
@@ -571,14 +571,14 @@ __aicore__ inline int32_t HcommImpl<COMM_PROTOCOL_UBC_CTP>::ReadNbi(
571}571}
572 572 
573template <auto const& config>573template <auto const& config>
574-__aicore__ inline int32_t HcommImpl<COMM_PROTOCOL_UBC_CTP>::ReadNbi(574+__aicore__ inline int32_t HcommImpl<COMM_PROTOCOL_UB_CTP>::ReadNbi(
575 UbcBatchHandle& batchHandle, const BufDesc* dstDescs, uint32_t dstNum, GM_ADDR src)575 UbcBatchHandle& batchHandle, const BufDesc* dstDescs, uint32_t dstNum, GM_ADDR src)
576{576{
577 return BatchPostSend<HcommUrmaOpCode::READ, config>(batchHandle, src, dstDescs, dstNum);577 return BatchPostSend<HcommUrmaOpCode::READ, config>(batchHandle, src, dstDescs, dstNum);
578}578}
579 579 
580template <auto const& config>580template <auto const& config>
581-__aicore__ inline int32_t HcommImpl<COMM_PROTOCOL_UBC_CTP>::WriteWithNotifyNbi(581+__aicore__ inline int32_t HcommImpl<COMM_PROTOCOL_UB_CTP>::WriteWithNotifyNbi(
582 UbcBatchHandle& batchHandle, GM_ADDR dst, GM_ADDR src, uint32_t len, GM_ADDR notifyAddr, uint64_t notifyVal)582 UbcBatchHandle& batchHandle, GM_ADDR dst, GM_ADDR src, uint32_t len, GM_ADDR notifyAddr, uint64_t notifyVal)
583{583{
584 const BufDesc srcDesc{src, len};584 const BufDesc srcDesc{src, len};
@@ -587,7 +587,7 @@ __aicore__ inline int32_t HcommImpl<COMM_PROTOCOL_UBC_CTP>::WriteWithNotifyNbi(
587}587}
588 588 
589template <auto const& config>589template <auto const& config>
590-__aicore__ inline int32_t HcommImpl<COMM_PROTOCOL_UBC_CTP>::WriteWithNotifyNbi(590+__aicore__ inline int32_t HcommImpl<COMM_PROTOCOL_UB_CTP>::WriteWithNotifyNbi(
591 UbcBatchHandle& batchHandle, GM_ADDR dst, const BufDesc* srcDescs, uint32_t srcNum, GM_ADDR notifyAddr,591 UbcBatchHandle& batchHandle, GM_ADDR dst, const BufDesc* srcDescs, uint32_t srcNum, GM_ADDR notifyAddr,
592 uint64_t notifyVal)592 uint64_t notifyVal)
593{593{
@@ -595,7 +595,7 @@ __aicore__ inline int32_t HcommImpl<COMM_PROTOCOL_UBC_CTP>::WriteWithNotifyNbi(
595 batchHandle, dst, srcDescs, srcNum, notifyAddr, notifyVal);595 batchHandle, dst, srcDescs, srcNum, notifyAddr, notifyVal);
596}596}
597 597 
598-__aicore__ inline void HcommImpl<COMM_PROTOCOL_UBC_CTP>::PollCqWhenCqOverflow(598+__aicore__ inline void HcommImpl<COMM_PROTOCOL_UB_CTP>::PollCqWhenCqOverflow(
599 ChannelHandle channel, const SqContext& sqCtx, const CqContext& cqCtx, uint32_t sqHead, uint32_t cqeCnt)599 ChannelHandle channel, const SqContext& sqCtx, const CqContext& cqCtx, uint32_t sqHead, uint32_t cqeCnt)
600{600{
601 __gm__ ChannelEntity* channelEntity = (__gm__ ChannelEntity*)channel;601 __gm__ ChannelEntity* channelEntity = (__gm__ ChannelEntity*)channel;
@@ -613,7 +613,7 @@ __aicore__ inline void HcommImpl<COMM_PROTOCOL_UBC_CTP>::PollCqWhenCqOverflow(
613 }613 }
614}614}
615 615 
616-__aicore__ inline void HcommImpl<COMM_PROTOCOL_UBC_CTP>::PollCqWhenSqOverflow(616+__aicore__ inline void HcommImpl<COMM_PROTOCOL_UB_CTP>::PollCqWhenSqOverflow(
617 ChannelHandle channel, const SqContext& sqCtx, uint32_t sqHead)617 ChannelHandle channel, const SqContext& sqCtx, uint32_t sqHead)
618{618{
619 __gm__ ChannelEntity* channelEntity = (__gm__ ChannelEntity*)channel;619 __gm__ ChannelEntity* channelEntity = (__gm__ ChannelEntity*)channel;
@@ -626,7 +626,7 @@ __aicore__ inline void HcommImpl<COMM_PROTOCOL_UBC_CTP>::PollCqWhenSqOverflow(
626 }626 }
627}627}
628 628 
629-__aicore__ inline void HcommImpl<COMM_PROTOCOL_UBC_CTP>::CommitImpl(629+__aicore__ inline void HcommImpl<COMM_PROTOCOL_UB_CTP>::CommitImpl(
630 ChannelHandle channel, const SqContext& sqCtx, uint32_t sqHead, uint32_t cqeCnt)630 ChannelHandle channel, const SqContext& sqCtx, uint32_t sqHead, uint32_t cqeCnt)
631{631{
632 __gm__ ChannelEntity* channelEntity = (__gm__ ChannelEntity*)channel;632 __gm__ ChannelEntity* channelEntity = (__gm__ ChannelEntity*)channel;
@@ -638,7 +638,7 @@ __aicore__ inline void HcommImpl<COMM_PROTOCOL_UBC_CTP>::CommitImpl(
638}638}
639 639 
640template <bool commit, pipe_t commitPipe, pipe_t reqPipe, HcommUrmaOpCode opCode, auto const& config, typename T>640template <bool commit, pipe_t commitPipe, pipe_t reqPipe, HcommUrmaOpCode opCode, auto const& config, typename T>
641-__aicore__ inline int32_t HcommImpl<COMM_PROTOCOL_UBC_CTP>::PostSend(641+__aicore__ inline int32_t HcommImpl<COMM_PROTOCOL_UB_CTP>::PostSend(
642 ChannelHandle channel, GM_ADDR remoteAddr, GM_ADDR localAddr, uint64_t len, GM_ADDR notifyAddr,642 ChannelHandle channel, GM_ADDR remoteAddr, GM_ADDR localAddr, uint64_t len, GM_ADDR notifyAddr,
643 const UdmaParams<T>& params)643 const UdmaParams<T>& params)
644{644{
@@ -724,7 +724,7 @@ __aicore__ inline int32_t HcommImpl<COMM_PROTOCOL_UBC_CTP>::PostSend(
724}724}
725 725 
726template <bool sqSafeMode>726template <bool sqSafeMode>
727-__aicore__ inline uint32_t HcommImpl<COMM_PROTOCOL_UBC_CTP>::PollCqImpl(727+__aicore__ inline uint32_t HcommImpl<COMM_PROTOCOL_UB_CTP>::PollCqImpl(
728 uint64_t cqBaseAddr, uint32_t cqeSize, uint32_t cqDepth, uint32_t expectIdx, uint32_t& curTail,728 uint64_t cqBaseAddr, uint32_t cqeSize, uint32_t cqDepth, uint32_t expectIdx, uint32_t& curTail,
729 LocalTensor<uint32_t> cqeItem, uint32_t& sqTail, uint32_t sqHead, uint32_t sqDepth, uint32_t threshold)729 LocalTensor<uint32_t> cqeItem, uint32_t& sqTail, uint32_t sqHead, uint32_t sqDepth, uint32_t threshold)
730{730{
@@ -795,7 +795,7 @@ __aicore__ inline uint32_t HcommImpl<COMM_PROTOCOL_UBC_CTP>::PollCqImpl(
795}795}
796 796 
797template <bool sqSafeMode>797template <bool sqSafeMode>
798-__aicore__ inline uint32_t HcommImpl<COMM_PROTOCOL_UBC_CTP>::PollCq(798+__aicore__ inline uint32_t HcommImpl<COMM_PROTOCOL_UB_CTP>::PollCq(
799 ChannelHandle channel, uint32_t expectIdx, uint32_t sqHead, uint32_t sqDepth, uint32_t threshold)799 ChannelHandle channel, uint32_t expectIdx, uint32_t sqHead, uint32_t sqDepth, uint32_t threshold)
800{800{
801 if (expectIdx == 0) {801 if (expectIdx == 0) {
@@ -823,8 +823,7 @@ __aicore__ inline uint32_t HcommImpl<COMM_PROTOCOL_UBC_CTP>::PollCq(
823 return HCOMM_SUCCESS;823 return HCOMM_SUCCESS;
824}824}
825 825 
826-__aicore__ inline uint32_t HcommImpl<COMM_PROTOCOL_UBC_CTP>::PollBatchCq(826+__aicore__ inline uint32_t HcommImpl<COMM_PROTOCOL_UB_CTP>::PollBatchCq(UbcBatchHandle& batchHandle, uint32_t expectIdx)
827- UbcBatchHandle& batchHandle, uint32_t expectIdx)
828{827{
829 if (expectIdx == 0) {828 if (expectIdx == 0) {
830 return HCOMM_SUCCESS;829 return HCOMM_SUCCESS;
@@ -848,14 +847,14 @@ __aicore__ inline uint32_t HcommImpl<COMM_PROTOCOL_UBC_CTP>::PollBatchCq(
848}847}
849 848 
850template <bool commit, pipe_t commitPipe, pipe_t reqPipe, auto const& config>849template <bool commit, pipe_t commitPipe, pipe_t reqPipe, auto const& config>
851-__aicore__ inline int32_t HcommImpl<COMM_PROTOCOL_UBC_CTP>::WriteNbi(850+__aicore__ inline int32_t HcommImpl<COMM_PROTOCOL_UB_CTP>::WriteNbi(
852 ChannelHandle channel, GM_ADDR dst, GM_ADDR src, uint64_t len)851 ChannelHandle channel, GM_ADDR dst, GM_ADDR src, uint64_t len)
853{852{
854 return PostSend<commit, commitPipe, reqPipe, HcommUrmaOpCode::WRITE, config>(channel, dst, src, len);853 return PostSend<commit, commitPipe, reqPipe, HcommUrmaOpCode::WRITE, config>(channel, dst, src, len);
855}854}
856 855 
857template <typename T, HcommUrmaReduceOp reduceOp, bool commit, pipe_t commitPipe, pipe_t reqPipe, auto const& config>856template <typename T, HcommUrmaReduceOp reduceOp, bool commit, pipe_t commitPipe, pipe_t reqPipe, auto const& config>
858-__aicore__ inline int32_t HcommImpl<COMM_PROTOCOL_UBC_CTP>::WriteReduceNbi(857+__aicore__ inline int32_t HcommImpl<COMM_PROTOCOL_UB_CTP>::WriteReduceNbi(
859 ChannelHandle channel, GM_ADDR dst, GM_ADDR src, uint64_t count)858 ChannelHandle channel, GM_ADDR dst, GM_ADDR src, uint64_t count)
860{859{
861 constexpr uint32_t reduceDataType = HCOMM_URMA_REDUCE_DATA_TYPE<T>;860 constexpr uint32_t reduceDataType = HCOMM_URMA_REDUCE_DATA_TYPE<T>;
@@ -875,14 +874,14 @@ __aicore__ inline int32_t HcommImpl<COMM_PROTOCOL_UBC_CTP>::WriteReduceNbi(
875}874}
876 875 
877template <bool commit, pipe_t commitPipe, pipe_t reqPipe, auto const& config>876template <bool commit, pipe_t commitPipe, pipe_t reqPipe, auto const& config>
878-__aicore__ inline int32_t HcommImpl<COMM_PROTOCOL_UBC_CTP>::ReadNbi(877+__aicore__ inline int32_t HcommImpl<COMM_PROTOCOL_UB_CTP>::ReadNbi(
879 ChannelHandle channel, GM_ADDR dst, GM_ADDR src, uint64_t len)878 ChannelHandle channel, GM_ADDR dst, GM_ADDR src, uint64_t len)
880{879{
881 return PostSend<commit, commitPipe, reqPipe, HcommUrmaOpCode::READ, config>(channel, src, dst, len);880 return PostSend<commit, commitPipe, reqPipe, HcommUrmaOpCode::READ, config>(channel, src, dst, len);
882}881}
883 882 
884template <typename T, bool commit, pipe_t commitPipe, pipe_t reqPipe, auto const& config>883template <typename T, bool commit, pipe_t commitPipe, pipe_t reqPipe, auto const& config>
885-__aicore__ inline int32_t HcommImpl<COMM_PROTOCOL_UBC_CTP>::WriteValueNbi(ChannelHandle channel, GM_ADDR dst, T value)884+__aicore__ inline int32_t HcommImpl<COMM_PROTOCOL_UB_CTP>::WriteValueNbi(ChannelHandle channel, GM_ADDR dst, T value)
886{885{
887 static_assert(config.inlineEn == 1, "WriteValueNbi requires inline data in WQE");886 static_assert(config.inlineEn == 1, "WriteValueNbi requires inline data in WQE");
888 UdmaParams<T> params{value, 0};887 UdmaParams<T> params{value, 0};
@@ -891,7 +890,7 @@ __aicore__ inline int32_t HcommImpl<COMM_PROTOCOL_UBC_CTP>::WriteValueNbi(Channe
891}890}
892 891 
893template <bool commit, pipe_t commitPipe, pipe_t reqPipe, auto const& config>892template <bool commit, pipe_t commitPipe, pipe_t reqPipe, auto const& config>
894-__aicore__ inline int32_t HcommImpl<COMM_PROTOCOL_UBC_CTP>::WriteWithNotifyNbi(893+__aicore__ inline int32_t HcommImpl<COMM_PROTOCOL_UB_CTP>::WriteWithNotifyNbi(
895 ChannelHandle channel, GM_ADDR dst, GM_ADDR src, uint64_t len, GM_ADDR notifyAddr, uint64_t notifyVal)894 ChannelHandle channel, GM_ADDR dst, GM_ADDR src, uint64_t len, GM_ADDR notifyAddr, uint64_t notifyVal)
896{895{
897 UdmaParams<uint64_t> params{notifyVal, 0, 0, 0};896 UdmaParams<uint64_t> params{notifyVal, 0, 0, 0};
@@ -900,7 +899,7 @@ __aicore__ inline int32_t HcommImpl<COMM_PROTOCOL_UBC_CTP>::WriteWithNotifyNbi(
900}899}
901 900 
902template <typename T, bool commit, pipe_t commitPipe, pipe_t reqPipe, auto const& config>901template <typename T, bool commit, pipe_t commitPipe, pipe_t reqPipe, auto const& config>
903-__aicore__ inline int32_t HcommImpl<COMM_PROTOCOL_UBC_CTP>::AtomicFAA(902+__aicore__ inline int32_t HcommImpl<COMM_PROTOCOL_UB_CTP>::AtomicFAA(
904 ChannelHandle channel, GM_ADDR dst, GM_ADDR fetchAddr, T addVal)903 ChannelHandle channel, GM_ADDR dst, GM_ADDR fetchAddr, T addVal)
905{904{
906 static_assert(905 static_assert(
@@ -913,7 +912,7 @@ __aicore__ inline int32_t HcommImpl<COMM_PROTOCOL_UBC_CTP>::AtomicFAA(
913}912}
914 913 
915template <typename T, bool commit, pipe_t commitPipe, pipe_t reqPipe, auto const& config>914template <typename T, bool commit, pipe_t commitPipe, pipe_t reqPipe, auto const& config>
916-__aicore__ inline int32_t HcommImpl<COMM_PROTOCOL_UBC_CTP>::AtomicCAS(915+__aicore__ inline int32_t HcommImpl<COMM_PROTOCOL_UB_CTP>::AtomicCAS(
917 ChannelHandle channel, GM_ADDR dst, GM_ADDR fetchAddr, T compareVal, T swapVal)916 ChannelHandle channel, GM_ADDR dst, GM_ADDR fetchAddr, T compareVal, T swapVal)
918{917{
919 static_assert(918 static_assert(
@@ -926,7 +925,7 @@ __aicore__ inline int32_t HcommImpl<COMM_PROTOCOL_UBC_CTP>::AtomicCAS(
926}925}
927 926 
928template <pipe_t pipe>927template <pipe_t pipe>
929-__aicore__ inline int32_t HcommImpl<COMM_PROTOCOL_UBC_CTP>::Commit(ChannelHandle channel)928+__aicore__ inline int32_t HcommImpl<COMM_PROTOCOL_UB_CTP>::Commit(ChannelHandle channel)
930{929{
931 (void)pipe;930 (void)pipe;
932 __gm__ ChannelEntity* channelEntity = (__gm__ ChannelEntity*)channel;931 __gm__ ChannelEntity* channelEntity = (__gm__ ChannelEntity*)channel;
@@ -935,7 +934,7 @@ __aicore__ inline int32_t HcommImpl<COMM_PROTOCOL_UBC_CTP>::Commit(ChannelHandle
935 return HCOMM_SUCCESS;934 return HCOMM_SUCCESS;
936}935}
937 936 
938-__aicore__ inline int32_t HcommImpl<COMM_PROTOCOL_UBC_CTP>::BatchCommit(UbcBatchHandle& batchHandle)937+__aicore__ inline int32_t HcommImpl<COMM_PROTOCOL_UB_CTP>::BatchCommit(UbcBatchHandle& batchHandle)
939{938{
940 uint32_t preSqCnt = batchHandle.cursor.preSqCnt;939 uint32_t preSqCnt = batchHandle.cursor.preSqCnt;
941 if (preSqCnt == 0 || preSqCnt > batchHandle.buffer.bufferCapacity) {940 if (preSqCnt == 0 || preSqCnt > batchHandle.buffer.bufferCapacity) {
@@ -985,13 +984,13 @@ __aicore__ inline int32_t HcommImpl<COMM_PROTOCOL_UBC_CTP>::BatchCommit(UbcBatch
985 return HCOMM_SUCCESS;984 return HCOMM_SUCCESS;
986}985}
987 986 
988-__aicore__ inline int32_t HcommImpl<COMM_PROTOCOL_UBC_CTP>::BatchCommit(UbcMultiBatchHandle& batchHandle)987+__aicore__ inline int32_t HcommImpl<COMM_PROTOCOL_UB_CTP>::BatchCommit(UbcMultiBatchHandle& batchHandle)
989{988{
990 return BatchCommit(batchHandle.handle);989 return BatchCommit(batchHandle.handle);
991}990}
992 991 
993template <pipe_t pipe>992template <pipe_t pipe>
994-__aicore__ inline int32_t HcommImpl<COMM_PROTOCOL_UBC_CTP>::Drain(ChannelHandle channel)993+__aicore__ inline int32_t HcommImpl<COMM_PROTOCOL_UB_CTP>::Drain(ChannelHandle channel)
995{994{
996 (void)pipe;995 (void)pipe;
997 __gm__ ChannelEntity* channelEntity = (__gm__ ChannelEntity*)channel;996 __gm__ ChannelEntity* channelEntity = (__gm__ ChannelEntity*)channel;
@@ -1004,7 +1003,7 @@ __aicore__ inline int32_t HcommImpl<COMM_PROTOCOL_UBC_CTP>::Drain(ChannelHandle
1004}1003}
1005 1004 
1006template <pipe_t pipe>1005template <pipe_t pipe>
1007-__aicore__ inline int32_t HcommImpl<COMM_PROTOCOL_UBC_CTP>::Drain(UbcBatchHandle& batchHandle)1006+__aicore__ inline int32_t HcommImpl<COMM_PROTOCOL_UB_CTP>::Drain(UbcBatchHandle& batchHandle)
1008{1007{
1009 (void)pipe;1008 (void)pipe;
1010 static_assert(1009 static_assert(
@@ -1032,12 +1031,12 @@ __aicore__ inline int32_t HcommImpl<COMM_PROTOCOL_UBC_CTP>::Drain(UbcBatchHandle
1032}1031}
1033 1032 
1034template <pipe_t pipe>1033template <pipe_t pipe>
1035-__aicore__ inline int32_t HcommImpl<COMM_PROTOCOL_UBC_CTP>::Drain(UbcMultiBatchHandle& batchHandle)1034+__aicore__ inline int32_t HcommImpl<COMM_PROTOCOL_UB_CTP>::Drain(UbcMultiBatchHandle& batchHandle)
1036{1035{
1037 return Drain<pipe>(batchHandle.handle);1036 return Drain<pipe>(batchHandle.handle);
1038}1037}
1039 1038 
1040-__aicore__ inline int32_t HcommImpl<COMM_PROTOCOL_UBC_CTP>::Lock(ChannelHandle channel)1039+__aicore__ inline int32_t HcommImpl<COMM_PROTOCOL_UB_CTP>::Lock(ChannelHandle channel)
1041{1040{
1042 if (channel == 0U || (channel & (alignof(ChannelEntity) - 1U)) != 0U) {1041 if (channel == 0U || (channel & (alignof(ChannelEntity) - 1U)) != 0U) {
1043 return HCOMM_FAILED;1042 return HCOMM_FAILED;
@@ -1052,7 +1051,7 @@ __aicore__ inline int32_t HcommImpl<COMM_PROTOCOL_UBC_CTP>::Lock(ChannelHandle c
1052 return HCOMM_SUCCESS;1051 return HCOMM_SUCCESS;
1053}1052}
1054 1053 
1055-__aicore__ inline int32_t HcommImpl<COMM_PROTOCOL_UBC_CTP>::Unlock(ChannelHandle channel)1054+__aicore__ inline int32_t HcommImpl<COMM_PROTOCOL_UB_CTP>::Unlock(ChannelHandle channel)
1056{1055{
1057 if (channel == 0U || (channel & (alignof(ChannelEntity) - 1U)) != 0U) {1056 if (channel == 0U || (channel & (alignof(ChannelEntity) - 1U)) != 0U) {
1058 return HCOMM_FAILED;1057 return HCOMM_FAILED;
Msrc/aicore/hcomm/impl/platform_v310/hcomm_aiv_urma_def.h+1-1
@@ -69,7 +69,7 @@ struct UdmaParams {
69};69};
70 70 
71template <>71template <>
72-class HcommImpl<COMM_PROTOCOL_UBC_CTP> {72+class HcommImpl<COMM_PROTOCOL_UB_CTP> {
73public:73public:
74 __aicore__ inline HcommImpl();74 __aicore__ inline HcommImpl();
75 __aicore__ inline ~HcommImpl();75 __aicore__ inline ~HcommImpl();
Msrc/aicore/hcomm/impl/platform_v310/hcomm_simt_urma.h+14-14
@@ -317,11 +317,11 @@ __simt_callee__ inline void HcommSimtRingDwqe(__gm__ uint8_t* dwqeAddr, const Hc
317 asc_dcci_single(dwqeAddr + HCOMM_URMA_WQE_BB_SIZE);317 asc_dcci_single(dwqeAddr + HCOMM_URMA_WQE_BB_SIZE);
318}318}
319 319 
320-__simt_callee__ inline HcommImpl<COMM_PROTOCOL_UBC_CTP>::HcommImpl() {}320+__simt_callee__ inline HcommImpl<COMM_PROTOCOL_UB_CTP>::HcommImpl() {}
321 321 
322-__simt_callee__ inline HcommImpl<COMM_PROTOCOL_UBC_CTP>::~HcommImpl() {}322+__simt_callee__ inline HcommImpl<COMM_PROTOCOL_UB_CTP>::~HcommImpl() {}
323 323 
324-__simt_callee__ inline int32_t HcommImpl<COMM_PROTOCOL_UBC_CTP>::Init(__ubuf__ uint8_t* buff, uint32_t len)324+__simt_callee__ inline int32_t HcommImpl<COMM_PROTOCOL_UB_CTP>::Init(__ubuf__ uint8_t* buff, uint32_t len)
325{325{
326 // Nothing to set up: the WQE is staged on the stack for the duration of a post and every326 // Nothing to set up: the WQE is staged on the stack for the duration of a post and every
327 // post resolves its channel from global memory, so there is no state to hand out, publish,327 // post resolves its channel from global memory, so there is no state to hand out, publish,
@@ -332,7 +332,7 @@ __simt_callee__ inline int32_t HcommImpl<COMM_PROTOCOL_UBC_CTP>::Init(__ubuf__ u
332 return HCOMM_SUCCESS;332 return HCOMM_SUCCESS;
333}333}
334 334 
335-__simt_callee__ inline int32_t HcommImpl<COMM_PROTOCOL_UBC_CTP>::ResolvePost(335+__simt_callee__ inline int32_t HcommImpl<COMM_PROTOCOL_UB_CTP>::ResolvePost(
336 ChannelHandle channel, __gm__ uint8_t* remoteAddr, uint64_t len, HcommSimtResolvedPost& post)336 ChannelHandle channel, __gm__ uint8_t* remoteAddr, uint64_t len, HcommSimtResolvedPost& post)
337{337{
338 __gm__ HcommSimtChannelEntity* channelEntity = reinterpret_cast<__gm__ HcommSimtChannelEntity*>(channel);338 __gm__ HcommSimtChannelEntity* channelEntity = reinterpret_cast<__gm__ HcommSimtChannelEntity*>(channel);
@@ -471,7 +471,7 @@ struct HcommSimtAtomicDesc {
471 }471 }
472};472};
473 473 
474-__simt_callee__ inline uint32_t HcommImpl<COMM_PROTOCOL_UBC_CTP>::PollCq(ChannelHandle channel, uint32_t expectIdx)474+__simt_callee__ inline uint32_t HcommImpl<COMM_PROTOCOL_UB_CTP>::PollCq(ChannelHandle channel, uint32_t expectIdx)
475{475{
476 if (expectIdx == 0U) {476 if (expectIdx == 0U) {
477 return HCOMM_SUCCESS;477 return HCOMM_SUCCESS;
@@ -542,7 +542,7 @@ __simt_callee__ inline uint32_t HcommImpl<COMM_PROTOCOL_UBC_CTP>::PollCq(Channel
542// after each. Waiting for every submitted WQE would be wrong: wqeCnt may include deferred WQEs542// after each. Waiting for every submitted WQE would be wrong: wqeCnt may include deferred WQEs
543// that no doorbell has published yet, so those completions never arrive.543// that no doorbell has published yet, so those completions never arrive.
544template <typename Desc>544template <typename Desc>
545-__simt_callee__ inline bool HcommImpl<COMM_PROTOCOL_UBC_CTP>::ReservePost(545+__simt_callee__ inline bool HcommImpl<COMM_PROTOCOL_UB_CTP>::ReservePost(
546 ChannelHandle channel, const HcommSimtResolvedPost& post, uint64_t& headVal)546 ChannelHandle channel, const HcommSimtResolvedPost& post, uint64_t& headVal)
547{547{
548 constexpr bool commit = Desc::commit;548 constexpr bool commit = Desc::commit;
@@ -584,7 +584,7 @@ __simt_callee__ inline bool HcommImpl<COMM_PROTOCOL_UBC_CTP>::ReservePost(
584// task is committed, ring the doorbell. Every step is lane-local; a caller that needs several584// task is committed, ring the doorbell. Every step is lane-local; a caller that needs several
585// lanes to post must serialize them itself.585// lanes to post must serialize them itself.
586template <typename Desc>586template <typename Desc>
587-__simt_callee__ inline int32_t HcommImpl<COMM_PROTOCOL_UBC_CTP>::PostWqe(ChannelHandle channel, const Desc& desc)587+__simt_callee__ inline int32_t HcommImpl<COMM_PROTOCOL_UB_CTP>::PostWqe(ChannelHandle channel, const Desc& desc)
588{588{
589 constexpr uint32_t bbCnt = Desc::bbCnt;589 constexpr uint32_t bbCnt = Desc::bbCnt;
590 constexpr uint32_t wordCnt = bbCnt * HCOMM_SIMT_BB_WORDS;590 constexpr uint32_t wordCnt = bbCnt * HCOMM_SIMT_BB_WORDS;
@@ -636,7 +636,7 @@ __simt_callee__ inline int32_t HcommImpl<COMM_PROTOCOL_UBC_CTP>::PostWqe(Channel
636}636}
637 637 
638template <bool commit, auto const& config>638template <bool commit, auto const& config>
639-__simt_callee__ inline int32_t HcommImpl<COMM_PROTOCOL_UBC_CTP>::WriteNbi(639+__simt_callee__ inline int32_t HcommImpl<COMM_PROTOCOL_UB_CTP>::WriteNbi(
640 ChannelHandle channel, __gm__ void* dst, __gm__ void* src, uint64_t len)640 ChannelHandle channel, __gm__ void* dst, __gm__ void* src, uint64_t len)
641{641{
642 return PostWqe(642 return PostWqe(
@@ -645,7 +645,7 @@ __simt_callee__ inline int32_t HcommImpl<COMM_PROTOCOL_UBC_CTP>::WriteNbi(
645}645}
646 646 
647template <typename T, bool commit, auto const& config>647template <typename T, bool commit, auto const& config>
648-__simt_callee__ inline int32_t HcommImpl<COMM_PROTOCOL_UBC_CTP>::WriteValueNbi(648+__simt_callee__ inline int32_t HcommImpl<COMM_PROTOCOL_UB_CTP>::WriteValueNbi(
649 ChannelHandle channel, __gm__ void* dst, T value)649 ChannelHandle channel, __gm__ void* dst, T value)
650{650{
651 return PostWqe(channel, HcommSimtInlineDesc<T, commit, config>{reinterpret_cast<__gm__ uint8_t*>(dst), value});651 return PostWqe(channel, HcommSimtInlineDesc<T, commit, config>{reinterpret_cast<__gm__ uint8_t*>(dst), value});
@@ -653,7 +653,7 @@ __simt_callee__ inline int32_t HcommImpl<COMM_PROTOCOL_UBC_CTP>::WriteValueNbi(
653 653 
654// Read swaps dst/src relative to Write: src is the remote address, dst the local one.654// Read swaps dst/src relative to Write: src is the remote address, dst the local one.
655template <bool commit, auto const& config>655template <bool commit, auto const& config>
656-__simt_callee__ inline int32_t HcommImpl<COMM_PROTOCOL_UBC_CTP>::ReadNbi(656+__simt_callee__ inline int32_t HcommImpl<COMM_PROTOCOL_UB_CTP>::ReadNbi(
657 ChannelHandle channel, __gm__ void* dst, __gm__ void* src, uint64_t len)657 ChannelHandle channel, __gm__ void* dst, __gm__ void* src, uint64_t len)
658{658{
659 return PostWqe(659 return PostWqe(
@@ -662,7 +662,7 @@ __simt_callee__ inline int32_t HcommImpl<COMM_PROTOCOL_UBC_CTP>::ReadNbi(
662}662}
663 663 
664template <bool commit, auto const& config>664template <bool commit, auto const& config>
665-__simt_callee__ inline int32_t HcommImpl<COMM_PROTOCOL_UBC_CTP>::WriteWithNotifyNbi(665+__simt_callee__ inline int32_t HcommImpl<COMM_PROTOCOL_UB_CTP>::WriteWithNotifyNbi(
666 ChannelHandle channel, __gm__ void* dst, __gm__ void* src, uint64_t len, __gm__ void* notifyAddr,666 ChannelHandle channel, __gm__ void* dst, __gm__ void* src, uint64_t len, __gm__ void* notifyAddr,
667 uint64_t notifyVal)667 uint64_t notifyVal)
668{668{
@@ -673,7 +673,7 @@ __simt_callee__ inline int32_t HcommImpl<COMM_PROTOCOL_UBC_CTP>::WriteWithNotify
673}673}
674 674 
675template <typename T, bool commit, auto const& config>675template <typename T, bool commit, auto const& config>
676-__simt_callee__ inline int32_t HcommImpl<COMM_PROTOCOL_UBC_CTP>::AtomicFAA(676+__simt_callee__ inline int32_t HcommImpl<COMM_PROTOCOL_UB_CTP>::AtomicFAA(
677 ChannelHandle channel, __gm__ void* dst, __gm__ void* fetchAddr, T addVal)677 ChannelHandle channel, __gm__ void* dst, __gm__ void* fetchAddr, T addVal)
678{678{
679 return PostWqe(679 return PostWqe(
@@ -683,7 +683,7 @@ __simt_callee__ inline int32_t HcommImpl<COMM_PROTOCOL_UBC_CTP>::AtomicFAA(
683}683}
684 684 
685template <typename T, bool commit, auto const& config>685template <typename T, bool commit, auto const& config>
686-__simt_callee__ inline int32_t HcommImpl<COMM_PROTOCOL_UBC_CTP>::AtomicCAS(686+__simt_callee__ inline int32_t HcommImpl<COMM_PROTOCOL_UB_CTP>::AtomicCAS(
687 ChannelHandle channel, __gm__ void* dst, __gm__ void* fetchAddr, T compareVal, T swapVal)687 ChannelHandle channel, __gm__ void* dst, __gm__ void* fetchAddr, T compareVal, T swapVal)
688{688{
689 return PostWqe(689 return PostWqe(
@@ -693,7 +693,7 @@ __simt_callee__ inline int32_t HcommImpl<COMM_PROTOCOL_UBC_CTP>::AtomicCAS(
693}693}
694 694 
695template <auto pipe>695template <auto pipe>
696-__simt_callee__ inline int32_t HcommImpl<COMM_PROTOCOL_UBC_CTP>::Drain(ChannelHandle channel)696+__simt_callee__ inline int32_t HcommImpl<COMM_PROTOCOL_UB_CTP>::Drain(ChannelHandle channel)
697{697{
698 (void)pipe;698 (void)pipe;
699 __gm__ HcommSimtChannelEntity* channelEntity = reinterpret_cast<__gm__ HcommSimtChannelEntity*>(channel);699 __gm__ HcommSimtChannelEntity* channelEntity = reinterpret_cast<__gm__ HcommSimtChannelEntity*>(channel);
Msrc/aicore/hcomm/impl/platform_v310/hcomm_simt_urma_def.h+1-1
@@ -66,7 +66,7 @@ struct HcommSimtPackedSqeTemplate {
66};66};
67 67 
68template <>68template <>
69-class HcommImpl<COMM_PROTOCOL_UBC_CTP> {69+class HcommImpl<COMM_PROTOCOL_UB_CTP> {
70public:70public:
71 __simt_callee__ inline HcommImpl();71 __simt_callee__ inline HcommImpl();
72 __simt_callee__ inline ~HcommImpl();72 __simt_callee__ inline ~HcommImpl();
Mtests/ut/aicore/hcomm/test_hcomm_urma_950.cpp+31-31
@@ -252,7 +252,7 @@ protected:
252 252 
253 void TearDown() override { block_idx = blockIdxBak_; }253 void TearDown() override { block_idx = blockIdxBak_; }
254 254 
255- int32_t InitHcomm(AscendC::Hcomm<AscendC::COMM_PROTOCOL_UBC_CTP>& hcomm)255+ int32_t InitHcomm(AscendC::Hcomm<AscendC::COMM_PROTOCOL_UB_CTP>& hcomm)
256 {256 {
257 pipe_.InitBuffer(hcommBuf_, AscendC::HCOMM_URMA_TMP_BUF_SIZE);257 pipe_.InitBuffer(hcommBuf_, AscendC::HCOMM_URMA_TMP_BUF_SIZE);
258 AscendC::LocalTensor<uint8_t> hcommLocal = hcommBuf_.Get<uint8_t>();258 AscendC::LocalTensor<uint8_t> hcommLocal = hcommBuf_.Get<uint8_t>();
@@ -271,7 +271,7 @@ protected:
271 constexpr uint64_t localAddr = 0x2008;271 constexpr uint64_t localAddr = 0x2008;
272 UrmaChannelResource channel;272 UrmaChannelResource channel;
273 273 
274- AscendC::Hcomm<AscendC::COMM_PROTOCOL_UBC_CTP> hcomm;274+ AscendC::Hcomm<AscendC::COMM_PROTOCOL_UB_CTP> hcomm;
275 ASSERT_EQ(InitHcomm(hcomm), AscendC::HCOMM_SUCCESS);275 ASSERT_EQ(InitHcomm(hcomm), AscendC::HCOMM_SUCCESS);
276 int32_t ret = hcomm.WriteReduceNbi<T, reduceOp, false>(276 int32_t ret = hcomm.WriteReduceNbi<T, reduceOp, false>(
277 channel.GetHandle(), reinterpret_cast<GM_ADDR>(remoteAddr), reinterpret_cast<GM_ADDR>(localAddr), count);277 channel.GetHandle(), reinterpret_cast<GM_ADDR>(remoteAddr), reinterpret_cast<GM_ADDR>(localAddr), count);
@@ -301,7 +301,7 @@ TEST_F(HcommUrmaTestSuite, Aiv_Urma_MakeBatchHandleLocalTensor)
301{301{
302 UrmaChannelResource channel;302 UrmaChannelResource channel;
303 channel.SetQueueState(3U, 2U, 1U);303 channel.SetQueueState(3U, 2U, 1U);
304- AscendC::Hcomm<AscendC::COMM_PROTOCOL_UBC_CTP> hcomm;304+ AscendC::Hcomm<AscendC::COMM_PROTOCOL_UB_CTP> hcomm;
305 AscendC::TPipe pipe;305 AscendC::TPipe pipe;
306 AscendC::TBuf<AscendC::TPosition::VECOUT> batchBuffer;306 AscendC::TBuf<AscendC::TPosition::VECOUT> batchBuffer;
307 pipe.InitBuffer(batchBuffer, 128);307 pipe.InitBuffer(batchBuffer, 128);
@@ -360,7 +360,7 @@ TEST_F(HcommUrmaTestSuite, Aiv_Urma_MultiChannelBatchUsesOuterHandleForCommitAnd
360 "UbcMultiBatchHandle must resolve to its execution BatchHandle");360 "UbcMultiBatchHandle must resolve to its execution BatchHandle");
361 361 
362 UrmaMultiChannelResource multiChannel;362 UrmaMultiChannelResource multiChannel;
363- AscendC::Hcomm<AscendC::COMM_PROTOCOL_UBC_CTP> hcomm;363+ AscendC::Hcomm<AscendC::COMM_PROTOCOL_UB_CTP> hcomm;
364 alignas(32) std::array<uint8_t, 2U * URMA_WQE_SIZE> batchBuffer{};364 alignas(32) std::array<uint8_t, 2U * URMA_WQE_SIZE> batchBuffer{};
365 auto multiBatchHandle =365 auto multiBatchHandle =
366 hcomm.MakeBatchHandle(multiChannel.GetHandle(), WrapUbBuffer(batchBuffer), batchBuffer.size());366 hcomm.MakeBatchHandle(multiChannel.GetHandle(), WrapUbBuffer(batchBuffer), batchBuffer.size());
@@ -408,7 +408,7 @@ TEST_F(HcommUrmaTestSuite, Aiv_Urma_MultiChannelBatchUsesOuterHandleForCommitAnd
408TEST_F(HcommUrmaTestSuite, Aiv_Urma_BatchWriteNbi)408TEST_F(HcommUrmaTestSuite, Aiv_Urma_BatchWriteNbi)
409{409{
410 UrmaChannelResource channel(URMA_BATCH_QUEUE_DEPTH);410 UrmaChannelResource channel(URMA_BATCH_QUEUE_DEPTH);
411- AscendC::Hcomm<AscendC::COMM_PROTOCOL_UBC_CTP> hcomm;411+ AscendC::Hcomm<AscendC::COMM_PROTOCOL_UB_CTP> hcomm;
412 alignas(32) std::array<uint8_t, 128> batchBuffer;412 alignas(32) std::array<uint8_t, 128> batchBuffer;
413 batchBuffer.fill(0xFFU);413 batchBuffer.fill(0xFFU);
414 auto batchHandle = hcomm.MakeBatchHandle(414 auto batchHandle = hcomm.MakeBatchHandle(
@@ -462,7 +462,7 @@ TEST_F(HcommUrmaTestSuite, Aiv_Urma_BatchWriteNbi)
462TEST_F(HcommUrmaTestSuite, Aiv_Urma_BatchReadNbi)462TEST_F(HcommUrmaTestSuite, Aiv_Urma_BatchReadNbi)
463{463{
464 UrmaChannelResource channel(URMA_BATCH_QUEUE_DEPTH);464 UrmaChannelResource channel(URMA_BATCH_QUEUE_DEPTH);
465- AscendC::Hcomm<AscendC::COMM_PROTOCOL_UBC_CTP> hcomm;465+ AscendC::Hcomm<AscendC::COMM_PROTOCOL_UB_CTP> hcomm;
466 alignas(32) std::array<uint8_t, 128> batchBuffer;466 alignas(32) std::array<uint8_t, 128> batchBuffer;
467 batchBuffer.fill(0xFFU);467 batchBuffer.fill(0xFFU);
468 auto batchHandle = hcomm.MakeBatchHandle(468 auto batchHandle = hcomm.MakeBatchHandle(
@@ -506,7 +506,7 @@ TEST_F(HcommUrmaTestSuite, Aiv_Urma_BatchReadNbi)
506TEST_F(HcommUrmaTestSuite, Aiv_Urma_BatchWriteWithNotifyNbiMixed)506TEST_F(HcommUrmaTestSuite, Aiv_Urma_BatchWriteWithNotifyNbiMixed)
507{507{
508 UrmaChannelResource channel(8);508 UrmaChannelResource channel(8);
509- AscendC::Hcomm<AscendC::COMM_PROTOCOL_UBC_CTP> hcomm;509+ AscendC::Hcomm<AscendC::COMM_PROTOCOL_UB_CTP> hcomm;
510 alignas(32) std::array<uint8_t, 384> batchBuffer{};510 alignas(32) std::array<uint8_t, 384> batchBuffer{};
511 auto batchHandle = hcomm.MakeBatchHandle(511 auto batchHandle = hcomm.MakeBatchHandle(
512 channel.GetHandle(), WrapUbBuffer(batchBuffer), batchBuffer.size(), reinterpret_cast<GM_ADDR>(0x1008));512 channel.GetHandle(), WrapUbBuffer(batchBuffer), batchBuffer.size(), reinterpret_cast<GM_ADDR>(0x1008));
@@ -581,7 +581,7 @@ TEST_F(HcommUrmaTestSuite, Aiv_Urma_BatchWriteWithNotifyEncodes64BitAddresses)
581 UrmaChannelResource channel(URMA_BATCH_QUEUE_DEPTH);581 UrmaChannelResource channel(URMA_BATCH_QUEUE_DEPTH);
582 channel.SetRemoteBufferAddr(0U, remoteBase);582 channel.SetRemoteBufferAddr(0U, remoteBase);
583 channel.SetLocalBufferAddr(0U, localBase);583 channel.SetLocalBufferAddr(0U, localBase);
584- AscendC::Hcomm<AscendC::COMM_PROTOCOL_UBC_CTP> hcomm;584+ AscendC::Hcomm<AscendC::COMM_PROTOCOL_UB_CTP> hcomm;
585 alignas(32) std::array<uint8_t, 2U * URMA_WQE_SIZE> batchBuffer{};585 alignas(32) std::array<uint8_t, 2U * URMA_WQE_SIZE> batchBuffer{};
586 auto batchHandle = hcomm.MakeBatchHandle(586 auto batchHandle = hcomm.MakeBatchHandle(
587 channel.GetHandle(), WrapUbBuffer(batchBuffer), batchBuffer.size(), reinterpret_cast<GM_ADDR>(remoteBase + 8U));587 channel.GetHandle(), WrapUbBuffer(batchBuffer), batchBuffer.size(), reinterpret_cast<GM_ADDR>(remoteBase + 8U));
@@ -607,7 +607,7 @@ TEST_F(HcommUrmaTestSuite, Aiv_Urma_BatchWriteWithNotifyEncodes64BitAddresses)
607TEST_F(HcommUrmaTestSuite, Aiv_Urma_BatchReadWriteNotifyMixedCommit)607TEST_F(HcommUrmaTestSuite, Aiv_Urma_BatchReadWriteNotifyMixedCommit)
608{608{
609 UrmaChannelResource channel(8);609 UrmaChannelResource channel(8);
610- AscendC::Hcomm<AscendC::COMM_PROTOCOL_UBC_CTP> hcomm;610+ AscendC::Hcomm<AscendC::COMM_PROTOCOL_UB_CTP> hcomm;
611 alignas(32) std::array<uint8_t, 256> batchBuffer{};611 alignas(32) std::array<uint8_t, 256> batchBuffer{};
612 auto batchHandle = hcomm.MakeBatchHandle(612 auto batchHandle = hcomm.MakeBatchHandle(
613 channel.GetHandle(), WrapUbBuffer(batchBuffer), batchBuffer.size(), reinterpret_cast<GM_ADDR>(0x1008));613 channel.GetHandle(), WrapUbBuffer(batchBuffer), batchBuffer.size(), reinterpret_cast<GM_ADDR>(0x1008));
@@ -639,7 +639,7 @@ TEST_F(HcommUrmaTestSuite, Aiv_Urma_BatchReadWriteNotifyMixedCommit)
639TEST_F(HcommUrmaTestSuite, Aiv_Urma_BatchCommitRejectsInvalidCounts)639TEST_F(HcommUrmaTestSuite, Aiv_Urma_BatchCommitRejectsInvalidCounts)
640{640{
641 UrmaChannelResource channel(URMA_BATCH_QUEUE_DEPTH);641 UrmaChannelResource channel(URMA_BATCH_QUEUE_DEPTH);
642- AscendC::Hcomm<AscendC::COMM_PROTOCOL_UBC_CTP> hcomm;642+ AscendC::Hcomm<AscendC::COMM_PROTOCOL_UB_CTP> hcomm;
643 alignas(32) std::array<uint8_t, URMA_WQE_SIZE> batchBuffer{};643 alignas(32) std::array<uint8_t, URMA_WQE_SIZE> batchBuffer{};
644 auto batchHandle = hcomm.MakeBatchHandle(644 auto batchHandle = hcomm.MakeBatchHandle(
645 channel.GetHandle(), WrapUbBuffer(batchBuffer), batchBuffer.size(), reinterpret_cast<GM_ADDR>(0x1008));645 channel.GetHandle(), WrapUbBuffer(batchBuffer), batchBuffer.size(), reinterpret_cast<GM_ADDR>(0x1008));
@@ -670,7 +670,7 @@ TEST_F(HcommUrmaTestSuite, Aiv_Urma_BatchHandleCommitWrapAndReuse)
670{670{
671 UrmaChannelResource channel(URMA_BATCH_QUEUE_DEPTH);671 UrmaChannelResource channel(URMA_BATCH_QUEUE_DEPTH);
672 channel.SetSqHead(URMA_BATCH_QUEUE_DEPTH - 1U);672 channel.SetSqHead(URMA_BATCH_QUEUE_DEPTH - 1U);
673- AscendC::Hcomm<AscendC::COMM_PROTOCOL_UBC_CTP> hcomm;673+ AscendC::Hcomm<AscendC::COMM_PROTOCOL_UB_CTP> hcomm;
674 alignas(32) std::array<uint8_t, 128> batchBuffer{};674 alignas(32) std::array<uint8_t, 128> batchBuffer{};
675 auto batchHandle = hcomm.MakeBatchHandle(675 auto batchHandle = hcomm.MakeBatchHandle(
676 channel.GetHandle(), WrapUbBuffer(batchBuffer), batchBuffer.size(), reinterpret_cast<GM_ADDR>(0x1008));676 channel.GetHandle(), WrapUbBuffer(batchBuffer), batchBuffer.size(), reinterpret_cast<GM_ADDR>(0x1008));
@@ -712,7 +712,7 @@ TEST_F(HcommUrmaTestSuite, Aiv_Urma_BatchWriteWithNotifyCommitWrapsSingleWqe)
712{712{
713 UrmaChannelResource channel(URMA_BATCH_QUEUE_DEPTH);713 UrmaChannelResource channel(URMA_BATCH_QUEUE_DEPTH);
714 channel.SetSqHead(URMA_BATCH_QUEUE_DEPTH - 1U);714 channel.SetSqHead(URMA_BATCH_QUEUE_DEPTH - 1U);
715- AscendC::Hcomm<AscendC::COMM_PROTOCOL_UBC_CTP> hcomm;715+ AscendC::Hcomm<AscendC::COMM_PROTOCOL_UB_CTP> hcomm;
716 alignas(32) std::array<uint8_t, 2U * URMA_WQE_SIZE> batchBuffer{};716 alignas(32) std::array<uint8_t, 2U * URMA_WQE_SIZE> batchBuffer{};
717 auto batchHandle = hcomm.MakeBatchHandle(717 auto batchHandle = hcomm.MakeBatchHandle(
718 channel.GetHandle(), WrapUbBuffer(batchBuffer), batchBuffer.size(), reinterpret_cast<GM_ADDR>(0x1008));718 channel.GetHandle(), WrapUbBuffer(batchBuffer), batchBuffer.size(), reinterpret_cast<GM_ADDR>(0x1008));
@@ -735,7 +735,7 @@ TEST_F(HcommUrmaTestSuite, Aiv_Urma_BatchWriteWithNotifyCommitWrapsSingleWqe)
735TEST_F(HcommUrmaTestSuite, Aiv_Urma_BatchAllNoCqeCommitAndDrain)735TEST_F(HcommUrmaTestSuite, Aiv_Urma_BatchAllNoCqeCommitAndDrain)
736{736{
737 UrmaChannelResource channel(8);737 UrmaChannelResource channel(8);
738- AscendC::Hcomm<AscendC::COMM_PROTOCOL_UBC_CTP> hcomm;738+ AscendC::Hcomm<AscendC::COMM_PROTOCOL_UB_CTP> hcomm;
739 alignas(32) std::array<uint8_t, 4U * URMA_WQE_SIZE> batchBuffer{};739 alignas(32) std::array<uint8_t, 4U * URMA_WQE_SIZE> batchBuffer{};
740 auto batchHandle = hcomm.MakeBatchHandle(740 auto batchHandle = hcomm.MakeBatchHandle(
741 channel.GetHandle(), WrapUbBuffer(batchBuffer), batchBuffer.size(), reinterpret_cast<GM_ADDR>(0x1008));741 channel.GetHandle(), WrapUbBuffer(batchBuffer), batchBuffer.size(), reinterpret_cast<GM_ADDR>(0x1008));
@@ -770,7 +770,7 @@ TEST_F(HcommUrmaTestSuite, Aiv_Urma_BatchAllNoCqeCommitAndDrain)
770TEST_F(HcommUrmaTestSuite, Aiv_Urma_BatchMultipleCommitsSingleDrain)770TEST_F(HcommUrmaTestSuite, Aiv_Urma_BatchMultipleCommitsSingleDrain)
771{771{
772 UrmaChannelResource channel(8);772 UrmaChannelResource channel(8);
773- AscendC::Hcomm<AscendC::COMM_PROTOCOL_UBC_CTP> hcomm;773+ AscendC::Hcomm<AscendC::COMM_PROTOCOL_UB_CTP> hcomm;
774 alignas(32) std::array<uint8_t, 3U * URMA_WQE_SIZE> batchBuffer{};774 alignas(32) std::array<uint8_t, 3U * URMA_WQE_SIZE> batchBuffer{};
775 auto batchHandle = hcomm.MakeBatchHandle(775 auto batchHandle = hcomm.MakeBatchHandle(
776 channel.GetHandle(), WrapUbBuffer(batchBuffer), batchBuffer.size(), reinterpret_cast<GM_ADDR>(0x1008));776 channel.GetHandle(), WrapUbBuffer(batchBuffer), batchBuffer.size(), reinterpret_cast<GM_ADDR>(0x1008));
@@ -812,7 +812,7 @@ TEST_F(HcommUrmaTestSuite, Aiv_Urma_BatchMultipleCommitsSingleDrain)
812TEST_F(HcommUrmaTestSuite, Aiv_Urma_BatchDrainRejectsInvalidHandleState)812TEST_F(HcommUrmaTestSuite, Aiv_Urma_BatchDrainRejectsInvalidHandleState)
813{813{
814 UrmaChannelResource channel(URMA_BATCH_QUEUE_DEPTH);814 UrmaChannelResource channel(URMA_BATCH_QUEUE_DEPTH);
815- AscendC::Hcomm<AscendC::COMM_PROTOCOL_UBC_CTP> hcomm;815+ AscendC::Hcomm<AscendC::COMM_PROTOCOL_UB_CTP> hcomm;
816 alignas(32) std::array<uint8_t, URMA_WQE_SIZE> batchBuffer{};816 alignas(32) std::array<uint8_t, URMA_WQE_SIZE> batchBuffer{};
817 auto batchHandle = hcomm.MakeBatchHandle(817 auto batchHandle = hcomm.MakeBatchHandle(
818 channel.GetHandle(), WrapUbBuffer(batchBuffer), batchBuffer.size(), reinterpret_cast<GM_ADDR>(0x1008));818 channel.GetHandle(), WrapUbBuffer(batchBuffer), batchBuffer.size(), reinterpret_cast<GM_ADDR>(0x1008));
@@ -845,7 +845,7 @@ TEST_F(HcommUrmaTestSuite, Aiv_Urma_BatchDrainRejectsInvalidHandleState)
845TEST_F(HcommUrmaTestSuite, Aiv_Urma_BatchDrainWithoutInit)845TEST_F(HcommUrmaTestSuite, Aiv_Urma_BatchDrainWithoutInit)
846{846{
847 UrmaChannelResource channel(URMA_BATCH_QUEUE_DEPTH);847 UrmaChannelResource channel(URMA_BATCH_QUEUE_DEPTH);
848- AscendC::Hcomm<AscendC::COMM_PROTOCOL_UBC_CTP> hcomm;848+ AscendC::Hcomm<AscendC::COMM_PROTOCOL_UB_CTP> hcomm;
849 alignas(32) std::array<uint8_t, 64> batchBuffer{};849 alignas(32) std::array<uint8_t, 64> batchBuffer{};
850 auto batchHandle = hcomm.MakeBatchHandle(850 auto batchHandle = hcomm.MakeBatchHandle(
851 channel.GetHandle(), WrapUbBuffer(batchBuffer), batchBuffer.size(), reinterpret_cast<GM_ADDR>(0x1008));851 channel.GetHandle(), WrapUbBuffer(batchBuffer), batchBuffer.size(), reinterpret_cast<GM_ADDR>(0x1008));
@@ -876,7 +876,7 @@ TEST_F(HcommUrmaTestSuite, Aiv_Urma_BatchDrainWithoutInit)
876TEST_F(HcommUrmaTestSuite, Aiv_Urma_LockUnlock)876TEST_F(HcommUrmaTestSuite, Aiv_Urma_LockUnlock)
877{877{
878 UrmaChannelResource channel;878 UrmaChannelResource channel;
879- AscendC::Hcomm<AscendC::COMM_PROTOCOL_UBC_CTP> hcomm;879+ AscendC::Hcomm<AscendC::COMM_PROTOCOL_UB_CTP> hcomm;
880 880 
881 EXPECT_EQ(channel.GetLock(), AscendC::HCOMM_LOCK_FREE);881 EXPECT_EQ(channel.GetLock(), AscendC::HCOMM_LOCK_FREE);
882 EXPECT_EQ(hcomm.Lock(channel.GetHandle()), AscendC::HCOMM_SUCCESS);882 EXPECT_EQ(hcomm.Lock(channel.GetHandle()), AscendC::HCOMM_SUCCESS);
@@ -888,7 +888,7 @@ TEST_F(HcommUrmaTestSuite, Aiv_Urma_LockUnlock)
888TEST_F(HcommUrmaTestSuite, Aiv_Urma_UnlockWithoutLock)888TEST_F(HcommUrmaTestSuite, Aiv_Urma_UnlockWithoutLock)
889{889{
890 UrmaChannelResource channel;890 UrmaChannelResource channel;
891- AscendC::Hcomm<AscendC::COMM_PROTOCOL_UBC_CTP> hcomm;891+ AscendC::Hcomm<AscendC::COMM_PROTOCOL_UB_CTP> hcomm;
892 892 
893 EXPECT_EQ(channel.GetLock(), AscendC::HCOMM_LOCK_FREE);893 EXPECT_EQ(channel.GetLock(), AscendC::HCOMM_LOCK_FREE);
894 EXPECT_EQ(hcomm.Unlock(channel.GetHandle()), AscendC::HCOMM_FAILED);894 EXPECT_EQ(hcomm.Unlock(channel.GetHandle()), AscendC::HCOMM_FAILED);
@@ -898,7 +898,7 @@ TEST_F(HcommUrmaTestSuite, Aiv_Urma_UnlockWithoutLock)
898TEST_F(HcommUrmaTestSuite, Aiv_Urma_LockUnlockInvalidChannel)898TEST_F(HcommUrmaTestSuite, Aiv_Urma_LockUnlockInvalidChannel)
899{899{
900 UrmaChannelResource channel;900 UrmaChannelResource channel;
901- AscendC::Hcomm<AscendC::COMM_PROTOCOL_UBC_CTP> hcomm;901+ AscendC::Hcomm<AscendC::COMM_PROTOCOL_UB_CTP> hcomm;
902 ChannelHandle misalignedChannel = channel.GetHandle() + 1U;902 ChannelHandle misalignedChannel = channel.GetHandle() + 1U;
903 903 
904 EXPECT_EQ(hcomm.Lock(0U), AscendC::HCOMM_FAILED);904 EXPECT_EQ(hcomm.Lock(0U), AscendC::HCOMM_FAILED);
@@ -912,7 +912,7 @@ TEST_F(HcommUrmaTestSuite, Aiv_Urma_Read)
912{912{
913 UrmaChannelResource channel;913 UrmaChannelResource channel;
914 914 
915- AscendC::Hcomm<AscendC::COMM_PROTOCOL_UBC_CTP> hcomm;915+ AscendC::Hcomm<AscendC::COMM_PROTOCOL_UB_CTP> hcomm;
916 EXPECT_EQ(InitHcomm(hcomm), AscendC::HCOMM_SUCCESS);916 EXPECT_EQ(InitHcomm(hcomm), AscendC::HCOMM_SUCCESS);
917 int32_t ret =917 int32_t ret =
918 hcomm.ReadNbi(channel.GetHandle(), reinterpret_cast<GM_ADDR>(0x5008), reinterpret_cast<GM_ADDR>(0x3008), 8);918 hcomm.ReadNbi(channel.GetHandle(), reinterpret_cast<GM_ADDR>(0x5008), reinterpret_cast<GM_ADDR>(0x3008), 8);
@@ -927,7 +927,7 @@ TEST_F(HcommUrmaTestSuite, Aiv_Urma_Write)
927{927{
928 UrmaChannelResource channel;928 UrmaChannelResource channel;
929 929 
930- AscendC::Hcomm<AscendC::COMM_PROTOCOL_UBC_CTP> hcomm;930+ AscendC::Hcomm<AscendC::COMM_PROTOCOL_UB_CTP> hcomm;
931 EXPECT_EQ(InitHcomm(hcomm), AscendC::HCOMM_SUCCESS);931 EXPECT_EQ(InitHcomm(hcomm), AscendC::HCOMM_SUCCESS);
932 int32_t ret = hcomm.WriteNbi<false>(932 int32_t ret = hcomm.WriteNbi<false>(
933 channel.GetHandle(), reinterpret_cast<GM_ADDR>(0x3008), reinterpret_cast<GM_ADDR>(0x5008), 8);933 channel.GetHandle(), reinterpret_cast<GM_ADDR>(0x3008), reinterpret_cast<GM_ADDR>(0x5008), 8);
@@ -959,7 +959,7 @@ TEST_F(HcommUrmaTestSuite, Aiv_Urma_WriteWithNotify)
959{959{
960 UrmaChannelResource channel;960 UrmaChannelResource channel;
961 961 
962- AscendC::Hcomm<AscendC::COMM_PROTOCOL_UBC_CTP> hcomm;962+ AscendC::Hcomm<AscendC::COMM_PROTOCOL_UB_CTP> hcomm;
963 EXPECT_EQ(InitHcomm(hcomm), AscendC::HCOMM_SUCCESS);963 EXPECT_EQ(InitHcomm(hcomm), AscendC::HCOMM_SUCCESS);
964 int32_t ret = hcomm.WriteWithNotifyNbi<false>(964 int32_t ret = hcomm.WriteWithNotifyNbi<false>(
965 channel.GetHandle(), reinterpret_cast<GM_ADDR>(0x3008), reinterpret_cast<GM_ADDR>(0x5008), 8,965 channel.GetHandle(), reinterpret_cast<GM_ADDR>(0x3008), reinterpret_cast<GM_ADDR>(0x5008), 8,
@@ -977,7 +977,7 @@ TEST_F(HcommUrmaTestSuite, Aiv_Urma_WriteWithValue)
977{977{
978 UrmaChannelResource channel;978 UrmaChannelResource channel;
979 979 
980- AscendC::Hcomm<AscendC::COMM_PROTOCOL_UBC_CTP> hcomm;980+ AscendC::Hcomm<AscendC::COMM_PROTOCOL_UB_CTP> hcomm;
981 EXPECT_EQ(InitHcomm(hcomm), AscendC::HCOMM_SUCCESS);981 EXPECT_EQ(InitHcomm(hcomm), AscendC::HCOMM_SUCCESS);
982 int32_t ret =982 int32_t ret =
983 hcomm.WriteValueNbi<uint64_t>(channel.GetHandle(), reinterpret_cast<GM_ADDR>(0x3008), 0xCAFEBABEDEADBEEFULL);983 hcomm.WriteValueNbi<uint64_t>(channel.GetHandle(), reinterpret_cast<GM_ADDR>(0x3008), 0xCAFEBABEDEADBEEFULL);
@@ -992,7 +992,7 @@ TEST_F(HcommUrmaTestSuite, Aiv_Urma_WriteWithValue_DelayedCommit)
992{992{
993 UrmaChannelResource channel;993 UrmaChannelResource channel;
994 994 
995- AscendC::Hcomm<AscendC::COMM_PROTOCOL_UBC_CTP> hcomm;995+ AscendC::Hcomm<AscendC::COMM_PROTOCOL_UB_CTP> hcomm;
996 EXPECT_EQ(InitHcomm(hcomm), AscendC::HCOMM_SUCCESS);996 EXPECT_EQ(InitHcomm(hcomm), AscendC::HCOMM_SUCCESS);
997 int32_t ret =997 int32_t ret =
998 hcomm.WriteValueNbi<uint32_t, false>(channel.GetHandle(), reinterpret_cast<GM_ADDR>(0x1008), 0x12345678U);998 hcomm.WriteValueNbi<uint32_t, false>(channel.GetHandle(), reinterpret_cast<GM_ADDR>(0x1008), 0x12345678U);
@@ -1009,7 +1009,7 @@ TEST_F(HcommUrmaTestSuite, Aiv_Urma_WriteWithValue_WqeBbCnt)
1009{1009{
1010 UrmaChannelResource channel;1010 UrmaChannelResource channel;
1011 1011 
1012- AscendC::Hcomm<AscendC::COMM_PROTOCOL_UBC_CTP> hcomm;1012+ AscendC::Hcomm<AscendC::COMM_PROTOCOL_UB_CTP> hcomm;
1013 EXPECT_EQ(InitHcomm(hcomm), AscendC::HCOMM_SUCCESS);1013 EXPECT_EQ(InitHcomm(hcomm), AscendC::HCOMM_SUCCESS);
1014 1014 
1015 int32_t ret = hcomm.WriteValueNbi<uint64_t, false>(channel.GetHandle(), reinterpret_cast<GM_ADDR>(0x1008), 0xAAULL);1015 int32_t ret = hcomm.WriteValueNbi<uint64_t, false>(channel.GetHandle(), reinterpret_cast<GM_ADDR>(0x1008), 0xAAULL);
@@ -1026,7 +1026,7 @@ TEST_F(HcommUrmaTestSuite, Aiv_Urma_WriteWithValue_RemoteBufferNotFound)
1026{1026{
1027 UrmaChannelResource channel;1027 UrmaChannelResource channel;
1028 1028 
1029- AscendC::Hcomm<AscendC::COMM_PROTOCOL_UBC_CTP> hcomm;1029+ AscendC::Hcomm<AscendC::COMM_PROTOCOL_UB_CTP> hcomm;
1030 EXPECT_EQ(InitHcomm(hcomm), AscendC::HCOMM_SUCCESS);1030 EXPECT_EQ(InitHcomm(hcomm), AscendC::HCOMM_SUCCESS);
1031 1031 
1032 int32_t ret = hcomm.WriteValueNbi<uint64_t>(channel.GetHandle(), reinterpret_cast<GM_ADDR>(0x9000), 0x1ULL);1032 int32_t ret = hcomm.WriteValueNbi<uint64_t>(channel.GetHandle(), reinterpret_cast<GM_ADDR>(0x9000), 0x1ULL);
@@ -1039,7 +1039,7 @@ TEST_F(HcommUrmaTestSuite, Aiv_Urma_WriteWithNotify_WqeBbCnt)
1039{1039{
1040 UrmaChannelResource channel;1040 UrmaChannelResource channel;
1041 1041 
1042- AscendC::Hcomm<AscendC::COMM_PROTOCOL_UBC_CTP> hcomm;1042+ AscendC::Hcomm<AscendC::COMM_PROTOCOL_UB_CTP> hcomm;
1043 EXPECT_EQ(InitHcomm(hcomm), AscendC::HCOMM_SUCCESS);1043 EXPECT_EQ(InitHcomm(hcomm), AscendC::HCOMM_SUCCESS);
1044 1044 
1045 // WriteNbi should advance sqHead by 11045 // WriteNbi should advance sqHead by 1
@@ -1067,7 +1067,7 @@ TEST_F(HcommUrmaTestSuite, Aiv_Urma_RemoteBufferNotFound)
1067{1067{
1068 UrmaChannelResource channel;1068 UrmaChannelResource channel;
1069 1069 
1070- AscendC::Hcomm<AscendC::COMM_PROTOCOL_UBC_CTP> hcomm;1070+ AscendC::Hcomm<AscendC::COMM_PROTOCOL_UB_CTP> hcomm;
1071 EXPECT_EQ(InitHcomm(hcomm), AscendC::HCOMM_SUCCESS);1071 EXPECT_EQ(InitHcomm(hcomm), AscendC::HCOMM_SUCCESS);
1072 1072 
1073 // Address completely outside any remote buffer range (remote buffers are at 0x1000-0x2000 and 0x3000-0x4000)1073 // Address completely outside any remote buffer range (remote buffers are at 0x1000-0x2000 and 0x3000-0x4000)
@@ -1087,7 +1087,7 @@ TEST_F(HcommUrmaTestSuite, Aiv_Urma_BatchCommitDrain)
1087{1087{
1088 UrmaChannelResource channel;1088 UrmaChannelResource channel;
1089 1089 
1090- AscendC::Hcomm<AscendC::COMM_PROTOCOL_UBC_CTP> hcomm;1090+ AscendC::Hcomm<AscendC::COMM_PROTOCOL_UB_CTP> hcomm;
1091 EXPECT_EQ(InitHcomm(hcomm), AscendC::HCOMM_SUCCESS);1091 EXPECT_EQ(InitHcomm(hcomm), AscendC::HCOMM_SUCCESS);
1092 1092 
1093 int32_t ret = hcomm.WriteNbi<false>(1093 int32_t ret = hcomm.WriteNbi<false>(
@@ -1111,7 +1111,7 @@ TEST_F(HcommUrmaTestSuite, Aiv_Urma_InitLocalTensor)
1111{1111{
1112 UrmaChannelResource channel;1112 UrmaChannelResource channel;
1113 1113 
1114- AscendC::Hcomm<AscendC::COMM_PROTOCOL_UBC_CTP> hcomm;1114+ AscendC::Hcomm<AscendC::COMM_PROTOCOL_UB_CTP> hcomm;
1115 1115 
1116 // Allocate buffer via TPipe and get LocalTensor1116 // Allocate buffer via TPipe and get LocalTensor
1117 AscendC::TPipe pipe;1117 AscendC::TPipe pipe;
@@ -1123,7 +1123,7 @@ TEST_F(HcommUrmaTestSuite, Aiv_Urma_InitLocalTensor)
1123 EXPECT_EQ(hcomm.Init(localBuf, AscendC::HCOMM_URMA_TMP_BUF_SIZE), AscendC::HCOMM_SUCCESS);1123 EXPECT_EQ(hcomm.Init(localBuf, AscendC::HCOMM_URMA_TMP_BUF_SIZE), AscendC::HCOMM_SUCCESS);
1124 1124 
1125 // Init with insufficient length should fail1125 // Init with insufficient length should fail
1126- AscendC::Hcomm<AscendC::COMM_PROTOCOL_UBC_CTP> hcomm2;1126+ AscendC::Hcomm<AscendC::COMM_PROTOCOL_UB_CTP> hcomm2;
1127 EXPECT_EQ(hcomm2.Init(localBuf, AscendC::HCOMM_URMA_TMP_BUF_SIZE - 1), AscendC::HCOMM_FAILED);1127 EXPECT_EQ(hcomm2.Init(localBuf, AscendC::HCOMM_URMA_TMP_BUF_SIZE - 1), AscendC::HCOMM_FAILED);
1128 1128 
1129 // Verify the initialized hcomm can perform operations1129 // Verify the initialized hcomm can perform operations