已合并
扩展pre-commit hooks (第一批目录) #4169
Water8L创建于 7月8日
扩展pre-commit hooks (第一批目录) #4169
已合并
共 876 个文件变更+1299-1323
| @@ -7,6 +7,24 @@ ci: | |||
| 7 | autoupdate_schedule: monthly | 7 | autoupdate_schedule: monthly |
| 8 | 8 | ||
| 9 | repos: | 9 | repos: |
| 10 | + # pre-commit 基础检查 | ||
| 11 | + - repo: https://gitcode.com/pre-commit/pre-commit-hooks | ||
| 12 | + rev: v4.6.0 | ||
| 13 | + hooks: | ||
| 14 | + - id: trailing-whitespace | ||
| 15 | + files: ^(tests/api/c_api/|include/adv_api/|include/basic_api/|impl/c_api/instr_impl/npu_arch_3510/|include/c_api/|impl/adv_api/(?!detail/(matmul|hccl)/)) | ||
| 16 | + exclude: \.md$ | ||
| 17 | + - id: end-of-file-fixer | ||
| 18 | + files: ^(tests/api/c_api/|include/adv_api/|include/basic_api/|impl/c_api/instr_impl/npu_arch_3510/|include/c_api/|impl/adv_api/(?!detail/(matmul|hccl)/)) | ||
| 19 | + exclude: \.md$ | ||
| 20 | + - id: check-yaml | ||
| 21 | + args: ["--allow-multiple-documents"] | ||
| 22 | + - id: check-added-large-files | ||
| 23 | + - id: check-merge-conflict | ||
| 24 | + - id: detect-private-key | ||
| 25 | + - id: check-json | ||
| 26 | + exclude: ^\.devcontainer/devcontainer\.json$ | ||
| 27 | + | ||
| 10 | # C++ 代码格式化检查 | 28 | # C++ 代码格式化检查 |
| 11 | - repo: https://gitcode.com/pre-commit-clang/mirrors-clang-format | 29 | - repo: https://gitcode.com/pre-commit-clang/mirrors-clang-format |
| 12 | rev: v18.1.8 | 30 | rev: v18.1.8 |
| @@ -99,7 +99,7 @@ if(NOT "${DPRODUCT_SIDE}" STREQUAL "device") | |||
| 99 | @ONLY | 99 | @ONLY |
| 100 | ) | 100 | ) |
| 101 | install(SCRIPT ${CMAKE_CURRENT_BINARY_DIR}/utils_headers.cmake COMPONENT asc-devkit) | 101 | install(SCRIPT ${CMAKE_CURRENT_BINARY_DIR}/utils_headers.cmake COMPONENT asc-devkit) |
| 102 | -endif() | 102 | +endif() |
| 103 | 103 | ||
| 104 | if (BUILD_OPEN_PROJECT) | 104 | if (BUILD_OPEN_PROJECT) |
| 105 | add_subdirectory(detail/hccl/cc) | 105 | add_subdirectory(detail/hccl/cc) |
| @@ -39,10 +39,3 @@ target_compile_options(intf_pub INTERFACE | |||
| 39 | target_link_libraries(intf_pub INTERFACE | 39 | target_link_libraries(intf_pub INTERFACE |
| 40 | $<BUILD_INTERFACE:intf_pub_base> | 40 | $<BUILD_INTERFACE:intf_pub_base> |
| 41 | ) | 41 | ) |
| 42 | - | ||
| 43 | - | ||
| 44 | - | ||
| 45 | - | ||
| 46 | - | ||
| 47 | - | ||
| 48 | - | ||
| @@ -30,7 +30,7 @@ function main() | |||
| 30 | 30 | ||
| 31 | cann_version=$(grep -w "Version" ${CANN_VERSION_INFO_FILE} | cut -d"=" -f2) | 31 | cann_version=$(grep -w "Version" ${CANN_VERSION_INFO_FILE} | cut -d"=" -f2) |
| 32 | local_version=$(grep -w "Version" ${CURRENT_VERSION_INFO_FILE} | cut -d"=" -f2) | 32 | local_version=$(grep -w "Version" ${CURRENT_VERSION_INFO_FILE} | cut -d"=" -f2) |
| 33 | - | 33 | + |
| 34 | _cann_version=$(echo ${cann_version} | cut -d'.' -f1-4) | 34 | _cann_version=$(echo ${cann_version} | cut -d'.' -f1-4) |
| 35 | _local_version=$(echo ${local_version} | cut -d'.' -f1-4) | 35 | _local_version=$(echo ${local_version} | cut -d'.' -f1-4) |
| 36 | 36 | ||
| @@ -43,9 +43,3 @@ function main() | |||
| 43 | } | 43 | } |
| 44 | 44 | ||
| 45 | main | 45 | main |
| 46 | - | ||
| 47 | - | ||
| 48 | - | ||
| 49 | - | ||
| 50 | - | ||
| 51 | - | ||
| @@ -111,7 +111,7 @@ if __name__ == '__main__': | |||
| 111 | if file.endswith("tilingdata.h"): | 111 | if file.endswith("tilingdata.h"): |
| 112 | file_list.append(os.path.join(root, file)) | 112 | file_list.append(os.path.join(root, file)) |
| 113 | file_list.sort() | 113 | file_list.sort() |
| 114 | - | 114 | + |
| 115 | tiling_source = "" | 115 | tiling_source = "" |
| 116 | legacy_tiling_export = "" | 116 | legacy_tiling_export = "" |
| 117 | for file in file_list: | 117 | for file in file_list: |
| @@ -127,4 +127,4 @@ __aicore__ inline void SwiGLUImpl( | |||
| 127 | 127 | ||
| 128 | 128 | ||
| 129 | 129 | ||
| 130 | -#endif | 130 | +#endif |
| @@ -229,4 +229,4 @@ __aicore__ inline void SwiGLUImpl<half>( | |||
| 229 | 229 | ||
| 230 | 230 | ||
| 231 | 231 | ||
| 232 | -#endif | 232 | +#endif |
| @@ -74,4 +74,4 @@ __aicore__ inline void SwishCompute( | |||
| 74 | 74 | ||
| 75 | 75 | ||
| 76 | 76 | ||
| 77 | -#endif | 77 | +#endif |
| @@ -109,4 +109,4 @@ __aicore__ inline __inout_pipe__(V) void SwishCompute( | |||
| 109 | 109 | ||
| 110 | 110 | ||
| 111 | 111 | ||
| 112 | -#endif | 112 | +#endif |
| @@ -70,4 +70,4 @@ private: | |||
| 70 | 70 | ||
| 71 | 71 | ||
| 72 | 72 | ||
| 73 | -#endif | 73 | +#endif |
| @@ -38,4 +38,4 @@ __aicore__ inline void CheckFuncBitwiseNot( | |||
| 38 | 38 | ||
| 39 | 39 | ||
| 40 | 40 | ||
| 41 | -#endif | 41 | +#endif |
| @@ -39,4 +39,4 @@ __aicore__ inline void CheckFuncBitwiseOr( | |||
| 39 | 39 | ||
| 40 | 40 | ||
| 41 | 41 | ||
| 42 | -#endif | 42 | +#endif |
| @@ -67,4 +67,4 @@ public: | |||
| 67 | 67 | ||
| 68 | 68 | ||
| 69 | 69 | ||
| 70 | -#endif | 70 | +#endif |
| @@ -39,4 +39,4 @@ __aicore__ inline void CheckFuncBitwiseXor( | |||
| 39 | 39 | ||
| 40 | 40 | ||
| 41 | 41 | ||
| 42 | -#endif | 42 | +#endif |
| @@ -67,4 +67,4 @@ public: | |||
| 67 | 67 | ||
| 68 | 68 | ||
| 69 | 69 | ||
| 70 | -#endif | 70 | +#endif |
| @@ -68,4 +68,4 @@ public: | |||
| 68 | 68 | ||
| 69 | 69 | ||
| 70 | 70 | ||
| 71 | -#endif | 71 | +#endif |
| @@ -72,4 +72,4 @@ __aicore__ inline void CheckTmpBufferSize( | |||
| 72 | 72 | ||
| 73 | 73 | ||
| 74 | 74 | ||
| 75 | -#endif | 75 | +#endif |
| @@ -34,4 +34,4 @@ constexpr Reg::CastTrait castTraitB32ToB16 = { | |||
| 34 | 34 | ||
| 35 | 35 | ||
| 36 | 36 | ||
| 37 | -#endif | 37 | +#endif |
| @@ -454,7 +454,7 @@ __aicore__ inline int32_t HcommImpl<COMM_PROTOCOL_UBC_CTP>::AtomicFAA( | |||
| 454 | ChannelHandle channel, GM_ADDR dst, GM_ADDR fetchAddr, T addVal) | 454 | ChannelHandle channel, GM_ADDR dst, GM_ADDR fetchAddr, T addVal) |
| 455 | { | 455 | { |
| 456 | static_assert( | 456 | static_assert( |
| 457 | - std::is_same<T, int32_t>::value || std::is_same<T, uint32_t>::value || | 457 | + std::is_same<T, int32_t>::value || std::is_same<T, uint32_t>::value || |
| 458 | std::is_same<T, int64_t>::value || std::is_same<T, uint64_t>::value, | 458 | std::is_same<T, int64_t>::value || std::is_same<T, uint64_t>::value, |
| 459 | "AtomicFAA only supports int32_t, uint32_t, int64_t, uint64_t" | 459 | "AtomicFAA only supports int32_t, uint32_t, int64_t, uint64_t" |
| 460 | ); | 460 | ); |
| @@ -467,7 +467,7 @@ __aicore__ inline int32_t HcommImpl<COMM_PROTOCOL_UBC_CTP>::AtomicCAS( | |||
| 467 | ChannelHandle channel, GM_ADDR dst, GM_ADDR fetchAddr, T compareVal, T swapVal) | 467 | ChannelHandle channel, GM_ADDR dst, GM_ADDR fetchAddr, T compareVal, T swapVal) |
| 468 | { | 468 | { |
| 469 | static_assert( | 469 | static_assert( |
| 470 | - std::is_same<T, int32_t>::value || std::is_same<T, uint32_t>::value || | 470 | + std::is_same<T, int32_t>::value || std::is_same<T, uint32_t>::value || |
| 471 | std::is_same<T, int64_t>::value || std::is_same<T, uint64_t>::value, | 471 | std::is_same<T, int64_t>::value || std::is_same<T, uint64_t>::value, |
| 472 | "AtomicCAS only supports int32_t, uint32_t, int64_t, uint64_t" | 472 | "AtomicCAS only supports int32_t, uint32_t, int64_t, uint64_t" |
| 473 | ); | 473 | ); |
| @@ -60,4 +60,4 @@ void LoggingSingleton::CheckLogLibFuncApi( | |||
| 60 | } // namespace UnifiedLog | 60 | } // namespace UnifiedLog |
| 61 | 61 | ||
| 62 | UnifiedLog::LoggingSingleton* logInstance = UnifiedLog::LoggingSingleton::getInstance(); | 62 | UnifiedLog::LoggingSingleton* logInstance = UnifiedLog::LoggingSingleton::getInstance(); |
| 63 | -} // namespace AscendC | 63 | +} // namespace AscendC |
| @@ -54,4 +54,4 @@ __aicore__ inline void CommonCheckInputsValidness( | |||
| 54 | 54 | ||
| 55 | 55 | ||
| 56 | 56 | ||
| 57 | -#endif | 57 | +#endif |
| @@ -50,4 +50,4 @@ constexpr float kCOEF[] = { | |||
| 50 | 50 | ||
| 51 | 51 | ||
| 52 | 52 | ||
| 53 | -#endif | 53 | +#endif |
| @@ -207,4 +207,4 @@ __aicore__ inline void RmsNormImpl( | |||
| 207 | 207 | ||
| 208 | 208 | ||
| 209 | 209 | ||
| 210 | -#endif | 210 | +#endif |
| @@ -319,4 +319,4 @@ __aicore__ inline void RmsNormImpl( | |||
| 319 | 319 | ||
| 320 | 320 | ||
| 321 | 321 | ||
| 322 | -#endif | 322 | +#endif |
| @@ -366,10 +366,10 @@ __aicore__ inline void TopKNSmallGetHalfTopKValue(const LocalTensor<T> &dstValue | |||
| 366 | SetFlag<HardEvent::V_S>(eventID); | 366 | SetFlag<HardEvent::V_S>(eventID); |
| 367 | WaitFlag<HardEvent::V_S>(eventID); | 367 | WaitFlag<HardEvent::V_S>(eventID); |
| 368 | SetVectorMask<T, MaskMode::COUNTER>(0, 2); | 368 | SetVectorMask<T, MaskMode::COUNTER>(0, 2); |
| 369 | - Duplicate<uint16_t, false>(src1stackTensor, static_cast<uint16_t>(tilling.vreduceValMask1), MASK_PLACEHOLDER, 1, 1, | 369 | + Duplicate<uint16_t, false>(src1stackTensor, static_cast<uint16_t>(tilling.vreduceValMask1), MASK_PLACEHOLDER, 1, 1, |
| 370 | DEFAULT_REPEAT_STRIDE); | 370 | DEFAULT_REPEAT_STRIDE); |
| 371 | SetVectorMask<T, MaskMode::COUNTER>(0, 1); | 371 | SetVectorMask<T, MaskMode::COUNTER>(0, 1); |
| 372 | - Duplicate<uint16_t, false>(src1stackTensor, static_cast<uint16_t>(tilling.vreduceValMask0), MASK_PLACEHOLDER, 1, 1, | 372 | + Duplicate<uint16_t, false>(src1stackTensor, static_cast<uint16_t>(tilling.vreduceValMask0), MASK_PLACEHOLDER, 1, 1, |
| 373 | DEFAULT_REPEAT_STRIDE); | 373 | DEFAULT_REPEAT_STRIDE); |
| 374 | PipeBarrier<PIPE_V>(); | 374 | PipeBarrier<PIPE_V>(); |
| 375 | SetMaskNorm(); | 375 | SetMaskNorm(); |
| @@ -377,13 +377,13 @@ __aicore__ inline void TopKNSmallGetHalfTopKValue(const LocalTensor<T> &dstValue | |||
| 377 | SetVectorMask<half>(topKInfo.inner); | 377 | SetVectorMask<half>(topKInfo.inner); |
| 378 | struct GatherMaskParams gatherMaskParams(DEFAULT_BLK_STRIDE, topKInfo.outter, ONE_FOURTH_DEFAULT_REPEAT_STRIDE, 0); | 378 | struct GatherMaskParams gatherMaskParams(DEFAULT_BLK_STRIDE, topKInfo.outter, ONE_FOURTH_DEFAULT_REPEAT_STRIDE, 0); |
| 379 | uint64_t rsvdCnt = 0; | 379 | uint64_t rsvdCnt = 0; |
| 380 | - GatherMask<half, uint16_t>(dstValueLocal, tmpLocal[tilling.innerDataSize], src1stackTensor, false, 0, | 380 | + GatherMask<half, uint16_t>(dstValueLocal, tmpLocal[tilling.innerDataSize], src1stackTensor, false, 0, |
| 381 | gatherMaskParams, rsvdCnt); | 381 | gatherMaskParams, rsvdCnt); |
| 382 | PipeBarrier<PIPE_V>(); | 382 | PipeBarrier<PIPE_V>(); |
| 383 | LocalTensor<uint32_t> indexStackTensor = tmpLocal.template ReinterpretCast<uint32_t>(); | 383 | LocalTensor<uint32_t> indexStackTensor = tmpLocal.template ReinterpretCast<uint32_t>(); |
| 384 | SetMaskCount(); | 384 | SetMaskCount(); |
| 385 | SetVectorMask<T, MaskMode::COUNTER>(0, 2); | 385 | SetVectorMask<T, MaskMode::COUNTER>(0, 2); |
| 386 | - Duplicate<uint32_t, false>(indexStackTensor, static_cast<uint32_t>(0), MASK_PLACEHOLDER, 1, 1, | 386 | + Duplicate<uint32_t, false>(indexStackTensor, static_cast<uint32_t>(0), MASK_PLACEHOLDER, 1, 1, |
| 387 | DEFAULT_REPEAT_STRIDE); | 387 | DEFAULT_REPEAT_STRIDE); |
| 388 | SetVectorMask<T, MaskMode::COUNTER>(0, 1); | 388 | SetVectorMask<T, MaskMode::COUNTER>(0, 1); |
| 389 | Duplicate<uint32_t, false>(indexStackTensor, static_cast<uint32_t>(tilling.vreduceIdxMask0), MASK_PLACEHOLDER, 1, 1, | 389 | Duplicate<uint32_t, false>(indexStackTensor, static_cast<uint32_t>(tilling.vreduceIdxMask0), MASK_PLACEHOLDER, 1, 1, |
| @@ -443,7 +443,7 @@ __aicore__ inline void CopyData(LocalTensor<int32_t> indexLocalTmp, const TopKIn | |||
| 443 | ResetMask(); | 443 | ResetMask(); |
| 444 | SetVectorMask<int32_t>(topKInfo.inner); | 444 | SetVectorMask<int32_t>(topKInfo.inner); |
| 445 | const UnaryRepeatParams unaryParams = {1, 1, 4, 0}; | 445 | const UnaryRepeatParams unaryParams = {1, 1, 4, 0}; |
| 446 | - Adds<int32_t, false>(indexLocalTmp[topKInfo.inner], indexLocalTmp, 0, MASK_PLACEHOLDER, topKInfo.outter - 1, | 446 | + Adds<int32_t, false>(indexLocalTmp[topKInfo.inner], indexLocalTmp, 0, MASK_PLACEHOLDER, topKInfo.outter - 1, |
| 447 | unaryParams); | 447 | unaryParams); |
| 448 | PipeBarrier<PIPE_V>(); | 448 | PipeBarrier<PIPE_V>(); |
| 449 | } | 449 | } |
| @@ -7,7 +7,7 @@ | |||
| 7 | # INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, MERCHANTABILITY, OR FITNESS FOR A PARTICULAR PURPOSE. | 7 | # INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, MERCHANTABILITY, OR FITNESS FOR A PARTICULAR PURPOSE. |
| 8 | # See LICENSE in the root of the software repository for the full text of the License. | 8 | # See LICENSE in the root of the software repository for the full text of the License. |
| 9 | # ---------------------------------------------------------------------------------------------------------- | 9 | # ---------------------------------------------------------------------------------------------------------- |
| 10 | -cmake_minimum_required(VERSION 3.16.0) | 10 | +cmake_minimum_required(VERSION 3.16.0) |
| 11 | project(ascendc_tiling_api) | 11 | project(ascendc_tiling_api) |
| 12 | 12 | ||
| 13 | add_library(tiling_api_headers INTERFACE) | 13 | add_library(tiling_api_headers INTERFACE) |
| @@ -30,7 +30,7 @@ target_include_directories( | |||
| 30 | $<INSTALL_INTERFACE:include/ascendc/include/highlevel_api/tiling>) | 30 | $<INSTALL_INTERFACE:include/ascendc/include/highlevel_api/tiling>) |
| 31 | 31 | ||
| 32 | target_link_libraries(tiling_api_headers | 32 | target_link_libraries(tiling_api_headers |
| 33 | - INTERFACE | 33 | + INTERFACE |
| 34 | $<BUILD_INTERFACE:metadef_headers> | 34 | $<BUILD_INTERFACE:metadef_headers> |
| 35 | $<BUILD_INTERFACE:unified_dlog> | 35 | $<BUILD_INTERFACE:unified_dlog> |
| 36 | $<BUILD_INTERFACE:tikcfw_headers>) | 36 | $<BUILD_INTERFACE:tikcfw_headers>) |
| @@ -175,7 +175,7 @@ target_compile_options( | |||
| 175 | $<$<STREQUAL:${PRODUCT_SIDE},device>:-fvisibility=hidden>) | 175 | $<$<STREQUAL:${PRODUCT_SIDE},device>:-fvisibility=hidden>) |
| 176 | 176 | ||
| 177 | target_compile_definitions( | 177 | target_compile_definitions( |
| 178 | - tiling_api PRIVATE | 178 | + tiling_api PRIVATE |
| 179 | $<$<STREQUAL:${PRODUCT_SIDE},device>:_FORTIFY_SOURCE=2> | 179 | $<$<STREQUAL:${PRODUCT_SIDE},device>:_FORTIFY_SOURCE=2> |
| 180 | $<$<STREQUAL:${PRODUCT_SIDE},device>:ASCENDC_DEVICE_REG_STATIC> | 180 | $<$<STREQUAL:${PRODUCT_SIDE},device>:ASCENDC_DEVICE_REG_STATIC> |
| 181 | ) | 181 | ) |
| @@ -921,4 +921,4 @@ void SoftMaxFlashV3TilingFunc( | |||
| 921 | tiling.SaveToBuffer(&softmaxFlashV3Tiling, sizeof(SoftMaxTiling)); | 921 | tiling.SaveToBuffer(&softmaxFlashV3Tiling, sizeof(SoftMaxTiling)); |
| 922 | } | 922 | } |
| 923 | 923 | ||
| 924 | -} // namespace AscendC | 924 | +} // namespace AscendC |
| @@ -253,4 +253,4 @@ typename std::enable_if<std::is_integral<T>::value, T>::type FloorAlign(T x, T a | |||
| 253 | } | 253 | } |
| 254 | 254 | ||
| 255 | } // namespace ConvBackpropApi | 255 | } // namespace ConvBackpropApi |
| 256 | -#endif // TILING_CONV_BACKPROP_CONV3D_BP_TILING_UTIL_H | 256 | +#endif // TILING_CONV_BACKPROP_CONV3D_BP_TILING_UTIL_H |
| @@ -70,4 +70,4 @@ void GetHypotTmpBufferFactorSize(const uint32_t typeSize, uint32_t& maxLiveNodeC | |||
| 70 | maxLiveNodeCount = 0; | 70 | maxLiveNodeCount = 0; |
| 71 | } | 71 | } |
| 72 | } | 72 | } |
| 73 | -} // namespace AscendC | 73 | +} // namespace AscendC |
| @@ -131,4 +131,4 @@ void GetSinMaxMinTmpSize( | |||
| 131 | minValue = sizeof(float) * inputSize * SIN_DOUBLE + SIN_EXTRA_BUF; | 131 | minValue = sizeof(float) * inputSize * SIN_DOUBLE + SIN_EXTRA_BUF; |
| 132 | } | 132 | } |
| 133 | } | 133 | } |
| 134 | -} // namespace AscendC | 134 | +} // namespace AscendC |
| @@ -59,4 +59,4 @@ public: | |||
| 59 | static std::pair<int32_t, int32_t> DivideIntoMainAndTail(int32_t num, int32_t divisor); | 59 | static std::pair<int32_t, int32_t> DivideIntoMainAndTail(int32_t num, int32_t divisor); |
| 60 | }; | 60 | }; |
| 61 | } // namespace matmul_tiling | 61 | } // namespace matmul_tiling |
| 62 | -#endif // _MATH_UTIL_H_ | 62 | +#endif // _MATH_UTIL_H_ |
| @@ -510,4 +510,4 @@ __aicore__ constexpr void GetMxMatmulApiTiling(MatmulApiStaticTiling& tiling, in | |||
| 510 | 510 | ||
| 511 | } | 511 | } |
| 512 | } // namespace AscendC | 512 | } // namespace AscendC |
| 513 | -#endif // _MATMUL_CONSTANT_TILING_IMPL_ | 513 | +#endif // _MATMUL_CONSTANT_TILING_IMPL_ |
| @@ -542,4 +542,4 @@ __aicore__ constexpr L1Status GetL1StatusNFirst(const L1Status& l1Status, const | |||
| 542 | return l1NFirst; | 542 | return l1NFirst; |
| 543 | } | 543 | } |
| 544 | } // namespace AscendC | 544 | } // namespace AscendC |
| 545 | -#endif // _MATMUL_CONSTANT_TILING_UTILS_H_ | 545 | +#endif // _MATMUL_CONSTANT_TILING_UTILS_H_ |
| @@ -219,4 +219,4 @@ __aicore__ constexpr MxScaleStatus GetMxScaleFactor(const MatmulApiStaticTiling& | |||
| 219 | return mxScaleFactor; | 219 | return mxScaleFactor; |
| 220 | } | 220 | } |
| 221 | } // namespace AscendC | 221 | } // namespace AscendC |
| 222 | -#endif // _MATMUL_CONSTANT_TILING_SHAPE_UTILS_H | 222 | +#endif // _MATMUL_CONSTANT_TILING_SHAPE_UTILS_H |
| @@ -569,4 +569,4 @@ private: | |||
| 569 | }; | 569 | }; |
| 570 | } // namespace matmul_tiling | 570 | } // namespace matmul_tiling |
| 571 | 571 | ||
| 572 | -#endif // _MATMUL_TILING_ALGORITHM_H | 572 | +#endif // _MATMUL_TILING_ALGORITHM_H |
| @@ -85,4 +85,4 @@ void GetNormalizeMaxMinTmpSize( | |||
| 85 | minValue = GetNormalizeMinTmpSize(aLength, rLengthWithPadding, typeSizeU); | 85 | minValue = GetNormalizeMinTmpSize(aLength, rLengthWithPadding, typeSizeU); |
| 86 | } | 86 | } |
| 87 | } | 87 | } |
| 88 | -} // namespace AscendC | 88 | +} // namespace AscendC |
| @@ -58,4 +58,4 @@ void GetWelfordFinalizeMaxMinTmpSize( | |||
| 58 | } | 58 | } |
| 59 | } | 59 | } |
| 60 | } | 60 | } |
| 61 | -} // namespace AscendC | 61 | +} // namespace AscendC |
| @@ -254,4 +254,4 @@ void UnPadTilingFunc( | |||
| 254 | UnPadTilingFunc(srcShape, stackBufferSize, typeSize, tilingData); | 254 | UnPadTilingFunc(srcShape, stackBufferSize, typeSize, tilingData); |
| 255 | tilingData.SaveToBuffer(&tiling, sizeof(UnPadTiling)); | 255 | tilingData.SaveToBuffer(&tiling, sizeof(UnPadTiling)); |
| 256 | } | 256 | } |
| 257 | -} // namespace AscendC | 257 | +} // namespace AscendC |
| @@ -24,7 +24,7 @@ | |||
| 24 | 24 | ||
| 25 | 25 | ||
| 26 | 26 | ||
| 27 | - | 27 | + |
| 28 | __aicore__ inline void asc_get_store_atomic_config_impl(asc_store_atomic_config& config) | 28 | __aicore__ inline void asc_get_store_atomic_config_impl(asc_store_atomic_config& config) |
| 29 | { | 29 | { |
| 30 | config.config = get_st_atomic_cfg(); | 30 | config.config = get_st_atomic_cfg(); |
| @@ -38,4 +38,3 @@ __aicore__ inline void asc_get_store_atomic_config_impl(asc_store_atomic_config& | |||
| 38 | 38 | ||
| 39 | 39 | ||
| 40 | 40 | ||
| 41 | - | ||
| @@ -39,4 +39,3 @@ __aicore__ inline void asc_set_atomic_add_bfloat_impl() | |||
| 39 | 39 | ||
| 40 | 40 | ||
| 41 | 41 | ||
| 42 | - | ||
| @@ -19,4 +19,4 @@ __aicore__ inline void asc_set_atomic_add_float16_impl() | |||
| 19 | set_atomic_f16(); | 19 | set_atomic_f16(); |
| 20 | } | 20 | } |
| 21 | 21 | ||
| 22 | -#endif | 22 | +#endif |
| @@ -36,4 +36,4 @@ __aicore__ inline void asc_set_atomic_add_float_impl() | |||
| 36 | 36 | ||
| 37 | 37 | ||
| 38 | 38 | ||
| 39 | -#endif | 39 | +#endif |
| @@ -36,4 +36,4 @@ __aicore__ inline void asc_set_atomic_add_int16_impl() | |||
| 36 | 36 | ||
| 37 | 37 | ||
| 38 | 38 | ||
| 39 | -#endif | 39 | +#endif |
| @@ -36,4 +36,4 @@ __aicore__ inline void asc_set_atomic_add_int_impl() | |||
| 36 | 36 | ||
| 37 | 37 | ||
| 38 | 38 | ||
| 39 | -#endif | 39 | +#endif |
| @@ -36,4 +36,4 @@ __aicore__ inline void asc_set_atomic_max_bfloat_impl() | |||
| 36 | 36 | ||
| 37 | 37 | ||
| 38 | 38 | ||
| 39 | -#endif | 39 | +#endif |
| @@ -36,4 +36,4 @@ __aicore__ inline void asc_set_atomic_max_float16_impl() | |||
| 36 | 36 | ||
| 37 | 37 | ||
| 38 | 38 | ||
| 39 | -#endif | 39 | +#endif |
| @@ -19,4 +19,4 @@ __aicore__ inline void asc_set_atomic_max_float_impl() | |||
| 19 | set_atomic_f32(); | 19 | set_atomic_f32(); |
| 20 | } | 20 | } |
| 21 | 21 | ||
| 22 | -#endif | 22 | +#endif |
| @@ -36,4 +36,4 @@ __aicore__ inline void asc_set_atomic_min_bfloat_impl() | |||
| 36 | 36 | ||
| 37 | 37 | ||
| 38 | 38 | ||
| 39 | -#endif | 39 | +#endif |
| @@ -36,4 +36,4 @@ __aicore__ inline void asc_set_atomic_min_float16_impl() | |||
| 36 | 36 | ||
| 37 | 37 | ||
| 38 | 38 | ||
| 39 | -#endif | 39 | +#endif |
| @@ -36,4 +36,4 @@ __aicore__ inline void asc_set_atomic_min_float_impl() | |||
| 36 | 36 | ||
| 37 | 37 | ||
| 38 | 38 | ||
| 39 | -#endif | 39 | +#endif |
| @@ -35,4 +35,4 @@ __aicore__ inline void asc_set_atomic_none_impl() | |||
| 35 | 35 | ||
| 36 | 36 | ||
| 37 | 37 | ||
| 38 | -#endif | 38 | +#endif |
| @@ -39,4 +39,4 @@ __aicore__ inline void asc_set_store_atomic_config_v2_impl(uint16_t type, uint16 | |||
| 39 | 39 | ||
| 40 | 40 | ||
| 41 | 41 | ||
| 42 | -#endif | 42 | +#endif |
| @@ -15,12 +15,11 @@ | |||
| 15 | 15 | ||
| 16 | 16 | ||
| 17 | 17 | ||
| 18 | - | 18 | + |
| 19 | 19 | ||
| 20 | 20 | ||
| 21 | __aicore__ inline void asc_datacache_preload_impl(__gm__ uint64_t* address, int64_t offset) | 21 | __aicore__ inline void asc_datacache_preload_impl(__gm__ uint64_t* address, int64_t offset) |
| 22 | { | 22 | { |
| 23 | dc_preload(address, offset); | 23 | dc_preload(address, offset); |
| 24 | } | 24 | } |
| 25 | -#endif | 25 | +#endif |
| 26 | - | ||
| @@ -12,17 +12,17 @@ | |||
| 12 | * \file asc_dcci_impl.h | 12 | * \file asc_dcci_impl.h |
| 13 | * \brief | 13 | * \brief |
| 14 | */ | 14 | */ |
| 15 | - | ||
| 16 | 15 | ||
| 17 | -#if !defined(ASCENDC_C_API_INCLUDE_COMPILER_INTERNAL_HEADERS) | 16 | + |
| 18 | -#warning "impl/c_api/instr_impl/npu_arch_3510/cache_ctrl_impl/asc_dcci_impl.h is an internal header file and must not be used directly. Functions or variables defined in this file maybe removed in the future. Please use "#include "c_api/asc_simd.h"" and use public functions or variables defined in interface headers files." | 17 | +#if !defined(ASCENDC_C_API_INCLUDE_COMPILER_INTERNAL_HEADERS) |
| 19 | -#define ASCENDC_C_API_INCLUDE_COMPILER_INTERNAL_HEADERS | 18 | +#warning "impl/c_api/instr_impl/npu_arch_3510/cache_ctrl_impl/asc_dcci_impl.h is an internal header file and must not be used directly. Functions or variables defined in this file maybe removed in the future. Please use "#include "c_api/asc_simd.h"" and use public functions or variables defined in interface headers files." |
| 20 | -#define UNDEF_ASCENDC_C_API_INCLUDE_COMPILER_INTERNAL_HEADERS_ASCENDC | 19 | +#define ASCENDC_C_API_INCLUDE_COMPILER_INTERNAL_HEADERS |
| 21 | -#endif | 20 | +#define UNDEF_ASCENDC_C_API_INCLUDE_COMPILER_INTERNAL_HEADERS_ASCENDC |
| 21 | + | ||
| 22 | 22 | ||
| 23 | 23 | ||
| 24 | 24 | ||
| 25 | - | 25 | + |
| 26 | 26 | ||
| 27 | 27 | ||
| 28 | namespace __asc_aicore { | 28 | namespace __asc_aicore { |
| @@ -54,7 +54,7 @@ __aicore__ inline void asc_dcci_entire_atomic_impl() | |||
| 54 | 54 | ||
| 55 | 55 | ||
| 56 | 56 | ||
| 57 | -#if defined(UNDEF_ASCENDC_C_API_INCLUDE_COMPILER_INTERNAL_HEADERS_ASCENDC) | 57 | +#if defined(UNDEF_ASCENDC_C_API_INCLUDE_COMPILER_INTERNAL_HEADERS_ASCENDC) |
| 58 | -#undef ASCENDC_C_API_INCLUDE_COMPILER_INTERNAL_HEADERS | 58 | +#undef ASCENDC_C_API_INCLUDE_COMPILER_INTERNAL_HEADERS |
| 59 | -#undef UNDEF_ASCENDC_C_API_INCLUDE_COMPILER_INTERNAL_HEADERS_ASCENDC | 59 | +#undef UNDEF_ASCENDC_C_API_INCLUDE_COMPILER_INTERNAL_HEADERS_ASCENDC |
| 60 | -#endif | 60 | +#endif |
| @@ -9,11 +9,11 @@ | |||
| 9 | */ | 9 | */ |
| 10 | 10 | ||
| 11 | 11 | ||
| 12 | -#if !defined(ASCENDC_C_API_INCLUDE_COMPILER_INTERNAL_HEADERS) | 12 | +#if !defined(ASCENDC_C_API_INCLUDE_COMPILER_INTERNAL_HEADERS) |
| 13 | -#warning "impl/c_api/instr_impl/npu_arch_3510/cache_ctrl_impl/asc_get_icache_preload_status_impl.h is an internal header file and must not be used directly. Functions or variables defined in this file maybe removed in the future. Please use "#include "c_api/asc_simd.h"" and use public functions or variables defined in interface headers files." | 13 | +#warning "impl/c_api/instr_impl/npu_arch_3510/cache_ctrl_impl/asc_get_icache_preload_status_impl.h is an internal header file and must not be used directly. Functions or variables defined in this file maybe removed in the future. Please use "#include "c_api/asc_simd.h"" and use public functions or variables defined in interface headers files." |
| 14 | -#define ASCENDC_C_API_INCLUDE_COMPILER_INTERNAL_HEADERS | 14 | +#define ASCENDC_C_API_INCLUDE_COMPILER_INTERNAL_HEADERS |
| 15 | -#define UNDEF_ASCENDC_C_API_INCLUDE_COMPILER_INTERNAL_HEADERS_ASCENDC | 15 | +#define UNDEF_ASCENDC_C_API_INCLUDE_COMPILER_INTERNAL_HEADERS_ASCENDC |
| 16 | -#endif | 16 | +#endif |
| 17 | 17 | ||
| 18 | 18 | ||
| 19 | 19 | ||
| @@ -27,8 +27,7 @@ __aicore__ inline int64_t asc_get_icache_preload_status_impl() | |||
| 27 | 27 | ||
| 28 | 28 | ||
| 29 | 29 | ||
| 30 | -#if defined(UNDEF_ASCENDC_C_API_INCLUDE_COMPILER_INTERNAL_HEADERS_ASCENDC) | 30 | +#if defined(UNDEF_ASCENDC_C_API_INCLUDE_COMPILER_INTERNAL_HEADERS_ASCENDC) |
| 31 | -#undef ASCENDC_C_API_INCLUDE_COMPILER_INTERNAL_HEADERS | 31 | +#undef ASCENDC_C_API_INCLUDE_COMPILER_INTERNAL_HEADERS |
| 32 | -#undef UNDEF_ASCENDC_C_API_INCLUDE_COMPILER_INTERNAL_HEADERS_ASCENDC | 32 | +#undef UNDEF_ASCENDC_C_API_INCLUDE_COMPILER_INTERNAL_HEADERS_ASCENDC |
| 33 | -#endif | 33 | +#endif |
| 34 | - | ||
| @@ -18,4 +18,4 @@ __aicore__ inline void asc_icache_preload_impl(const void* addr, int64_t prefetc | |||
| 18 | preload(addr, prefetch_len); | 18 | preload(addr, prefetch_len); |
| 19 | } | 19 | } |
| 20 | 20 | ||
| 21 | -#endif | 21 | +#endif |
| @@ -9,11 +9,11 @@ | |||
| 9 | */ | 9 | */ |
| 10 | 10 | ||
| 11 | 11 | ||
| 12 | -#if !defined(ASCENDC_C_API_INCLUDE_COMPILER_INTERNAL_HEADERS) | 12 | +#if !defined(ASCENDC_C_API_INCLUDE_COMPILER_INTERNAL_HEADERS) |
| 13 | -#warning "c_api/instr_impl/cube_compute_impl/asc_set_l0c2gm_config_impl.h is an internal header file and must not be used directly. Functions or variables defined in this file maybe removed in the future. Please use "#include "c_api/asc_simd.h"" and use public functions or variables defined in interface headers files." | 13 | +#warning "c_api/instr_impl/cube_compute_impl/asc_set_l0c2gm_config_impl.h is an internal header file and must not be used directly. Functions or variables defined in this file maybe removed in the future. Please use "#include "c_api/asc_simd.h"" and use public functions or variables defined in interface headers files." |
| 14 | -#define ASCENDC_C_API_INCLUDE_COMPILER_INTERNAL_HEADERS | 14 | +#define ASCENDC_C_API_INCLUDE_COMPILER_INTERNAL_HEADERS |
| 15 | -#define UNDEF_ASCENDC_C_API_INCLUDE_COMPILER_INTERNAL_HEADERS_ASCENDC | 15 | +#define UNDEF_ASCENDC_C_API_INCLUDE_COMPILER_INTERNAL_HEADERS_ASCENDC |
| 16 | -#endif | 16 | +#endif |
| 17 | 17 | ||
| 18 | 18 | ||
| 19 | 19 | ||
| @@ -21,7 +21,7 @@ | |||
| 21 | 21 | ||
| 22 | 22 | ||
| 23 | __aicore__ inline void asc_set_l0c2gm_config_impl(uint64_t relu_pre, uint64_t quant_pre, bool enable_unit_flag) | 23 | __aicore__ inline void asc_set_l0c2gm_config_impl(uint64_t relu_pre, uint64_t quant_pre, bool enable_unit_flag) |
| 24 | -{ | 24 | +{ |
| 25 | if ASC_IS_AIC { | 25 | if ASC_IS_AIC { |
| 26 | asc_capi_fpc_reg_config config; | 26 | asc_capi_fpc_reg_config config; |
| 27 | config.config = 0; | 27 | config.config = 0; |
| @@ -34,7 +34,7 @@ __aicore__ inline void asc_set_l0c2gm_config_impl(uint64_t relu_pre, uint64_t qu | |||
| 34 | 34 | ||
| 35 | 35 | ||
| 36 | 36 | ||
| 37 | -#if defined(UNDEF_ASCENDC_C_API_INCLUDE_COMPILER_INTERNAL_HEADERS_ASCENDC) | 37 | +#if defined(UNDEF_ASCENDC_C_API_INCLUDE_COMPILER_INTERNAL_HEADERS_ASCENDC) |
| 38 | -#undef ASCENDC_C_API_INCLUDE_COMPILER_INTERNAL_HEADERS | 38 | +#undef ASCENDC_C_API_INCLUDE_COMPILER_INTERNAL_HEADERS |
| 39 | -#undef UNDEF_ASCENDC_C_API_INCLUDE_COMPILER_INTERNAL_HEADERS_ASCENDC | 39 | +#undef UNDEF_ASCENDC_C_API_INCLUDE_COMPILER_INTERNAL_HEADERS_ASCENDC |
| 40 | -#endif | 40 | +#endif |
| @@ -1017,7 +1017,7 @@ __aicore__ inline void asc_copy_l12l0b_trans_sync(__cb__ int32_t* dst, __cbuf__ | |||
| 1017 | __aicore__ inline void asc_copy_l12l0b_trans(__cb__ int8_t* dst, __cbuf__ int8_t* src, uint16_t index_id, uint8_t repeat, uint16_t src_stride, | 1017 | __aicore__ inline void asc_copy_l12l0b_trans(__cb__ int8_t* dst, __cbuf__ int8_t* src, uint16_t index_id, uint8_t repeat, uint16_t src_stride, |
| 1018 | uint16_t dst_gap, uint16_t dst_frac_gap, uint16_t src_frac_gap) | 1018 | uint16_t dst_gap, uint16_t dst_frac_gap, uint16_t src_frac_gap) |
| 1019 | { | 1019 | { |
| 1020 | - asc_copy_l12l0b_trans_impl(dst, src, index_id, repeat, src_stride, dst_gap, dst_frac_gap, src_frac_gap); | 1020 | + asc_copy_l12l0b_trans_impl(dst, src, index_id, repeat, src_stride, dst_gap, dst_frac_gap, src_frac_gap); |
| 1021 | } | 1021 | } |
| 1022 | 1022 | ||
| 1023 | __aicore__ inline void asc_copy_l12l0b_trans_sync(__cb__ int8_t* dst, __cbuf__ int8_t* src, uint16_t index_id, uint8_t repeat, uint16_t src_stride, | 1023 | __aicore__ inline void asc_copy_l12l0b_trans_sync(__cb__ int8_t* dst, __cbuf__ int8_t* src, uint16_t index_id, uint8_t repeat, uint16_t src_stride, |
| @@ -45,4 +45,4 @@ __aicore__ inline void asc_copy_l12l0a_mx_sync_impl(uint64_t dst, __cbuf__ fp8_e | |||
| 45 | 45 | ||
| 46 | 46 | ||
| 47 | 47 | ||
| 48 | -#endif | 48 | +#endif |
| @@ -45,4 +45,4 @@ __aicore__ inline void asc_copy_l12l0b_mx_sync_impl(uint64_t dst, __cbuf__ fp8_e | |||
| 45 | 45 | ||
| 46 | 46 | ||
| 47 | 47 | ||
| 48 | -#endif | 48 | +#endif |
| @@ -32,4 +32,4 @@ __aicore__ inline void asc_set_l0c_copy_prequant_impl(uint64_t config) | |||
| 32 | 32 | ||
| 33 | 33 | ||
| 34 | 34 | ||
| 35 | -#endif | 35 | +#endif |
| @@ -18,4 +18,4 @@ __aicore__ inline void asc_init() | |||
| 18 | asc_init_soc_state_impl(); | 18 | asc_init_soc_state_impl(); |
| 19 | } | 19 | } |
| 20 | 20 | ||
| 21 | -#endif | 21 | +#endif |
| @@ -27,10 +27,10 @@ __aicore__ inline void asc_init_soc_state_impl() | |||
| 27 | set_vector_mask(static_cast<uint64_t>(-1), static_cast<uint64_t>(-1)); | 27 | set_vector_mask(static_cast<uint64_t>(-1), static_cast<uint64_t>(-1)); |
| 28 | } | 28 | } |
| 29 | } | 29 | } |
| 30 | - | 30 | + |
| 31 | 31 | ||
| 32 | 32 | ||
| 33 | 33 | ||
| 34 | 34 | ||
| 35 | 35 | ||
| 36 | -#endif | 36 | +#endif |
| @@ -18,4 +18,4 @@ __aicore__ inline int64_t asc_clz_impl(uint64_t value_in) | |||
| 18 | return clz(value_in); | 18 | return clz(value_in); |
| 19 | } | 19 | } |
| 20 | 20 | ||
| 21 | -#endif | 21 | +#endif |
| @@ -29,4 +29,4 @@ __aicore__ inline int64_t asc_ffs_impl(uint64_t value) | |||
| 29 | 29 | ||
| 30 | 30 | ||
| 31 | 31 | ||
| 32 | -#endif | 32 | +#endif |
| @@ -33,4 +33,4 @@ __aicore__ inline int32_t asc_float2int32_rna_impl(float value) | |||
| 33 | return conv_f322s32a(value); | 33 | return conv_f322s32a(value); |
| 34 | } | 34 | } |
| 35 | 35 | ||
| 36 | -#endif | 36 | +#endif |
| @@ -36,4 +36,3 @@ __aicore__ inline int64_t asc_zero_bits_cnt_impl(uint64_t value) | |||
| 36 | 36 | ||
| 37 | 37 | ||
| 38 | 38 | ||
| 39 | - | ||
| @@ -32,4 +32,4 @@ | |||
| 32 | 32 | ||
| 33 | 33 | ||
| 34 | 34 | ||
| 35 | -#endif | 35 | +#endif |
| @@ -32,4 +32,4 @@ | |||
| 32 | 32 | ||
| 33 | 33 | ||
| 34 | 34 | ||
| 35 | -#endif | 35 | +#endif |
| @@ -40,4 +40,4 @@ __aicore__ inline int64_t asc_get_squeeze_status_impl() | |||
| 40 | 40 | ||
| 41 | 41 | ||
| 42 | 42 | ||
| 43 | -#endif | 43 | +#endif |
| @@ -35,4 +35,4 @@ __aicore__ inline int64_t asc_get_block_num_impl() | |||
| 35 | 35 | ||
| 36 | 36 | ||
| 37 | 37 | ||
| 38 | -#endif | 38 | +#endif |
| @@ -9,11 +9,11 @@ | |||
| 9 | */ | 9 | */ |
| 10 | 10 | ||
| 11 | 11 | ||
| 12 | -#if !defined(ASCENDC_C_API_INCLUDE_COMPILER_INTERNAL_HEADERS) | 12 | +#if !defined(ASCENDC_C_API_INCLUDE_COMPILER_INTERNAL_HEADERS) |
| 13 | -#warning "impl/c_api/instr_impl/npu_arch_3510/sys_var_impl/asc_get_ctrl_impl.h is an internal header file and must not be used directly. Functions or variables defined in this file maybe removed in the future. Please use "#include "c_api/asc_simd.h"" and use public functions or variables defined in interface headers files." | 13 | +#warning "impl/c_api/instr_impl/npu_arch_3510/sys_var_impl/asc_get_ctrl_impl.h is an internal header file and must not be used directly. Functions or variables defined in this file maybe removed in the future. Please use "#include "c_api/asc_simd.h"" and use public functions or variables defined in interface headers files." |
| 14 | -#define ASCENDC_C_API_INCLUDE_COMPILER_INTERNAL_HEADERS | 14 | +#define ASCENDC_C_API_INCLUDE_COMPILER_INTERNAL_HEADERS |
| 15 | -#define UNDEF_ASCENDC_C_API_INCLUDE_COMPILER_INTERNAL_HEADERS_ASCENDC | 15 | +#define UNDEF_ASCENDC_C_API_INCLUDE_COMPILER_INTERNAL_HEADERS_ASCENDC |
| 16 | -#endif | 16 | +#endif |
| 17 | 17 | ||
| 18 | 18 | ||
| 19 | 19 | ||
| @@ -27,8 +27,7 @@ __aicore__ inline int64_t asc_get_ctrl_impl() | |||
| 27 | 27 | ||
| 28 | 28 | ||
| 29 | 29 | ||
| 30 | -#if defined(UNDEF_ASCENDC_C_API_INCLUDE_COMPILER_INTERNAL_HEADERS_ASCENDC) | 30 | +#if defined(UNDEF_ASCENDC_C_API_INCLUDE_COMPILER_INTERNAL_HEADERS_ASCENDC) |
| 31 | -#undef ASCENDC_C_API_INCLUDE_COMPILER_INTERNAL_HEADERS | 31 | +#undef ASCENDC_C_API_INCLUDE_COMPILER_INTERNAL_HEADERS |
| 32 | -#undef UNDEF_ASCENDC_C_API_INCLUDE_COMPILER_INTERNAL_HEADERS_ASCENDC | 32 | +#undef UNDEF_ASCENDC_C_API_INCLUDE_COMPILER_INTERNAL_HEADERS_ASCENDC |
| 33 | -#endif | 33 | +#endif |
| 34 | - | ||
| @@ -9,11 +9,11 @@ | |||
| 9 | */ | 9 | */ |
| 10 | 10 | ||
| 11 | 11 | ||
| 12 | -#if !defined(ASCENDC_C_API_INCLUDE_COMPILER_INTERNAL_HEADERS) | 12 | +#if !defined(ASCENDC_C_API_INCLUDE_COMPILER_INTERNAL_HEADERS) |
| 13 | -#warning "impl/c_api/instr_impl/npu_arch_3510/sys_var_impl/asc_get_phy_buf_addr_impl.h is an internal header file and must not be used directly. Functions or variables defined in this file maybe removed in the future. Please use "#include "c_api/asc_simd.h"" and use public functions or variables defined in interface headers files." | 13 | +#warning "impl/c_api/instr_impl/npu_arch_3510/sys_var_impl/asc_get_phy_buf_addr_impl.h is an internal header file and must not be used directly. Functions or variables defined in this file maybe removed in the future. Please use "#include "c_api/asc_simd.h"" and use public functions or variables defined in interface headers files." |
| 14 | -#define ASCENDC_C_API_INCLUDE_COMPILER_INTERNAL_HEADERS | 14 | +#define ASCENDC_C_API_INCLUDE_COMPILER_INTERNAL_HEADERS |
| 15 | -#define UNDEF_ASCENDC_C_API_INCLUDE_COMPILER_INTERNAL_HEADERS_ASCENDC | 15 | +#define UNDEF_ASCENDC_C_API_INCLUDE_COMPILER_INTERNAL_HEADERS_ASCENDC |
| 16 | -#endif | 16 | +#endif |
| 17 | 17 | ||
| 18 | 18 | ||
| 19 | 19 | ||
| @@ -27,8 +27,7 @@ __aicore__ inline uint64_t asc_get_phy_buf_addr_impl(uint64_t offset) | |||
| 27 | 27 | ||
| 28 | 28 | ||
| 29 | 29 | ||
| 30 | -#if defined(UNDEF_ASCENDC_C_API_INCLUDE_COMPILER_INTERNAL_HEADERS_ASCENDC) | 30 | +#if defined(UNDEF_ASCENDC_C_API_INCLUDE_COMPILER_INTERNAL_HEADERS_ASCENDC) |
| 31 | -#undef ASCENDC_C_API_INCLUDE_COMPILER_INTERNAL_HEADERS | 31 | +#undef ASCENDC_C_API_INCLUDE_COMPILER_INTERNAL_HEADERS |
| 32 | -#undef UNDEF_ASCENDC_C_API_INCLUDE_COMPILER_INTERNAL_HEADERS_ASCENDC | 32 | +#undef UNDEF_ASCENDC_C_API_INCLUDE_COMPILER_INTERNAL_HEADERS_ASCENDC |
| 33 | -#endif | 33 | +#endif |
| 34 | - | ||
| @@ -35,4 +35,4 @@ __aicore__ inline int64_t asc_get_phy_stack_base_impl() | |||
| 35 | 35 | ||
| 36 | 36 | ||
| 37 | 37 | ||
| 38 | -#endif | 38 | +#endif |
| @@ -18,4 +18,4 @@ __aicore__ inline int64_t asc_get_program_counter_impl() | |||
| 18 | return get_pc(); | 18 | return get_pc(); |
| 19 | } | 19 | } |
| 20 | 20 | ||
| 21 | -#endif | 21 | +#endif |
| @@ -35,4 +35,4 @@ __aicore__ inline int64_t asc_get_smmu_tag_version_impl() | |||
| 35 | 35 | ||
| 36 | 36 | ||
| 37 | 37 | ||
| 38 | -#endif | 38 | +#endif |
| @@ -35,4 +35,4 @@ __aicore__ inline int64_t asc_get_status_impl() | |||
| 35 | 35 | ||
| 36 | 36 | ||
| 37 | 37 | ||
| 38 | -#endif | 38 | +#endif |
| @@ -35,4 +35,4 @@ __aicore__ inline int64_t asc_get_sys_virtual_base_impl() | |||
| 35 | 35 | ||
| 36 | 36 | ||
| 37 | 37 | ||
| 38 | -#endif | 38 | +#endif |
| @@ -35,4 +35,4 @@ __aicore__ inline int64_t asc_get_system_cycle_impl() | |||
| 35 | 35 | ||
| 36 | 36 | ||
| 37 | 37 | ||
| 38 | -#endif | 38 | +#endif |
| @@ -29,4 +29,4 @@ __aicore__ inline void asc_set_ctrl_impl(uint64_t config) | |||
| 29 | 29 | ||
| 30 | 30 | ||
| 31 | 31 | ||
| 32 | -#endif | 32 | +#endif |
| @@ -21,7 +21,7 @@ | |||
| 21 | 21 | ||
| 22 | 22 | ||
| 23 | __aicore__ inline void asc_set_l12l0_padding_val_impl(uint64_t config) | 23 | __aicore__ inline void asc_set_l12l0_padding_val_impl(uint64_t config) |
| 24 | -{ | 24 | +{ |
| 25 | if ASC_IS_AIC { | 25 | if ASC_IS_AIC { |
| 26 | set_padding_b(config); | 26 | set_padding_b(config); |
| 27 | } | 27 | } |
| @@ -14,4 +14,4 @@ | |||
| 14 | 14 | ||
| 15 | 15 | ||
| 16 | 16 | ||
| 17 | -#endif | 17 | +#endif |
| @@ -39,7 +39,7 @@ using vector_fp4x2_e1m2_t = vector_f4e1m2x2; | |||
| 39 | using vector_store_unalign = vector_align; | 39 | using vector_store_unalign = vector_align; |
| 40 | using vector_load_unalign = vector_align; | 40 | using vector_load_unalign = vector_align; |
| 41 | using addr_reg = vector_address; | 41 | using addr_reg = vector_address; |
| 42 | -// iter_reg has been deprecated, please use addr_reg instead. | 42 | +// iter_reg has been deprecated, please use addr_reg instead. |
| 43 | -using iter_reg [[deprecated("iter_reg has been deprecated, please use addr_reg instead.")]] = addr_reg; | 43 | +using iter_reg [[deprecated("iter_reg has been deprecated, please use addr_reg instead.")]] = addr_reg; |
| 44 | 44 | ||
| 45 | -#endif | 45 | +#endif |
| @@ -1886,84 +1886,84 @@ __simd_callee__ inline void asc_squeeze_v2(vector_uint8_t& dst, vector_uint8_t s | |||
| 1886 | "Please use asc_squeeze_with_status instead.")]] | 1886 | "Please use asc_squeeze_with_status instead.")]] |
| 1887 | __simd_callee__ inline void asc_squeeze_v2(vector_int8_t& dst, vector_int8_t src, vector_bool mask) | 1887 | __simd_callee__ inline void asc_squeeze_v2(vector_int8_t& dst, vector_int8_t src, vector_bool mask) |
| 1888 | { | 1888 | { |
| 1889 | - asc_squeeze_v2_impl(dst, src, mask); | 1889 | + asc_squeeze_v2_impl(dst, src, mask); |
| 1890 | } | 1890 | } |
| 1891 | 1891 | ||
| 1892 | [[deprecated("NOTICE: asc_squeeze_v2 is deprecated. " | 1892 | [[deprecated("NOTICE: asc_squeeze_v2 is deprecated. " |
| 1893 | "Please use asc_squeeze_with_status instead.")]] | 1893 | "Please use asc_squeeze_with_status instead.")]] |
| 1894 | __simd_callee__ inline void asc_squeeze_v2(vector_uint16_t& dst, vector_uint16_t src, vector_bool mask) | 1894 | __simd_callee__ inline void asc_squeeze_v2(vector_uint16_t& dst, vector_uint16_t src, vector_bool mask) |
| 1895 | { | 1895 | { |
| 1896 | - asc_squeeze_v2_impl(dst, src, mask); | 1896 | + asc_squeeze_v2_impl(dst, src, mask); |
| 1897 | } | 1897 | } |
| 1898 | 1898 | ||
| 1899 | [[deprecated("NOTICE: asc_squeeze_v2 is deprecated. " | 1899 | [[deprecated("NOTICE: asc_squeeze_v2 is deprecated. " |
| 1900 | "Please use asc_squeeze_with_status instead.")]] | 1900 | "Please use asc_squeeze_with_status instead.")]] |
| 1901 | __simd_callee__ inline void asc_squeeze_v2(vector_int16_t& dst, vector_int16_t src, vector_bool mask) | 1901 | __simd_callee__ inline void asc_squeeze_v2(vector_int16_t& dst, vector_int16_t src, vector_bool mask) |
| 1902 | { | 1902 | { |
| 1903 | - asc_squeeze_v2_impl(dst, src, mask); | 1903 | + asc_squeeze_v2_impl(dst, src, mask); |
| 1904 | } | 1904 | } |
| 1905 | 1905 | ||
| 1906 | [[deprecated("NOTICE: asc_squeeze_v2 is deprecated. " | 1906 | [[deprecated("NOTICE: asc_squeeze_v2 is deprecated. " |
| 1907 | "Please use asc_squeeze_with_status instead.")]] | 1907 | "Please use asc_squeeze_with_status instead.")]] |
| 1908 | __simd_callee__ inline void asc_squeeze_v2(vector_uint32_t& dst, vector_uint32_t src, vector_bool mask) | 1908 | __simd_callee__ inline void asc_squeeze_v2(vector_uint32_t& dst, vector_uint32_t src, vector_bool mask) |
| 1909 | { | 1909 | { |
| 1910 | - asc_squeeze_v2_impl(dst, src, mask); | 1910 | + asc_squeeze_v2_impl(dst, src, mask); |
| 1911 | } | 1911 | } |
| 1912 | 1912 | ||
| 1913 | [[deprecated("NOTICE: asc_squeeze_v2 is deprecated. " | 1913 | [[deprecated("NOTICE: asc_squeeze_v2 is deprecated. " |
| 1914 | "Please use asc_squeeze_with_status instead.")]] | 1914 | "Please use asc_squeeze_with_status instead.")]] |
| 1915 | __simd_callee__ inline void asc_squeeze_v2(vector_int32_t& dst, vector_int32_t src, vector_bool mask) | 1915 | __simd_callee__ inline void asc_squeeze_v2(vector_int32_t& dst, vector_int32_t src, vector_bool mask) |
| 1916 | { | 1916 | { |
| 1917 | - asc_squeeze_v2_impl(dst, src, mask); | 1917 | + asc_squeeze_v2_impl(dst, src, mask); |
| 1918 | } | 1918 | } |
| 1919 | 1919 | ||
| 1920 | [[deprecated("NOTICE: asc_squeeze_v2 is deprecated. " | 1920 | [[deprecated("NOTICE: asc_squeeze_v2 is deprecated. " |
| 1921 | "Please use asc_squeeze_with_status instead.")]] | 1921 | "Please use asc_squeeze_with_status instead.")]] |
| 1922 | __simd_callee__ inline void asc_squeeze_v2(vector_half& dst, vector_half src, vector_bool mask) | 1922 | __simd_callee__ inline void asc_squeeze_v2(vector_half& dst, vector_half src, vector_bool mask) |
| 1923 | { | 1923 | { |
| 1924 | - asc_squeeze_v2_impl(dst, src, mask); | 1924 | + asc_squeeze_v2_impl(dst, src, mask); |
| 1925 | } | 1925 | } |
| 1926 | 1926 | ||
| 1927 | [[deprecated("NOTICE: asc_squeeze_v2 is deprecated. " | 1927 | [[deprecated("NOTICE: asc_squeeze_v2 is deprecated. " |
| 1928 | "Please use asc_squeeze_with_status instead.")]] | 1928 | "Please use asc_squeeze_with_status instead.")]] |
| 1929 | __simd_callee__ inline void asc_squeeze_v2(vector_float& dst, vector_float src, vector_bool mask) | 1929 | __simd_callee__ inline void asc_squeeze_v2(vector_float& dst, vector_float src, vector_bool mask) |
| 1930 | { | 1930 | { |
| 1931 | - asc_squeeze_v2_impl(dst, src, mask); | 1931 | + asc_squeeze_v2_impl(dst, src, mask); |
| 1932 | } | 1932 | } |
| 1933 | 1933 | ||
| 1934 | [[deprecated("NOTICE: asc_squeeze_v2 is deprecated. " | 1934 | [[deprecated("NOTICE: asc_squeeze_v2 is deprecated. " |
| 1935 | "Please use asc_squeeze_with_status instead.")]] | 1935 | "Please use asc_squeeze_with_status instead.")]] |
| 1936 | __simd_callee__ inline void asc_squeeze_v2(vector_bfloat16_t& dst, vector_bfloat16_t src, vector_bool mask) | 1936 | __simd_callee__ inline void asc_squeeze_v2(vector_bfloat16_t& dst, vector_bfloat16_t src, vector_bool mask) |
| 1937 | { | 1937 | { |
| 1938 | - asc_squeeze_v2_impl(dst, src, mask); | 1938 | + asc_squeeze_v2_impl(dst, src, mask); |
| 1939 | } | 1939 | } |
| 1940 | 1940 | ||
| 1941 | [[deprecated("NOTICE: asc_squeeze_v2 is deprecated. " | 1941 | [[deprecated("NOTICE: asc_squeeze_v2 is deprecated. " |
| 1942 | "Please use asc_squeeze_with_status instead.")]] | 1942 | "Please use asc_squeeze_with_status instead.")]] |
| 1943 | __simd_callee__ inline void asc_squeeze_v2(vector_hifloat8_t& dst, vector_hifloat8_t src, vector_bool mask) | 1943 | __simd_callee__ inline void asc_squeeze_v2(vector_hifloat8_t& dst, vector_hifloat8_t src, vector_bool mask) |
| 1944 | { | 1944 | { |
| 1945 | - asc_squeeze_v2_impl(dst, src, mask); | 1945 | + asc_squeeze_v2_impl(dst, src, mask); |
| 1946 | } | 1946 | } |
| 1947 | 1947 | ||
| 1948 | [[deprecated("NOTICE: asc_squeeze_v2 is deprecated. " | 1948 | [[deprecated("NOTICE: asc_squeeze_v2 is deprecated. " |
| 1949 | "Please use asc_squeeze_with_status instead.")]] | 1949 | "Please use asc_squeeze_with_status instead.")]] |
| 1950 | __simd_callee__ inline void asc_squeeze_v2(vector_fp8_e4m3fn_t& dst, vector_fp8_e4m3fn_t src, vector_bool mask) | 1950 | __simd_callee__ inline void asc_squeeze_v2(vector_fp8_e4m3fn_t& dst, vector_fp8_e4m3fn_t src, vector_bool mask) |
| 1951 | { | 1951 | { |
| 1952 | - asc_squeeze_v2_impl(dst, src, mask); | 1952 | + asc_squeeze_v2_impl(dst, src, mask); |
| 1953 | } | 1953 | } |
| 1954 | 1954 | ||
| 1955 | [[deprecated("NOTICE: asc_squeeze_v2 is deprecated. " | 1955 | [[deprecated("NOTICE: asc_squeeze_v2 is deprecated. " |
| 1956 | "Please use asc_squeeze_with_status instead.")]] | 1956 | "Please use asc_squeeze_with_status instead.")]] |
| 1957 | __simd_callee__ inline void asc_squeeze_v2(vector_fp8_e5m2_t& dst, vector_fp8_e5m2_t src, vector_bool mask) | 1957 | __simd_callee__ inline void asc_squeeze_v2(vector_fp8_e5m2_t& dst, vector_fp8_e5m2_t src, vector_bool mask) |
| 1958 | { | 1958 | { |
| 1959 | - asc_squeeze_v2_impl(dst, src, mask); | 1959 | + asc_squeeze_v2_impl(dst, src, mask); |
| 1960 | } | 1960 | } |
| 1961 | 1961 | ||
| 1962 | [[deprecated("NOTICE: asc_squeeze_v2 is deprecated. " | 1962 | [[deprecated("NOTICE: asc_squeeze_v2 is deprecated. " |
| 1963 | "Please use asc_squeeze_with_status instead.")]] | 1963 | "Please use asc_squeeze_with_status instead.")]] |
| 1964 | __simd_callee__ inline void asc_squeeze_v2(vector_fp8_e8m0_t& dst, vector_fp8_e8m0_t src, vector_bool mask) | 1964 | __simd_callee__ inline void asc_squeeze_v2(vector_fp8_e8m0_t& dst, vector_fp8_e8m0_t src, vector_bool mask) |
| 1965 | { | 1965 | { |
| 1966 | - asc_squeeze_v2_impl(dst, src, mask); | 1966 | + asc_squeeze_v2_impl(dst, src, mask); |
| 1967 | } | 1967 | } |
| 1968 | 1968 | ||
| 1969 | // ==========asc_squeeze_with_status(uint8_t/int8_t/uint16_t/int16_t/uint32_t/int32_t/half/float/bfloat16_t/hifloat8_t/fp8_e4m3fn_t/fp8_e5m2_t/fp8_e8m0_t)========== | 1969 | // ==========asc_squeeze_with_status(uint8_t/int8_t/uint16_t/int16_t/uint32_t/int32_t/half/float/bfloat16_t/hifloat8_t/fp8_e4m3fn_t/fp8_e5m2_t/fp8_e8m0_t)========== |
| @@ -5405,9 +5405,9 @@ __simd_callee__ inline void asc_copy(vector_bool& dst, vector_bool src, vector_b | |||
| 5405 | asc_copy_impl(dst, src, mask); | 5405 | asc_copy_impl(dst, src, mask); |
| 5406 | } | 5406 | } |
| 5407 | 5407 | ||
| 5408 | -__simd_callee__ inline void asc_copy(vector_bool& dst, vector_bool src) | 5408 | +__simd_callee__ inline void asc_copy(vector_bool& dst, vector_bool src) |
| 5409 | -{ | 5409 | +{ |
| 5410 | - asc_copy_impl(dst, src); | 5410 | + asc_copy_impl(dst, src); |
| 5411 | } | 5411 | } |
| 5412 | 5412 | ||
| 5413 | __simd_callee__ inline void asc_copy(vector_bool& dst, vector_uint16_t src, int16_t part) | 5413 | __simd_callee__ inline void asc_copy(vector_bool& dst, vector_uint16_t src, int16_t part) |
| @@ -65,4 +65,4 @@ __simd_callee__ inline void asc_abs_impl(vector_float& dst, vector_float src, ve | |||
| 65 | 65 | ||
| 66 | 66 | ||
| 67 | 67 | ||
| 68 | -#endif | 68 | +#endif |
| @@ -32,4 +32,4 @@ __simd_callee__ inline void asc_abs_sub_impl(vector_float& dst, vector_float src | |||
| 32 | } | 32 | } |
| 33 | } | 33 | } |
| 34 | 34 | ||
| 35 | -#endif | 35 | +#endif |
| @@ -90,4 +90,4 @@ __simd_callee__ inline void asc_add_impl(vector_bool& dst0, vector_uint32_t& dst | |||
| 90 | } | 90 | } |
| 91 | } | 91 | } |
| 92 | 92 | ||
| 93 | -#endif | 93 | +#endif |
| @@ -93,4 +93,4 @@ __simd_callee__ inline void asc_add_scalar_impl(vector_float& dst, vector_float | |||
| 93 | 93 | ||
| 94 | 94 | ||
| 95 | 95 | ||
| 96 | -#endif | 96 | +#endif |
| @@ -29,4 +29,4 @@ __simd_callee__ inline void asc_addc_impl(vector_bool& dst0, vector_int32_t& dst | |||
| 29 | } | 29 | } |
| 30 | } | 30 | } |
| 31 | 31 | ||
| 32 | -#endif | 32 | +#endif |
| @@ -101,4 +101,4 @@ __simd_callee__ inline void asc_and_impl(vector_float& dst, vector_float src0, v | |||
| 101 | vand(dst, src0, src1, mask, MODE_ZEROING); | 101 | vand(dst, src0, src1, mask, MODE_ZEROING); |
| 102 | } | 102 | } |
| 103 | } | 103 | } |
| 104 | -#endif | 104 | +#endif |
| @@ -100,4 +100,4 @@ __simd_callee__ inline void asc_arange_descend_impl(vector_float& dst, float val | |||
| 100 | 100 | ||
| 101 | 101 | ||
| 102 | 102 | ||
| 103 | -#endif | 103 | +#endif |
| @@ -25,4 +25,4 @@ __simd_callee__ inline void asc_clear_ar_spr_impl() | |||
| 25 | } | 25 | } |
| 26 | } | 26 | } |
| 27 | 27 | ||
| 28 | -#endif | 28 | +#endif |
| @@ -120,4 +120,4 @@ __simd_callee__ inline void asc_copy_impl(vector_bool& dst, vector_uint32_t src, | |||
| 120 | 120 | ||
| 121 | 121 | ||
| 122 | 122 | ||
| 123 | -#endif | 123 | +#endif |
| @@ -44,4 +44,4 @@ __simd_callee__ inline void asc_cumulative_histogram_bin1_impl(vector_uint16_t& | |||
| 44 | 44 | ||
| 45 | 45 | ||
| 46 | 46 | ||
| 47 | -#endif | 47 | +#endif |
| @@ -29,49 +29,49 @@ __simd_callee__ inline void asc_deintlv_impl(vector_int32_t& dst0, vector_int32_ | |||
| 29 | { | 29 | { |
| 30 | if ASC_IS_AIV { | 30 | if ASC_IS_AIV { |
| 31 | vdintlv(dst0, dst1, src0, src1); | 31 | vdintlv(dst0, dst1, src0, src1); |
| 32 | - } | 32 | + } |
| 33 | } | 33 | } |
| 34 | 34 | ||
| 35 | __simd_callee__ inline void asc_deintlv_impl(vector_uint32_t& dst0, vector_uint32_t& dst1, vector_uint32_t src0, vector_uint32_t src1) | 35 | __simd_callee__ inline void asc_deintlv_impl(vector_uint32_t& dst0, vector_uint32_t& dst1, vector_uint32_t src0, vector_uint32_t src1) |
| 36 | { | 36 | { |
| 37 | if ASC_IS_AIV { | 37 | if ASC_IS_AIV { |
| 38 | vdintlv(dst0, dst1, src0, src1); | 38 | vdintlv(dst0, dst1, src0, src1); |
| 39 | - } | 39 | + } |
| 40 | } | 40 | } |
| 41 | 41 | ||
| 42 | __simd_callee__ inline void asc_deintlv_impl(vector_int16_t& dst0, vector_int16_t& dst1, vector_int16_t src0, vector_int16_t src1) | 42 | __simd_callee__ inline void asc_deintlv_impl(vector_int16_t& dst0, vector_int16_t& dst1, vector_int16_t src0, vector_int16_t src1) |
| 43 | { | 43 | { |
| 44 | if ASC_IS_AIV { | 44 | if ASC_IS_AIV { |
| 45 | vdintlv(dst0, dst1, src0, src1); | 45 | vdintlv(dst0, dst1, src0, src1); |
| 46 | - } | 46 | + } |
| 47 | } | 47 | } |
| 48 | 48 | ||
| 49 | __simd_callee__ inline void asc_deintlv_impl(vector_uint16_t& dst0, vector_uint16_t& dst1, vector_uint16_t src0, vector_uint16_t src1) | 49 | __simd_callee__ inline void asc_deintlv_impl(vector_uint16_t& dst0, vector_uint16_t& dst1, vector_uint16_t src0, vector_uint16_t src1) |
| 50 | { | 50 | { |
| 51 | if ASC_IS_AIV { | 51 | if ASC_IS_AIV { |
| 52 | vdintlv(dst0, dst1, src0, src1); | 52 | vdintlv(dst0, dst1, src0, src1); |
| 53 | - } | 53 | + } |
| 54 | } | 54 | } |
| 55 | 55 | ||
| 56 | __simd_callee__ inline void asc_deintlv_impl(vector_int8_t& dst0, vector_int8_t& dst1, vector_int8_t src0, vector_int8_t src1) | 56 | __simd_callee__ inline void asc_deintlv_impl(vector_int8_t& dst0, vector_int8_t& dst1, vector_int8_t src0, vector_int8_t src1) |
| 57 | { | 57 | { |
| 58 | if ASC_IS_AIV { | 58 | if ASC_IS_AIV { |
| 59 | vdintlv(dst0, dst1, src0, src1); | 59 | vdintlv(dst0, dst1, src0, src1); |
| 60 | - } | 60 | + } |
| 61 | } | 61 | } |
| 62 | 62 | ||
| 63 | __simd_callee__ inline void asc_deintlv_impl(vector_uint8_t& dst0, vector_uint8_t& dst1, vector_uint8_t src0, vector_uint8_t src1) | 63 | __simd_callee__ inline void asc_deintlv_impl(vector_uint8_t& dst0, vector_uint8_t& dst1, vector_uint8_t src0, vector_uint8_t src1) |
| 64 | { | 64 | { |
| 65 | if ASC_IS_AIV { | 65 | if ASC_IS_AIV { |
| 66 | vdintlv(dst0, dst1, src0, src1); | 66 | vdintlv(dst0, dst1, src0, src1); |
| 67 | - } | 67 | + } |
| 68 | } | 68 | } |
| 69 | 69 | ||
| 70 | __simd_callee__ inline void asc_deintlv_impl(vector_fp8_e4m3fn_t& dst0, vector_fp8_e4m3fn_t& dst1, vector_fp8_e4m3fn_t src0, vector_fp8_e4m3fn_t src1) | 70 | __simd_callee__ inline void asc_deintlv_impl(vector_fp8_e4m3fn_t& dst0, vector_fp8_e4m3fn_t& dst1, vector_fp8_e4m3fn_t src0, vector_fp8_e4m3fn_t src1) |
| 71 | { | 71 | { |
| 72 | if ASC_IS_AIV { | 72 | if ASC_IS_AIV { |
| 73 | vdintlv(dst0, dst1, src0, src1); | 73 | vdintlv(dst0, dst1, src0, src1); |
| 74 | - } | 74 | + } |
| 75 | } | 75 | } |
| 76 | 76 | ||
| 77 | __simd_callee__ inline void asc_deintlv_impl(vector_hifloat8_t& dst0, vector_hifloat8_t& dst1, vector_hifloat8_t src0, vector_hifloat8_t src1) | 77 | __simd_callee__ inline void asc_deintlv_impl(vector_hifloat8_t& dst0, vector_hifloat8_t& dst1, vector_hifloat8_t src0, vector_hifloat8_t src1) |
| @@ -79,63 +79,63 @@ __simd_callee__ inline void asc_deintlv_impl(vector_hifloat8_t& dst0, vector_hif | |||
| 79 | if ASC_IS_AIV { | 79 | if ASC_IS_AIV { |
| 80 | vdintlv(reinterpret_cast<vector_uint8_t&>(dst0), reinterpret_cast<vector_uint8_t&>(dst1), | 80 | vdintlv(reinterpret_cast<vector_uint8_t&>(dst0), reinterpret_cast<vector_uint8_t&>(dst1), |
| 81 | *reinterpret_cast<vector_uint8_t*>(&src0), *reinterpret_cast<vector_uint8_t*>(&src1)); | 81 | *reinterpret_cast<vector_uint8_t*>(&src0), *reinterpret_cast<vector_uint8_t*>(&src1)); |
| 82 | - } | 82 | + } |
| 83 | } | 83 | } |
| 84 | 84 | ||
| 85 | __simd_callee__ inline void asc_deintlv_impl(vector_fp8_e5m2_t& dst0, vector_fp8_e5m2_t& dst1, vector_fp8_e5m2_t src0, vector_fp8_e5m2_t src1) | 85 | __simd_callee__ inline void asc_deintlv_impl(vector_fp8_e5m2_t& dst0, vector_fp8_e5m2_t& dst1, vector_fp8_e5m2_t src0, vector_fp8_e5m2_t src1) |
| 86 | { | 86 | { |
| 87 | if ASC_IS_AIV { | 87 | if ASC_IS_AIV { |
| 88 | vdintlv(dst0, dst1, src0, src1); | 88 | vdintlv(dst0, dst1, src0, src1); |
| 89 | - } | 89 | + } |
| 90 | } | 90 | } |
| 91 | 91 | ||
| 92 | __simd_callee__ inline void asc_deintlv_impl(vector_fp8_e8m0_t& dst0, vector_fp8_e8m0_t& dst1, vector_fp8_e8m0_t src0, vector_fp8_e8m0_t src1) | 92 | __simd_callee__ inline void asc_deintlv_impl(vector_fp8_e8m0_t& dst0, vector_fp8_e8m0_t& dst1, vector_fp8_e8m0_t src0, vector_fp8_e8m0_t src1) |
| 93 | { | 93 | { |
| 94 | if ASC_IS_AIV { | 94 | if ASC_IS_AIV { |
| 95 | vdintlv(dst0, dst1, src0, src1); | 95 | vdintlv(dst0, dst1, src0, src1); |
| 96 | - } | 96 | + } |
| 97 | } | 97 | } |
| 98 | 98 | ||
| 99 | __simd_callee__ inline void asc_deintlv_impl(vector_bfloat16_t& dst0, vector_bfloat16_t& dst1, vector_bfloat16_t src0, vector_bfloat16_t src1) | 99 | __simd_callee__ inline void asc_deintlv_impl(vector_bfloat16_t& dst0, vector_bfloat16_t& dst1, vector_bfloat16_t src0, vector_bfloat16_t src1) |
| 100 | { | 100 | { |
| 101 | if ASC_IS_AIV { | 101 | if ASC_IS_AIV { |
| 102 | vdintlv(dst0, dst1, src0, src1); | 102 | vdintlv(dst0, dst1, src0, src1); |
| 103 | - } | 103 | + } |
| 104 | } | 104 | } |
| 105 | 105 | ||
| 106 | __simd_callee__ inline void asc_deintlv_impl(vector_float& dst0, vector_float& dst1, vector_float src0, vector_float src1) | 106 | __simd_callee__ inline void asc_deintlv_impl(vector_float& dst0, vector_float& dst1, vector_float src0, vector_float src1) |
| 107 | { | 107 | { |
| 108 | if ASC_IS_AIV { | 108 | if ASC_IS_AIV { |
| 109 | vdintlv(dst0, dst1, src0, src1); | 109 | vdintlv(dst0, dst1, src0, src1); |
| 110 | - } | 110 | + } |
| 111 | } | 111 | } |
| 112 | 112 | ||
| 113 | __simd_callee__ inline void asc_deintlv_impl(vector_half& dst0, vector_half& dst1, vector_half src0, vector_half src1) | 113 | __simd_callee__ inline void asc_deintlv_impl(vector_half& dst0, vector_half& dst1, vector_half src0, vector_half src1) |
| 114 | { | 114 | { |
| 115 | if ASC_IS_AIV { | 115 | if ASC_IS_AIV { |
| 116 | vdintlv(dst0, dst1, src0, src1); | 116 | vdintlv(dst0, dst1, src0, src1); |
| 117 | - } | 117 | + } |
| 118 | } | 118 | } |
| 119 | 119 | ||
| 120 | __simd_callee__ inline void asc_deintlv_b8_impl(vector_bool& dst0, vector_bool& dst1, vector_bool src0, vector_bool src1) | 120 | __simd_callee__ inline void asc_deintlv_b8_impl(vector_bool& dst0, vector_bool& dst1, vector_bool src0, vector_bool src1) |
| 121 | { | 121 | { |
| 122 | if ASC_IS_AIV { | 122 | if ASC_IS_AIV { |
| 123 | pdintlv_b8(dst0, dst1, src0, src1); | 123 | pdintlv_b8(dst0, dst1, src0, src1); |
| 124 | - } | 124 | + } |
| 125 | } | 125 | } |
| 126 | 126 | ||
| 127 | __simd_callee__ inline void asc_deintlv_b16_impl(vector_bool& dst0, vector_bool& dst1, vector_bool src0, vector_bool src1) | 127 | __simd_callee__ inline void asc_deintlv_b16_impl(vector_bool& dst0, vector_bool& dst1, vector_bool src0, vector_bool src1) |
| 128 | { | 128 | { |
| 129 | if ASC_IS_AIV { | 129 | if ASC_IS_AIV { |
| 130 | pdintlv_b16(dst0, dst1, src0, src1); | 130 | pdintlv_b16(dst0, dst1, src0, src1); |
| 131 | - } | 131 | + } |
| 132 | } | 132 | } |
| 133 | 133 | ||
| 134 | __simd_callee__ inline void asc_deintlv_b32_impl(vector_bool& dst0, vector_bool& dst1, vector_bool src0, vector_bool src1) | 134 | __simd_callee__ inline void asc_deintlv_b32_impl(vector_bool& dst0, vector_bool& dst1, vector_bool src0, vector_bool src1) |
| 135 | { | 135 | { |
| 136 | if ASC_IS_AIV { | 136 | if ASC_IS_AIV { |
| 137 | pdintlv_b32(dst0, dst1, src0, src1); | 137 | pdintlv_b32(dst0, dst1, src0, src1); |
| 138 | - } | 138 | + } |
| 139 | } | 139 | } |
| 140 | 140 | ||
| 141 | -#endif | 141 | +#endif |
| @@ -29,7 +29,7 @@ __simd_callee__ inline void asc_div_impl(vector_half& dst, vector_half src0, vec | |||
| 29 | { | 29 | { |
| 30 | if ASC_IS_AIV{ | 30 | if ASC_IS_AIV{ |
| 31 | vdiv(dst, src0, src1, mask, MODE_ZEROING); | 31 | vdiv(dst, src0, src1, mask, MODE_ZEROING); |
| 32 | - } | 32 | + } |
| 33 | } | 33 | } |
| 34 | 34 | ||
| 35 | __simd_callee__ inline void asc_div_impl(vector_float& dst, vector_float src0, vector_float src1, vector_bool mask) | 35 | __simd_callee__ inline void asc_div_impl(vector_float& dst, vector_float src0, vector_float src1, vector_bool mask) |
| @@ -39,4 +39,4 @@ __simd_callee__ inline void asc_div_impl(vector_float& dst, vector_float src0, v | |||
| 39 | } | 39 | } |
| 40 | } | 40 | } |
| 41 | 41 | ||
| 42 | -#endif | 42 | +#endif |
| @@ -94,4 +94,4 @@ __simd_callee__ inline void asc_duplicate_impl(vector_float& dst, vector_float s | |||
| 94 | vdup(dst, src, mask, POS_LOWEST, MODE_ZEROING); | 94 | vdup(dst, src, mask, POS_LOWEST, MODE_ZEROING); |
| 95 | } | 95 | } |
| 96 | } | 96 | } |
| 97 | -#endif | 97 | +#endif |
| @@ -187,4 +187,4 @@ __simd_callee__ inline void asc_duplicate_scalar_impl(vector_fp8_e8m0_t& dst, fp | |||
| 187 | } | 187 | } |
| 188 | } | 188 | } |
| 189 | 189 | ||
| 190 | -#endif | 190 | +#endif |
| @@ -88,4 +88,4 @@ __simd_callee__ inline void asc_eq_impl(vector_bool& dst, vector_bfloat16_t src0 | |||
| 88 | 88 | ||
| 89 | 89 | ||
| 90 | 90 | ||
| 91 | -#endif | 91 | +#endif |
| @@ -88,4 +88,4 @@ __simd_callee__ inline void asc_eq_scalar_impl(vector_bool& dst, vector_float sr | |||
| 88 | 88 | ||
| 89 | 89 | ||
| 90 | 90 | ||
| 91 | -#endif | 91 | +#endif |
| @@ -44,4 +44,4 @@ __simd_callee__ inline void asc_exp_impl(vector_float& dst, vector_float src, ve | |||
| 44 | 44 | ||
| 45 | 45 | ||
| 46 | 46 | ||
| 47 | -#endif | 47 | +#endif |
| @@ -58,4 +58,4 @@ __simd_callee__ inline void asc_exp_sub_v2_impl(vector_float& dst, vector_float | |||
| 58 | 58 | ||
| 59 | 59 | ||
| 60 | 60 | ||
| 61 | -#endif | 61 | +#endif |
| @@ -44,4 +44,4 @@ __simd_callee__ inline void asc_frequency_histogram_bin1_impl(vector_uint16_t& d | |||
| 44 | 44 | ||
| 45 | 45 | ||
| 46 | 46 | ||
| 47 | -#endif | 47 | +#endif |
| @@ -102,4 +102,4 @@ __simd_callee__ inline void asc_gt_impl(vector_bool& dst, vector_bfloat16_t src0 | |||
| 102 | 102 | ||
| 103 | 103 | ||
| 104 | 104 | ||
| 105 | -#endif | 105 | +#endif |
| @@ -102,4 +102,4 @@ __simd_callee__ inline void asc_gt_scalar_impl(vector_bool& dst, vector_float sr | |||
| 102 | 102 | ||
| 103 | 103 | ||
| 104 | 104 | ||
| 105 | -#endif | 105 | +#endif |
| @@ -143,4 +143,4 @@ __simd_callee__ inline void asc_intlv_impl(vector_bfloat16_t& dst0, vector_bfloa | |||
| 143 | 143 | ||
| 144 | 144 | ||
| 145 | 145 | ||
| 146 | -#endif | 146 | +#endif |
| @@ -92,4 +92,4 @@ __simd_callee__ inline void asc_le_impl(vector_bool& dst, vector_bfloat16_t src0 | |||
| 92 | 92 | ||
| 93 | 93 | ||
| 94 | 94 | ||
| 95 | -#endif | 95 | +#endif |
| @@ -92,4 +92,4 @@ __simd_callee__ inline void asc_le_scalar_impl(vector_bool& dst, vector_bfloat16 | |||
| 92 | 92 | ||
| 93 | 93 | ||
| 94 | 94 | ||
| 95 | -#endif | 95 | +#endif |
| @@ -46,4 +46,4 @@ __simd_callee__ inline void asc_leakyrelu_impl(vector_half& dst, vector_half src | |||
| 46 | 46 | ||
| 47 | 47 | ||
| 48 | 48 | ||
| 49 | -#endif | 49 | +#endif |
| @@ -39,4 +39,4 @@ __simd_callee__ inline void asc_ln_impl(vector_float& dst, vector_float src, vec | |||
| 39 | } | 39 | } |
| 40 | } | 40 | } |
| 41 | 41 | ||
| 42 | -#endif | 42 | +#endif |
| @@ -76,4 +76,4 @@ __simd_callee__ inline void asc_lt_impl(vector_bool& dst, vector_bfloat16_t src0 | |||
| 76 | } | 76 | } |
| 77 | } | 77 | } |
| 78 | 78 | ||
| 79 | -#endif | 79 | +#endif |
| @@ -76,4 +76,4 @@ __simd_callee__ inline void asc_lt_scalar_impl(vector_bool& dst, vector_float sr | |||
| 76 | } | 76 | } |
| 77 | } | 77 | } |
| 78 | 78 | ||
| 79 | -#endif | 79 | +#endif |
| @@ -27,4 +27,4 @@ __simd_callee__ inline void asc_madd_impl(vector_float& dst, vector_float src0, | |||
| 27 | } | 27 | } |
| 28 | } | 28 | } |
| 29 | 29 | ||
| 30 | -#endif | 30 | +#endif |
| @@ -102,4 +102,4 @@ __simd_callee__ inline void asc_max_impl(vector_bfloat16_t& dst, vector_bfloat16 | |||
| 102 | 102 | ||
| 103 | 103 | ||
| 104 | 104 | ||
| 105 | -#endif | 105 | +#endif |
| @@ -88,4 +88,4 @@ __simd_callee__ inline void asc_max_scalar_impl(vector_bfloat16_t& dst, vector_b | |||
| 88 | } | 88 | } |
| 89 | } | 89 | } |
| 90 | 90 | ||
| 91 | -#endif | 91 | +#endif |
| @@ -94,4 +94,4 @@ __simd_callee__ inline void asc_min_scalar_impl(vector_half& dst, vector_half sr | |||
| 94 | 94 | ||
| 95 | 95 | ||
| 96 | 96 | ||
| 97 | -#endif | 97 | +#endif |
| @@ -74,4 +74,4 @@ __simd_callee__ inline void asc_mul_impl(vector_bfloat16_t& dst, vector_bfloat16 | |||
| 74 | 74 | ||
| 75 | 75 | ||
| 76 | 76 | ||
| 77 | -#endif | 77 | +#endif |
| @@ -66,4 +66,4 @@ __simd_callee__ inline void asc_mul_scalar_impl(vector_half& dst, vector_half sr | |||
| 66 | 66 | ||
| 67 | 67 | ||
| 68 | 68 | ||
| 69 | -#endif | 69 | +#endif |
| @@ -45,4 +45,4 @@ __simd_callee__ inline void asc_mull_impl(vector_int32_t& dst0, vector_int32_t& | |||
| 45 | 45 | ||
| 46 | 46 | ||
| 47 | 47 | ||
| 48 | -#endif | 48 | +#endif |
| @@ -44,4 +44,4 @@ __simd_callee__ inline void asc_muls_v2_impl(vector_half& dst, vector_float src, | |||
| 44 | 44 | ||
| 45 | 45 | ||
| 46 | 46 | ||
| 47 | -#endif | 47 | +#endif |
| @@ -29,56 +29,56 @@ __simd_callee__ inline void asc_ne_impl(vector_bool& dst, vector_uint8_t src0, v | |||
| 29 | { | 29 | { |
| 30 | if ASC_IS_AIV { | 30 | if ASC_IS_AIV { |
| 31 | vcmp_ne(dst, src0, src1, mask); | 31 | vcmp_ne(dst, src0, src1, mask); |
| 32 | - } | 32 | + } |
| 33 | } | 33 | } |
| 34 | 34 | ||
| 35 | __simd_callee__ inline void asc_ne_impl(vector_bool& dst, vector_int8_t src0, vector_int8_t src1, vector_bool mask) | 35 | __simd_callee__ inline void asc_ne_impl(vector_bool& dst, vector_int8_t src0, vector_int8_t src1, vector_bool mask) |
| 36 | { | 36 | { |
| 37 | if ASC_IS_AIV { | 37 | if ASC_IS_AIV { |
| 38 | vcmp_ne(dst, src0, src1, mask); | 38 | vcmp_ne(dst, src0, src1, mask); |
| 39 | - } | 39 | + } |
| 40 | } | 40 | } |
| 41 | 41 | ||
| 42 | __simd_callee__ inline void asc_ne_impl(vector_bool& dst, vector_uint16_t src0, vector_uint16_t src1, vector_bool mask) | 42 | __simd_callee__ inline void asc_ne_impl(vector_bool& dst, vector_uint16_t src0, vector_uint16_t src1, vector_bool mask) |
| 43 | { | 43 | { |
| 44 | if ASC_IS_AIV { | 44 | if ASC_IS_AIV { |
| 45 | vcmp_ne(dst, src0, src1, mask); | 45 | vcmp_ne(dst, src0, src1, mask); |
| 46 | - } | 46 | + } |
| 47 | } | 47 | } |
| 48 | 48 | ||
| 49 | __simd_callee__ inline void asc_ne_impl(vector_bool& dst, vector_int16_t src0, vector_int16_t src1, vector_bool mask) | 49 | __simd_callee__ inline void asc_ne_impl(vector_bool& dst, vector_int16_t src0, vector_int16_t src1, vector_bool mask) |
| 50 | { | 50 | { |
| 51 | if ASC_IS_AIV { | 51 | if ASC_IS_AIV { |
| 52 | vcmp_ne(dst, src0, src1, mask); | 52 | vcmp_ne(dst, src0, src1, mask); |
| 53 | - } | 53 | + } |
| 54 | } | 54 | } |
| 55 | 55 | ||
| 56 | __simd_callee__ inline void asc_ne_impl(vector_bool& dst, vector_uint32_t src0, vector_uint32_t src1, vector_bool mask) | 56 | __simd_callee__ inline void asc_ne_impl(vector_bool& dst, vector_uint32_t src0, vector_uint32_t src1, vector_bool mask) |
| 57 | { | 57 | { |
| 58 | if ASC_IS_AIV { | 58 | if ASC_IS_AIV { |
| 59 | vcmp_ne(dst, src0, src1, mask); | 59 | vcmp_ne(dst, src0, src1, mask); |
| 60 | - } | 60 | + } |
| 61 | } | 61 | } |
| 62 | 62 | ||
| 63 | __simd_callee__ inline void asc_ne_impl(vector_bool& dst, vector_int32_t src0, vector_int32_t src1, vector_bool mask) | 63 | __simd_callee__ inline void asc_ne_impl(vector_bool& dst, vector_int32_t src0, vector_int32_t src1, vector_bool mask) |
| 64 | { | 64 | { |
| 65 | if ASC_IS_AIV { | 65 | if ASC_IS_AIV { |
| 66 | vcmp_ne(dst, src0, src1, mask); | 66 | vcmp_ne(dst, src0, src1, mask); |
| 67 | - } | 67 | + } |
| 68 | } | 68 | } |
| 69 | 69 | ||
| 70 | __simd_callee__ inline void asc_ne_impl(vector_bool& dst, vector_half src0, vector_half src1, vector_bool mask) | 70 | __simd_callee__ inline void asc_ne_impl(vector_bool& dst, vector_half src0, vector_half src1, vector_bool mask) |
| 71 | { | 71 | { |
| 72 | if ASC_IS_AIV { | 72 | if ASC_IS_AIV { |
| 73 | vcmp_ne(dst, src0, src1, mask); | 73 | vcmp_ne(dst, src0, src1, mask); |
| 74 | - } | 74 | + } |
| 75 | } | 75 | } |
| 76 | 76 | ||
| 77 | __simd_callee__ inline void asc_ne_impl(vector_bool& dst, vector_float src0, vector_float src1, vector_bool mask) | 77 | __simd_callee__ inline void asc_ne_impl(vector_bool& dst, vector_float src0, vector_float src1, vector_bool mask) |
| 78 | { | 78 | { |
| 79 | if ASC_IS_AIV { | 79 | if ASC_IS_AIV { |
| 80 | vcmp_ne(dst, src0, src1, mask); | 80 | vcmp_ne(dst, src0, src1, mask); |
| 81 | - } | 81 | + } |
| 82 | } | 82 | } |
| 83 | 83 | ||
| 84 | -#endif | 84 | +#endif |
| @@ -29,63 +29,63 @@ __simd_callee__ inline void asc_ne_scalar_impl(vector_bool& dst, vector_uint8_t | |||
| 29 | { | 29 | { |
| 30 | if ASC_IS_AIV { | 30 | if ASC_IS_AIV { |
| 31 | vcmps_ne(dst, src, value, mask); | 31 | vcmps_ne(dst, src, value, mask); |
| 32 | - } | 32 | + } |
| 33 | } | 33 | } |
| 34 | 34 | ||
| 35 | __simd_callee__ inline void asc_ne_scalar_impl(vector_bool& dst, vector_int8_t src, int8_t value, vector_bool mask) | 35 | __simd_callee__ inline void asc_ne_scalar_impl(vector_bool& dst, vector_int8_t src, int8_t value, vector_bool mask) |
| 36 | { | 36 | { |
| 37 | if ASC_IS_AIV { | 37 | if ASC_IS_AIV { |
| 38 | vcmps_ne(dst, src, value, mask); | 38 | vcmps_ne(dst, src, value, mask); |
| 39 | - } | 39 | + } |
| 40 | } | 40 | } |
| 41 | 41 | ||
| 42 | __simd_callee__ inline void asc_ne_scalar_impl(vector_bool& dst, vector_uint16_t src, uint16_t value, vector_bool mask) | 42 | __simd_callee__ inline void asc_ne_scalar_impl(vector_bool& dst, vector_uint16_t src, uint16_t value, vector_bool mask) |
| 43 | { | 43 | { |
| 44 | if ASC_IS_AIV { | 44 | if ASC_IS_AIV { |
| 45 | vcmps_ne(dst, src, value, mask); | 45 | vcmps_ne(dst, src, value, mask); |
| 46 | - } | 46 | + } |
| 47 | } | 47 | } |
| 48 | 48 | ||
| 49 | __simd_callee__ inline void asc_ne_scalar_impl(vector_bool& dst, vector_int16_t src, int16_t value, vector_bool mask) | 49 | __simd_callee__ inline void asc_ne_scalar_impl(vector_bool& dst, vector_int16_t src, int16_t value, vector_bool mask) |
| 50 | { | 50 | { |
| 51 | if ASC_IS_AIV { | 51 | if ASC_IS_AIV { |
| 52 | vcmps_ne(dst, src, value, mask); | 52 | vcmps_ne(dst, src, value, mask); |
| 53 | - } | 53 | + } |
| 54 | } | 54 | } |
| 55 | 55 | ||
| 56 | __simd_callee__ inline void asc_ne_scalar_impl(vector_bool& dst, vector_uint32_t src, uint32_t value, vector_bool mask) | 56 | __simd_callee__ inline void asc_ne_scalar_impl(vector_bool& dst, vector_uint32_t src, uint32_t value, vector_bool mask) |
| 57 | { | 57 | { |
| 58 | if ASC_IS_AIV { | 58 | if ASC_IS_AIV { |
| 59 | vcmps_ne(dst, src, value, mask); | 59 | vcmps_ne(dst, src, value, mask); |
| 60 | - } | 60 | + } |
| 61 | } | 61 | } |
| 62 | 62 | ||
| 63 | __simd_callee__ inline void asc_ne_scalar_impl(vector_bool& dst, vector_int32_t src, int32_t value, vector_bool mask) | 63 | __simd_callee__ inline void asc_ne_scalar_impl(vector_bool& dst, vector_int32_t src, int32_t value, vector_bool mask) |
| 64 | { | 64 | { |
| 65 | if ASC_IS_AIV { | 65 | if ASC_IS_AIV { |
| 66 | vcmps_ne(dst, src, value, mask); | 66 | vcmps_ne(dst, src, value, mask); |
| 67 | - } | 67 | + } |
| 68 | } | 68 | } |
| 69 | 69 | ||
| 70 | __simd_callee__ inline void asc_ne_scalar_impl(vector_bool& dst, vector_half src, half value, vector_bool mask) | 70 | __simd_callee__ inline void asc_ne_scalar_impl(vector_bool& dst, vector_half src, half value, vector_bool mask) |
| 71 | { | 71 | { |
| 72 | if ASC_IS_AIV { | 72 | if ASC_IS_AIV { |
| 73 | vcmps_ne(dst, src, value, mask); | 73 | vcmps_ne(dst, src, value, mask); |
| 74 | - } | 74 | + } |
| 75 | } | 75 | } |
| 76 | 76 | ||
| 77 | __simd_callee__ inline void asc_ne_scalar_impl(vector_bool& dst, vector_float src, float value, vector_bool mask) | 77 | __simd_callee__ inline void asc_ne_scalar_impl(vector_bool& dst, vector_float src, float value, vector_bool mask) |
| 78 | { | 78 | { |
| 79 | if ASC_IS_AIV { | 79 | if ASC_IS_AIV { |
| 80 | vcmps_ne(dst, src, value, mask); | 80 | vcmps_ne(dst, src, value, mask); |
| 81 | - } | 81 | + } |
| 82 | } | 82 | } |
| 83 | 83 | ||
| 84 | __simd_callee__ inline void asc_ne_scalar_impl(vector_bool& dst, vector_bfloat16_t src, bfloat16_t value, vector_bool mask) | 84 | __simd_callee__ inline void asc_ne_scalar_impl(vector_bool& dst, vector_bfloat16_t src, bfloat16_t value, vector_bool mask) |
| 85 | { | 85 | { |
| 86 | if ASC_IS_AIV { | 86 | if ASC_IS_AIV { |
| 87 | vcmps_ne(dst, src, value, mask); | 87 | vcmps_ne(dst, src, value, mask); |
| 88 | - } | 88 | + } |
| 89 | } | 89 | } |
| 90 | 90 | ||
| 91 | -#endif | 91 | +#endif |
| @@ -76,4 +76,4 @@ __simd_callee__ inline void asc_not_impl(vector_bool& dst, vector_bool src, vect | |||
| 76 | } | 76 | } |
| 77 | } | 77 | } |
| 78 | 78 | ||
| 79 | -#endif | 79 | +#endif |
| @@ -88,4 +88,4 @@ __simd_callee__ inline void asc_or_impl(vector_bool& dst, vector_bool src0, vect | |||
| 88 | 88 | ||
| 89 | 89 | ||
| 90 | 90 | ||
| 91 | -#endif | 91 | +#endif |
| @@ -100,4 +100,4 @@ __simd_callee__ inline void asc_pack_v2_impl(vector_bool& dst, vector_bool src) | |||
| 100 | 100 | ||
| 101 | 101 | ||
| 102 | 102 | ||
| 103 | -#endif | 103 | +#endif |
| @@ -27,4 +27,4 @@ __simd_callee__ inline void asc_pair_reduce_sum_impl(vector_float& dst, vector_f | |||
| 27 | } | 27 | } |
| 28 | } | 28 | } |
| 29 | 29 | ||
| 30 | -#endif | 30 | +#endif |
| @@ -44,4 +44,4 @@ __simd_callee__ inline void asc_prelu_impl(vector_half& dst, vector_half src0, v | |||
| 44 | 44 | ||
| 45 | 45 | ||
| 46 | 46 | ||
| 47 | -#endif | 47 | +#endif |
| @@ -66,4 +66,4 @@ __simd_callee__ inline void asc_reduce_max_datablock_impl(vector_int32_t& dst, v | |||
| 66 | } | 66 | } |
| 67 | } | 67 | } |
| 68 | 68 | ||
| 69 | -#endif | 69 | +#endif |
| @@ -29,42 +29,42 @@ __simd_callee__ inline void asc_reduce_sum_impl(vector_int32_t& dst, vector_int1 | |||
| 29 | { | 29 | { |
| 30 | if ASC_IS_AIV { | 30 | if ASC_IS_AIV { |
| 31 | vcadd(dst, src, mask, MODE_ZEROING); | 31 | vcadd(dst, src, mask, MODE_ZEROING); |
| 32 | - } | 32 | + } |
| 33 | } | 33 | } |
| 34 | 34 | ||
| 35 | __simd_callee__ inline void asc_reduce_sum_impl(vector_int32_t& dst, vector_int32_t src, vector_bool mask) | 35 | __simd_callee__ inline void asc_reduce_sum_impl(vector_int32_t& dst, vector_int32_t src, vector_bool mask) |
| 36 | { | 36 | { |
| 37 | if ASC_IS_AIV { | 37 | if ASC_IS_AIV { |
| 38 | vcadd(dst, src, mask, MODE_ZEROING); | 38 | vcadd(dst, src, mask, MODE_ZEROING); |
| 39 | - } | 39 | + } |
| 40 | } | 40 | } |
| 41 | 41 | ||
| 42 | __simd_callee__ inline void asc_reduce_sum_impl(vector_uint32_t& dst, vector_uint16_t src, vector_bool mask) | 42 | __simd_callee__ inline void asc_reduce_sum_impl(vector_uint32_t& dst, vector_uint16_t src, vector_bool mask) |
| 43 | { | 43 | { |
| 44 | if ASC_IS_AIV { | 44 | if ASC_IS_AIV { |
| 45 | vcadd(dst, src, mask, MODE_ZEROING); | 45 | vcadd(dst, src, mask, MODE_ZEROING); |
| 46 | - } | 46 | + } |
| 47 | } | 47 | } |
| 48 | 48 | ||
| 49 | __simd_callee__ inline void asc_reduce_sum_impl(vector_uint32_t& dst, vector_uint32_t src, vector_bool mask) | 49 | __simd_callee__ inline void asc_reduce_sum_impl(vector_uint32_t& dst, vector_uint32_t src, vector_bool mask) |
| 50 | { | 50 | { |
| 51 | if ASC_IS_AIV { | 51 | if ASC_IS_AIV { |
| 52 | vcadd(dst, src, mask, MODE_ZEROING); | 52 | vcadd(dst, src, mask, MODE_ZEROING); |
| 53 | - } | 53 | + } |
| 54 | } | 54 | } |
| 55 | 55 | ||
| 56 | __simd_callee__ inline void asc_reduce_sum_impl(vector_half& dst, vector_half src, vector_bool mask) | 56 | __simd_callee__ inline void asc_reduce_sum_impl(vector_half& dst, vector_half src, vector_bool mask) |
| 57 | { | 57 | { |
| 58 | if ASC_IS_AIV { | 58 | if ASC_IS_AIV { |
| 59 | vcadd(dst, src, mask, MODE_ZEROING); | 59 | vcadd(dst, src, mask, MODE_ZEROING); |
| 60 | - } | 60 | + } |
| 61 | } | 61 | } |
| 62 | 62 | ||
| 63 | __simd_callee__ inline void asc_reduce_sum_impl(vector_float& dst, vector_float src, vector_bool mask) | 63 | __simd_callee__ inline void asc_reduce_sum_impl(vector_float& dst, vector_float src, vector_bool mask) |
| 64 | { | 64 | { |
| 65 | if ASC_IS_AIV { | 65 | if ASC_IS_AIV { |
| 66 | vcadd(dst, src, mask, MODE_ZEROING); | 66 | vcadd(dst, src, mask, MODE_ZEROING); |
| 67 | - } | 67 | + } |
| 68 | } | 68 | } |
| 69 | 69 | ||
| 70 | -#endif | 70 | +#endif |
| @@ -29,42 +29,42 @@ __simd_callee__ inline void asc_reduce_sum_datablock_impl(vector_half& dst, vect | |||
| 29 | { | 29 | { |
| 30 | if ASC_IS_AIV{ | 30 | if ASC_IS_AIV{ |
| 31 | vcgadd(dst, src, mask, MODE_ZEROING); | 31 | vcgadd(dst, src, mask, MODE_ZEROING); |
| 32 | - } | 32 | + } |
| 33 | } | 33 | } |
| 34 | 34 | ||
| 35 | __simd_callee__ inline void asc_reduce_sum_datablock_impl(vector_float& dst, vector_float src, vector_bool mask) | 35 | __simd_callee__ inline void asc_reduce_sum_datablock_impl(vector_float& dst, vector_float src, vector_bool mask) |
| 36 | { | 36 | { |
| 37 | if ASC_IS_AIV{ | 37 | if ASC_IS_AIV{ |
| 38 | vcgadd(dst, src, mask, MODE_ZEROING); | 38 | vcgadd(dst, src, mask, MODE_ZEROING); |
| 39 | - } | 39 | + } |
| 40 | } | 40 | } |
| 41 | 41 | ||
| 42 | __simd_callee__ inline void asc_reduce_sum_datablock_impl(vector_uint32_t& dst, vector_uint16_t src, vector_bool mask) | 42 | __simd_callee__ inline void asc_reduce_sum_datablock_impl(vector_uint32_t& dst, vector_uint16_t src, vector_bool mask) |
| 43 | { | 43 | { |
| 44 | if ASC_IS_AIV{ | 44 | if ASC_IS_AIV{ |
| 45 | vcgadd(dst, src, mask, MODE_ZEROING); | 45 | vcgadd(dst, src, mask, MODE_ZEROING); |
| 46 | - } | 46 | + } |
| 47 | } | 47 | } |
| 48 | 48 | ||
| 49 | __simd_callee__ inline void asc_reduce_sum_datablock_impl(vector_int32_t& dst, vector_int16_t src, vector_bool mask) | 49 | __simd_callee__ inline void asc_reduce_sum_datablock_impl(vector_int32_t& dst, vector_int16_t src, vector_bool mask) |
| 50 | { | 50 | { |
| 51 | if ASC_IS_AIV{ | 51 | if ASC_IS_AIV{ |
| 52 | vcgadd(dst, src, mask, MODE_ZEROING); | 52 | vcgadd(dst, src, mask, MODE_ZEROING); |
| 53 | - } | 53 | + } |
| 54 | } | 54 | } |
| 55 | 55 | ||
| 56 | __simd_callee__ inline void asc_reduce_sum_datablock_impl(vector_uint32_t& dst, vector_uint32_t src, vector_bool mask) | 56 | __simd_callee__ inline void asc_reduce_sum_datablock_impl(vector_uint32_t& dst, vector_uint32_t src, vector_bool mask) |
| 57 | { | 57 | { |
| 58 | if ASC_IS_AIV{ | 58 | if ASC_IS_AIV{ |
| 59 | vcgadd(dst, src, mask, MODE_ZEROING); | 59 | vcgadd(dst, src, mask, MODE_ZEROING); |
| 60 | - } | 60 | + } |
| 61 | } | 61 | } |
| 62 | 62 | ||
| 63 | __simd_callee__ inline void asc_reduce_sum_datablock_impl(vector_int32_t& dst, vector_int32_t src, vector_bool mask) | 63 | __simd_callee__ inline void asc_reduce_sum_datablock_impl(vector_int32_t& dst, vector_int32_t src, vector_bool mask) |
| 64 | { | 64 | { |
| 65 | if ASC_IS_AIV{ | 65 | if ASC_IS_AIV{ |
| 66 | vcgadd(dst, src, mask, MODE_ZEROING); | 66 | vcgadd(dst, src, mask, MODE_ZEROING); |
| 67 | - } | 67 | + } |
| 68 | } | 68 | } |
| 69 | 69 | ||
| 70 | -#endif | 70 | +#endif |
| @@ -38,4 +38,4 @@ __simd_callee__ inline void asc_relu_impl(vector_float& dst, vector_float src, v | |||
| 38 | vrelu(dst, src, mask, MODE_ZEROING); | 38 | vrelu(dst, src, mask, MODE_ZEROING); |
| 39 | } | 39 | } |
| 40 | } | 40 | } |
| 41 | -#endif | 41 | +#endif |
| @@ -108,4 +108,4 @@ __simd_callee__ inline void asc_select_impl(vector_float& dst, vector_float src0 | |||
| 108 | vsel(dst, src0, src1, mask); | 108 | vsel(dst, src0, src1, mask); |
| 109 | } | 109 | } |
| 110 | } | 110 | } |
| 111 | -#endif | 111 | +#endif |
| @@ -9,11 +9,11 @@ | |||
| 9 | */ | 9 | */ |
| 10 | 10 | ||
| 11 | 11 | ||
| 12 | -#if !defined(ASCENDC_C_API_INCLUDE_COMPILER_INTERNAL_HEADERS) | 12 | +#if !defined(ASCENDC_C_API_INCLUDE_COMPILER_INTERNAL_HEADERS) |
| 13 | -#warning "impl/c_api/instr_impl/npu_arch_3510/vector_compute_impl/asc_set_va_reg_impl.h is an internal header file and must not be used directly. Functions or variables defined in this file maybe removed in the future. Please use "#include "c_api/asc_simd.h"" and use public functions or variables defined in interface headers files." | 13 | +#warning "impl/c_api/instr_impl/npu_arch_3510/vector_compute_impl/asc_set_va_reg_impl.h is an internal header file and must not be used directly. Functions or variables defined in this file maybe removed in the future. Please use "#include "c_api/asc_simd.h"" and use public functions or variables defined in interface headers files." |
| 14 | -#define ASCENDC_C_API_INCLUDE_COMPILER_INTERNAL_HEADERS | 14 | +#define ASCENDC_C_API_INCLUDE_COMPILER_INTERNAL_HEADERS |
| 15 | -#define UNDEF_ASCENDC_C_API_INCLUDE_COMPILER_INTERNAL_HEADERS_ASCENDC | 15 | +#define UNDEF_ASCENDC_C_API_INCLUDE_COMPILER_INTERNAL_HEADERS_ASCENDC |
| 16 | -#endif | 16 | +#endif |
| 17 | 17 | ||
| 18 | 18 | ||
| 19 | 19 | ||
| @@ -110,8 +110,7 @@ __aicore__ inline void asc_set_va_reg_impl(ub_addr8_t addr, __ubuf__ float** src | |||
| 110 | 110 | ||
| 111 | 111 | ||
| 112 | 112 | ||
| 113 | -#if defined(UNDEF_ASCENDC_C_API_INCLUDE_COMPILER_INTERNAL_HEADERS_ASCENDC) | 113 | +#if defined(UNDEF_ASCENDC_C_API_INCLUDE_COMPILER_INTERNAL_HEADERS_ASCENDC) |
| 114 | -#undef ASCENDC_C_API_INCLUDE_COMPILER_INTERNAL_HEADERS | 114 | +#undef ASCENDC_C_API_INCLUDE_COMPILER_INTERNAL_HEADERS |
| 115 | -#undef UNDEF_ASCENDC_C_API_INCLUDE_COMPILER_INTERNAL_HEADERS_ASCENDC | 115 | +#undef UNDEF_ASCENDC_C_API_INCLUDE_COMPILER_INTERNAL_HEADERS_ASCENDC |
| 116 | -#endif | 116 | +#endif |
| 117 | - | ||
| @@ -61,4 +61,4 @@ __simd_callee__ inline void asc_shiftleft_impl(vector_int32_t& dst, | |||
| 61 | } | 61 | } |
| 62 | } | 62 | } |
| 63 | 63 | ||
| 64 | -#endif | 64 | +#endif |
| @@ -59,4 +59,4 @@ __simd_callee__ inline void asc_shiftleft_scalar_impl(vector_int32_t& dst, vecto | |||
| 59 | vshls(dst, src, value, mask, MODE_ZEROING); | 59 | vshls(dst, src, value, mask, MODE_ZEROING); |
| 60 | } | 60 | } |
| 61 | } | 61 | } |
| 62 | -#endif | 62 | +#endif |
| @@ -61,4 +61,4 @@ __simd_callee__ inline void asc_shiftright_impl(vector_int32_t& dst, | |||
| 61 | } | 61 | } |
| 62 | } | 62 | } |
| 63 | 63 | ||
| 64 | -#endif | 64 | +#endif |
| @@ -59,4 +59,4 @@ __simd_callee__ inline void asc_shiftright_scalar_impl(vector_int32_t& dst, vect | |||
| 59 | vshrs(dst, src, value, mask, MODE_ZEROING); | 59 | vshrs(dst, src, value, mask, MODE_ZEROING); |
| 60 | } | 60 | } |
| 61 | } | 61 | } |
| 62 | -#endif | 62 | +#endif |
| @@ -39,4 +39,4 @@ __simd_callee__ inline void asc_sqrt_impl(vector_half& dst, vector_half src, vec | |||
| 39 | 39 | ||
| 40 | 40 | ||
| 41 | 41 | ||
| 42 | -#endif | 42 | +#endif |
| @@ -277,4 +277,4 @@ __simd_callee__ inline void asc_squeeze_with_status_impl(vector_fp8_e8m0_t& dst, | |||
| 277 | 277 | ||
| 278 | 278 | ||
| 279 | 279 | ||
| 280 | -#endif | 280 | +#endif |
| @@ -94,4 +94,4 @@ __simd_callee__ inline void asc_sub_impl(vector_bool& carry, vector_int32_t& dst | |||
| 94 | vsubc(carry, dst, src0, src1, mask); | 94 | vsubc(carry, dst, src0, src1, mask); |
| 95 | } | 95 | } |
| 96 | } | 96 | } |
| 97 | -#endif | 97 | +#endif |
| @@ -31,4 +31,4 @@ __simd_callee__ inline void asc_subc_impl(vector_bool& carry, vector_int32_t& ds | |||
| 31 | vsubcs(carry, dst, src0, src1, carry_src, mask); | 31 | vsubcs(carry, dst, src0, src1, carry_src, mask); |
| 32 | } | 32 | } |
| 33 | } | 33 | } |
| 34 | -#endif | 34 | +#endif |
| @@ -95,4 +95,4 @@ __simd_callee__ inline void asc_unpack_lower_impl(vector_bool& dst, vector_bool | |||
| 95 | } | 95 | } |
| 96 | } | 96 | } |
| 97 | 97 | ||
| 98 | -#endif | 98 | +#endif |
| @@ -72,4 +72,4 @@ __simd_callee__ inline void asc_unsqueeze_impl(vector_int32_t& dst, vector_bool | |||
| 72 | 72 | ||
| 73 | 73 | ||
| 74 | 74 | ||
| 75 | -#endif | 75 | +#endif |
| @@ -53,4 +53,4 @@ __simd_callee__ inline vector_bool asc_update_mask_b32_impl(uint32_t& value) | |||
| 53 | 53 | ||
| 54 | 54 | ||
| 55 | 55 | ||
| 56 | -#endif | 56 | +#endif |
| @@ -86,4 +86,4 @@ __simd_callee__ inline void asc_xor_impl(vector_bool& dst, vector_bool src0, vec | |||
| 86 | 86 | ||
| 87 | 87 | ||
| 88 | 88 | ||
| 89 | -#endif | 89 | +#endif |
| @@ -40,4 +40,4 @@ __simd_callee__ inline void asc_bfloat162e1m2x2_rd_v4_impl(vector_fp4x2_e1m2_t& | |||
| 40 | vcvt(dst, src, mask, ROUND_F, PART_P3, MODE_ZEROING); | 40 | vcvt(dst, src, mask, ROUND_F, PART_P3, MODE_ZEROING); |
| 41 | } | 41 | } |
| 42 | } | 42 | } |
| 43 | -#endif | 43 | +#endif |
| @@ -40,4 +40,4 @@ __simd_callee__ inline void asc_bfloat162e1m2x2_rn_v4_impl(vector_fp4x2_e1m2_t& | |||
| 40 | vcvt(dst, src, mask, ROUND_R, PART_P3, MODE_ZEROING); | 40 | vcvt(dst, src, mask, ROUND_R, PART_P3, MODE_ZEROING); |
| 41 | } | 41 | } |
| 42 | } | 42 | } |
| 43 | -#endif | 43 | +#endif |
| @@ -40,4 +40,4 @@ __simd_callee__ inline void asc_bfloat162e1m2x2_rna_v4_impl(vector_fp4x2_e1m2_t& | |||
| 40 | vcvt(dst, src, mask, ROUND_A, PART_P3, MODE_ZEROING); | 40 | vcvt(dst, src, mask, ROUND_A, PART_P3, MODE_ZEROING); |
| 41 | } | 41 | } |
| 42 | } | 42 | } |
| 43 | -#endif | 43 | +#endif |
| @@ -40,4 +40,4 @@ __simd_callee__ inline void asc_bfloat162e1m2x2_ru_v4_impl(vector_fp4x2_e1m2_t& | |||
| 40 | vcvt(dst, src, mask, ROUND_C, PART_P3, MODE_ZEROING); | 40 | vcvt(dst, src, mask, ROUND_C, PART_P3, MODE_ZEROING); |
| 41 | } | 41 | } |
| 42 | } | 42 | } |
| 43 | -#endif | 43 | +#endif |
| @@ -40,4 +40,4 @@ __simd_callee__ inline void asc_bfloat162e1m2x2_rz_v4_impl(vector_fp4x2_e1m2_t& | |||
| 40 | vcvt(dst, src, mask, ROUND_Z, PART_P3, MODE_ZEROING); | 40 | vcvt(dst, src, mask, ROUND_Z, PART_P3, MODE_ZEROING); |
| 41 | } | 41 | } |
| 42 | } | 42 | } |
| 43 | -#endif | 43 | +#endif |
| @@ -53,4 +53,4 @@ __simd_callee__ inline void asc_bfloat162e2m1x2_rd_v4_impl(vector_fp4x2_e2m1_t& | |||
| 53 | 53 | ||
| 54 | 54 | ||
| 55 | 55 | ||
| 56 | -#endif | 56 | +#endif |
| @@ -52,4 +52,4 @@ __simd_callee__ inline void asc_bfloat162e2m1x2_rn_v4_impl(vector_fp4x2_e2m1_t& | |||
| 52 | 52 | ||
| 53 | 53 | ||
| 54 | 54 | ||
| 55 | -#endif | 55 | +#endif |
| @@ -52,4 +52,4 @@ __simd_callee__ inline void asc_bfloat162e2m1x2_rna_v4_impl(vector_fp4x2_e2m1_t& | |||
| 52 | 52 | ||
| 53 | 53 | ||
| 54 | 54 | ||
| 55 | -#endif | 55 | +#endif |
| @@ -52,4 +52,4 @@ __simd_callee__ inline void asc_bfloat162e2m1x2_ru_v4_impl(vector_fp4x2_e2m1_t& | |||
| 52 | 52 | ||
| 53 | 53 | ||
| 54 | 54 | ||
| 55 | -#endif | 55 | +#endif |
| @@ -52,4 +52,4 @@ __simd_callee__ inline void asc_bfloat162e2m1x2_rz_v4_impl(vector_fp4x2_e2m1_t& | |||
| 52 | 52 | ||
| 53 | 53 | ||
| 54 | 54 | ||
| 55 | -#endif | 55 | +#endif |
| @@ -57,4 +57,4 @@ __simd_callee__ inline void asc_bfloat162int32_rd_sat_v2_impl(vector_int32_t& ds | |||
| 57 | 57 | ||
| 58 | 58 | ||
| 59 | 59 | ||
| 60 | -#endif | 60 | +#endif |
| @@ -57,4 +57,4 @@ __simd_callee__ inline void asc_bfloat162int32_rn_sat_v2_impl(vector_int32_t& ds | |||
| 57 | 57 | ||
| 58 | 58 | ||
| 59 | 59 | ||
| 60 | -#endif | 60 | +#endif |
| @@ -57,4 +57,4 @@ __simd_callee__ inline void asc_bfloat162int32_rna_sat_v2_impl(vector_int32_t& d | |||
| 57 | 57 | ||
| 58 | 58 | ||
| 59 | 59 | ||
| 60 | -#endif | 60 | +#endif |
| @@ -57,4 +57,4 @@ __simd_callee__ inline void asc_bfloat162int32_ru_sat_v2_impl(vector_int32_t& ds | |||
| 57 | 57 | ||
| 58 | 58 | ||
| 59 | 59 | ||
| 60 | -#endif | 60 | +#endif |
| @@ -57,4 +57,4 @@ __simd_callee__ inline void asc_bfloat162int32_rz_sat_v2_impl(vector_int32_t& ds | |||
| 57 | 57 | ||
| 58 | 58 | ||
| 59 | 59 | ||
| 60 | -#endif | 60 | +#endif |
| @@ -45,4 +45,4 @@ __simd_callee__ inline void asc_ceil_impl(vector_float& dst, vector_float src, v | |||
| 45 | 45 | ||
| 46 | 46 | ||
| 47 | 47 | ||
| 48 | -#endif | 48 | +#endif |
| @@ -40,4 +40,4 @@ __simd_callee__ inline void asc_e1m2x22bfloat16_v4_impl(vector_bfloat16_t& dst, | |||
| 40 | vcvt(dst, src, mask, PART_P3, MODE_ZEROING); | 40 | vcvt(dst, src, mask, PART_P3, MODE_ZEROING); |
| 41 | } | 41 | } |
| 42 | } | 42 | } |
| 43 | -#endif | 43 | +#endif |
| @@ -52,4 +52,4 @@ __simd_callee__ inline void asc_e2m1x22bfloat16_v4_impl(vector_bfloat16_t& dst, | |||
| 52 | 52 | ||
| 53 | 53 | ||
| 54 | 54 | ||
| 55 | -#endif | 55 | +#endif |
| @@ -58,4 +58,4 @@ __simd_callee__ inline void asc_e5m22float_v4_impl(vector_float& dst, vector_fp8 | |||
| 58 | 58 | ||
| 59 | 59 | ||
| 60 | 60 | ||
| 61 | -#endif | 61 | +#endif |
| @@ -58,4 +58,4 @@ __simd_callee__ inline void asc_float2bfloat16_rd_sat_v2_impl(vector_bfloat16_t& | |||
| 58 | 58 | ||
| 59 | 59 | ||
| 60 | 60 | ||
| 61 | -#endif | 61 | +#endif |
| @@ -58,4 +58,4 @@ __simd_callee__ inline void asc_float2bfloat16_rn_sat_v2_impl(vector_bfloat16_t& | |||
| 58 | 58 | ||
| 59 | 59 | ||
| 60 | 60 | ||
| 61 | -#endif | 61 | +#endif |
| @@ -58,4 +58,4 @@ __simd_callee__ inline void asc_float2bfloat16_rna_sat_v2_impl(vector_bfloat16_t | |||
| 58 | 58 | ||
| 59 | 59 | ||
| 60 | 60 | ||
| 61 | -#endif | 61 | +#endif |
| @@ -58,4 +58,4 @@ __simd_callee__ inline void asc_float2bfloat16_ru_sat_v2_impl(vector_bfloat16_t& | |||
| 58 | 58 | ||
| 59 | 59 | ||
| 60 | 60 | ||
| 61 | -#endif | 61 | +#endif |
| @@ -58,4 +58,4 @@ __simd_callee__ inline void asc_float2bfloat16_rz_sat_v2_impl(vector_bfloat16_t& | |||
| 58 | 58 | ||
| 59 | 59 | ||
| 60 | 60 | ||
| 61 | -#endif | 61 | +#endif |
| @@ -80,4 +80,4 @@ __simd_callee__ inline void asc_float2e4m3_rn_v4_impl(vector_fp8_e4m3fn_t& dst, | |||
| 80 | 80 | ||
| 81 | 81 | ||
| 82 | 82 | ||
| 83 | -#endif | 83 | +#endif |
| @@ -86,4 +86,4 @@ __simd_callee__ inline void asc_float2e5m2_rn_sat_v4_impl(vector_fp8_e5m2_t& dst | |||
| 86 | 86 | ||
| 87 | 87 | ||
| 88 | 88 | ||
| 89 | -#endif | 89 | +#endif |
| @@ -80,4 +80,4 @@ __simd_callee__ inline void asc_float2hif8_rh_v4_impl(vector_hifloat8_t& dst, ve | |||
| 80 | 80 | ||
| 81 | 81 | ||
| 82 | 82 | ||
| 83 | -#endif | 83 | +#endif |
| @@ -80,4 +80,4 @@ __simd_callee__ inline void asc_float2hif8_rna_v4_impl(vector_hifloat8_t& dst, v | |||
| 80 | 80 | ||
| 81 | 81 | ||
| 82 | 82 | ||
| 83 | -#endif | 83 | +#endif |
| @@ -52,4 +52,4 @@ __simd_callee__ inline void asc_float2int16_rd_sat_v2_impl(vector_int16_t& dst, | |||
| 52 | 52 | ||
| 53 | 53 | ||
| 54 | 54 | ||
| 55 | -#endif | 55 | +#endif |
| @@ -52,4 +52,4 @@ __simd_callee__ inline void asc_float2int16_rn_sat_v2_impl(vector_int16_t& dst, | |||
| 52 | 52 | ||
| 53 | 53 | ||
| 54 | 54 | ||
| 55 | -#endif | 55 | +#endif |
| @@ -52,4 +52,4 @@ __simd_callee__ inline void asc_float2int16_rna_sat_v2_impl(vector_int16_t& dst, | |||
| 52 | 52 | ||
| 53 | 53 | ||
| 54 | 54 | ||
| 55 | -#endif | 55 | +#endif |
| @@ -52,4 +52,4 @@ __simd_callee__ inline void asc_float2int16_ru_sat_v2_impl(vector_int16_t& dst, | |||
| 52 | 52 | ||
| 53 | 53 | ||
| 54 | 54 | ||
| 55 | -#endif | 55 | +#endif |
| @@ -52,4 +52,4 @@ __simd_callee__ inline void asc_float2int16_rz_sat_v2_impl(vector_int16_t& dst, | |||
| 52 | 52 | ||
| 53 | 53 | ||
| 54 | 54 | ||
| 55 | -#endif | 55 | +#endif |
| @@ -39,4 +39,4 @@ __simd_callee__ inline void asc_float2int32_rd_sat_impl(vector_int32_t& dst, vec | |||
| 39 | 39 | ||
| 40 | 40 | ||
| 41 | 41 | ||
| 42 | -#endif | 42 | +#endif |
| @@ -38,4 +38,4 @@ __simd_callee__ inline void asc_float2int32_rn_sat_impl(vector_int32_t& dst, vec | |||
| 38 | 38 | ||
| 39 | 39 | ||
| 40 | 40 | ||
| 41 | -#endif | 41 | +#endif |
| @@ -38,4 +38,4 @@ __simd_callee__ inline void asc_float2int32_rna_impl(vector_int32_t& dst, vector | |||
| 38 | 38 | ||
| 39 | 39 | ||
| 40 | 40 | ||
| 41 | -#endif | 41 | +#endif |
| @@ -38,4 +38,4 @@ __simd_callee__ inline void asc_float2int32_ru_impl(vector_int32_t& dst, vector_ | |||
| 38 | 38 | ||
| 39 | 39 | ||
| 40 | 40 | ||
| 41 | -#endif | 41 | +#endif |
| @@ -38,4 +38,4 @@ __simd_callee__ inline void asc_float2int32_rz_impl(vector_int32_t& dst, vector_ | |||
| 38 | 38 | ||
| 39 | 39 | ||
| 40 | 40 | ||
| 41 | -#endif | 41 | +#endif |
| @@ -58,4 +58,4 @@ __simd_callee__ inline void asc_float2int64_rd_sat_v2_impl(vector_int64_t& dst, | |||
| 58 | 58 | ||
| 59 | 59 | ||
| 60 | 60 | ||
| 61 | -#endif | 61 | +#endif |
| @@ -57,4 +57,4 @@ __simd_callee__ inline void asc_float2int64_rn_sat_v2_impl(vector_int64_t& dst, | |||
| 57 | 57 | ||
| 58 | 58 | ||
| 59 | 59 | ||
| 60 | -#endif | 60 | +#endif |
| @@ -58,4 +58,4 @@ __simd_callee__ inline void asc_float2int64_rna_sat_v2_impl(vector_int64_t& dst, | |||
| 58 | 58 | ||
| 59 | 59 | ||
| 60 | 60 | ||
| 61 | -#endif | 61 | +#endif |
| @@ -58,4 +58,4 @@ __simd_callee__ inline void asc_float2int64_ru_sat_v2_impl(vector_int64_t& dst, | |||
| 58 | 58 | ||
| 59 | 59 | ||
| 60 | 60 | ||
| 61 | -#endif | 61 | +#endif |
| @@ -58,4 +58,4 @@ __simd_callee__ inline void asc_float2int64_rz_sat_v2_impl(vector_int64_t& dst, | |||
| 58 | 58 | ||
| 59 | 59 | ||
| 60 | 60 | ||
| 61 | -#endif | 61 | +#endif |
| @@ -45,4 +45,4 @@ __simd_callee__ inline void asc_floor_impl(vector_float& dst, vector_float src, | |||
| 45 | 45 | ||
| 46 | 46 | ||
| 47 | 47 | ||
| 48 | -#endif | 48 | +#endif |
| @@ -19,4 +19,4 @@ __simd_callee__ inline void asc_half2bfloat16_rd_impl(vector_bfloat16_t& dst, ve | |||
| 19 | vcvt(dst, src, mask, ROUND_F, MODE_ZEROING); | 19 | vcvt(dst, src, mask, ROUND_F, MODE_ZEROING); |
| 20 | } | 20 | } |
| 21 | } | 21 | } |
| 22 | -#endif | 22 | +#endif |
| @@ -20,4 +20,4 @@ __simd_callee__ inline void asc_half2bfloat16_rn_impl(vector_bfloat16_t& dst, ve | |||
| 20 | } | 20 | } |
| 21 | } | 21 | } |
| 22 | 22 | ||
| 23 | -#endif | 23 | +#endif |
| @@ -20,4 +20,4 @@ __simd_callee__ inline void asc_half2bfloat16_rna_impl(vector_bfloat16_t& dst, v | |||
| 20 | } | 20 | } |
| 21 | } | 21 | } |
| 22 | 22 | ||
| 23 | -#endif | 23 | +#endif |
| @@ -20,4 +20,4 @@ __simd_callee__ inline void asc_half2bfloat16_ru_impl(vector_bfloat16_t& dst, ve | |||
| 20 | } | 20 | } |
| 21 | } | 21 | } |
| 22 | 22 | ||
| 23 | -#endif | 23 | +#endif |
| @@ -20,4 +20,4 @@ __simd_callee__ inline void asc_half2bfloat16_rz_impl(vector_bfloat16_t& dst, ve | |||
| 20 | } | 20 | } |
| 21 | } | 21 | } |
| 22 | 22 | ||
| 23 | -#endif | 23 | +#endif |
| @@ -44,4 +44,4 @@ __simd_callee__ inline void asc_half2float_v2_impl(vector_float& dst, vector_hal | |||
| 44 | 44 | ||
| 45 | 45 | ||
| 46 | 46 | ||
| 47 | -#endif | 47 | +#endif |
| @@ -43,4 +43,4 @@ __simd_callee__ inline void asc_half2int16_rd_sat_impl(vector_int16_t& dst, vect | |||
| 43 | 43 | ||
| 44 | 44 | ||
| 45 | 45 | ||
| 46 | -#endif | 46 | +#endif |
| @@ -43,4 +43,4 @@ __simd_callee__ inline void asc_half2int16_rn_sat_impl(vector_int16_t& dst, vect | |||
| 43 | 43 | ||
| 44 | 44 | ||
| 45 | 45 | ||
| 46 | -#endif | 46 | +#endif |
| @@ -43,4 +43,4 @@ __simd_callee__ inline void asc_half2int16_rna_sat_impl(vector_int16_t& dst, vec | |||
| 43 | 43 | ||
| 44 | 44 | ||
| 45 | 45 | ||
| 46 | -#endif | 46 | +#endif |
| @@ -43,4 +43,4 @@ __simd_callee__ inline void asc_half2int16_ru_sat_impl(vector_int16_t& dst, vect | |||
| 43 | 43 | ||
| 44 | 44 | ||
| 45 | 45 | ||
| 46 | -#endif | 46 | +#endif |
| @@ -43,4 +43,4 @@ __simd_callee__ inline void asc_half2int16_rz_sat_impl(vector_int16_t& dst, vect | |||
| 43 | 43 | ||
| 44 | 44 | ||
| 45 | 45 | ||
| 46 | -#endif | 46 | +#endif |
| @@ -44,4 +44,4 @@ __simd_callee__ inline void asc_half2int32_rd_v2_impl(vector_int32_t& dst, vecto | |||
| 44 | 44 | ||
| 45 | 45 | ||
| 46 | 46 | ||
| 47 | -#endif | 47 | +#endif |
| @@ -44,4 +44,4 @@ __simd_callee__ inline void asc_half2int32_rn_v2_impl(vector_int32_t& dst, vecto | |||
| 44 | 44 | ||
| 45 | 45 | ||
| 46 | 46 | ||
| 47 | -#endif | 47 | +#endif |
| @@ -44,4 +44,4 @@ __simd_callee__ inline void asc_half2int32_rna_v2_impl(vector_int32_t& dst, vect | |||
| 44 | 44 | ||
| 45 | 45 | ||
| 46 | 46 | ||
| 47 | -#endif | 47 | +#endif |
| @@ -44,4 +44,4 @@ __simd_callee__ inline void asc_half2int32_ru_v2_impl(vector_int32_t& dst, vecto | |||
| 44 | 44 | ||
| 45 | 45 | ||
| 46 | 46 | ||
| 47 | -#endif | 47 | +#endif |
| @@ -44,4 +44,4 @@ __simd_callee__ inline void asc_half2int32_rz_v2_impl(vector_int32_t& dst, vecto | |||
| 44 | 44 | ||
| 45 | 45 | ||
| 46 | 46 | ||
| 47 | -#endif | 47 | +#endif |
| @@ -70,4 +70,4 @@ __simd_callee__ inline void asc_half2int4x2_rd_sat_v4_impl(vector_int4x2_t& dst, | |||
| 70 | } | 70 | } |
| 71 | } | 71 | } |
| 72 | 72 | ||
| 73 | -#endif | 73 | +#endif |
| @@ -70,4 +70,4 @@ __simd_callee__ inline void asc_half2int4x2_rn_sat_v4_impl(vector_int4x2_t& dst, | |||
| 70 | } | 70 | } |
| 71 | } | 71 | } |
| 72 | 72 | ||
| 73 | -#endif | 73 | +#endif |
| @@ -70,4 +70,4 @@ __simd_callee__ inline void asc_half2int4x2_rna_sat_v4_impl(vector_int4x2_t& dst | |||
| 70 | } | 70 | } |
| 71 | } | 71 | } |
| 72 | 72 | ||
| 73 | -#endif | 73 | +#endif |
| @@ -70,4 +70,4 @@ __simd_callee__ inline void asc_half2int4x2_ru_sat_v4_impl(vector_int4x2_t& dst, | |||
| 70 | } | 70 | } |
| 71 | } | 71 | } |
| 72 | 72 | ||
| 73 | -#endif | 73 | +#endif |
| @@ -70,4 +70,4 @@ __simd_callee__ inline void asc_half2int4x2_rz_sat_v4_impl(vector_int4x2_t& dst, | |||
| 70 | } | 70 | } |
| 71 | } | 71 | } |
| 72 | 72 | ||
| 73 | -#endif | 73 | +#endif |
| @@ -58,4 +58,4 @@ __simd_callee__ inline void asc_half2uint8_rd_sat_v2_impl(vector_uint8_t& dst, v | |||
| 58 | 58 | ||
| 59 | 59 | ||
| 60 | 60 | ||
| 61 | -#endif | 61 | +#endif |
| @@ -58,4 +58,4 @@ __simd_callee__ inline void asc_half2uint8_rn_sat_v2_impl(vector_uint8_t& dst, v | |||
| 58 | 58 | ||
| 59 | 59 | ||
| 60 | 60 | ||
| 61 | -#endif | 61 | +#endif |
| @@ -58,4 +58,4 @@ __simd_callee__ inline void asc_half2uint8_rna_sat_v2_impl(vector_uint8_t& dst, | |||
| 58 | 58 | ||
| 59 | 59 | ||
| 60 | 60 | ||
| 61 | -#endif | 61 | +#endif |
| @@ -58,4 +58,4 @@ __simd_callee__ inline void asc_half2uint8_ru_sat_v2_impl(vector_uint8_t& dst, v | |||
| 58 | 58 | ||
| 59 | 59 | ||
| 60 | 60 | ||
| 61 | -#endif | 61 | +#endif |
| @@ -58,4 +58,4 @@ __simd_callee__ inline void asc_half2uint8_rz_sat_v2_impl(vector_uint8_t& dst, v | |||
| 58 | 58 | ||
| 59 | 59 | ||
| 60 | 60 | ||
| 61 | -#endif | 61 | +#endif |
| @@ -45,4 +45,4 @@ __simd_callee__ inline void asc_hif82float_v4_impl(vector_float& dst, vector_hif | |||
| 45 | } | 45 | } |
| 46 | } | 46 | } |
| 47 | 47 | ||
| 48 | -#endif | 48 | +#endif |
| @@ -44,4 +44,4 @@ __simd_callee__ inline void asc_hif82half_v2_impl(vector_half& dst, vector_hiflo | |||
| 44 | 44 | ||
| 45 | 45 | ||
| 46 | 46 | ||
| 47 | -#endif | 47 | +#endif |
| @@ -30,4 +30,4 @@ __simd_callee__ inline void asc_int162float_v2_impl(vector_float& dst, vector_in | |||
| 30 | vcvt(dst, src, mask, PART_ODD, MODE_ZEROING); | 30 | vcvt(dst, src, mask, PART_ODD, MODE_ZEROING); |
| 31 | } | 31 | } |
| 32 | } | 32 | } |
| 33 | -#endif | 33 | +#endif |
| @@ -37,4 +37,4 @@ __simd_callee__ inline void asc_int162half_rd_impl(vector_half& dst, vector_int1 | |||
| 37 | 37 | ||
| 38 | 38 | ||
| 39 | 39 | ||
| 40 | -#endif | 40 | +#endif |
| @@ -37,4 +37,4 @@ __simd_callee__ inline void asc_int162half_rn_impl(vector_half& dst, vector_int1 | |||
| 37 | 37 | ||
| 38 | 38 | ||
| 39 | 39 | ||
| 40 | -#endif | 40 | +#endif |
| @@ -37,4 +37,4 @@ __simd_callee__ inline void asc_int162half_rna_impl(vector_half& dst, vector_int | |||
| 37 | 37 | ||
| 38 | 38 | ||
| 39 | 39 | ||
| 40 | -#endif | 40 | +#endif |
| @@ -37,4 +37,4 @@ __simd_callee__ inline void asc_int162half_ru_impl(vector_half& dst, vector_int1 | |||
| 37 | 37 | ||
| 38 | 38 | ||
| 39 | 39 | ||
| 40 | -#endif | 40 | +#endif |
| @@ -37,4 +37,4 @@ __simd_callee__ inline void asc_int162half_rz_impl(vector_half& dst, vector_int1 | |||
| 37 | 37 | ||
| 38 | 38 | ||
| 39 | 39 | ||
| 40 | -#endif | 40 | +#endif |
| @@ -43,4 +43,4 @@ __simd_callee__ inline void asc_int162int32_v2_impl(vector_int32_t& dst, vector_ | |||
| 43 | 43 | ||
| 44 | 44 | ||
| 45 | 45 | ||
| 46 | -#endif | 46 | +#endif |
| @@ -58,4 +58,4 @@ __simd_callee__ inline void asc_int162uint8_sat_v2_impl(vector_uint8_t& dst, vec | |||
| 58 | 58 | ||
| 59 | 59 | ||
| 60 | 60 | ||
| 61 | -#endif | 61 | +#endif |
| @@ -44,4 +44,4 @@ __simd_callee__ inline void asc_int322int64_v2_impl(vector_int64_t& dst, vector_ | |||
| 44 | 44 | ||
| 45 | 45 | ||
| 46 | 46 | ||
| 47 | -#endif | 47 | +#endif |
| @@ -58,4 +58,4 @@ __simd_callee__ inline void asc_int322uint16_sat_v2_impl(vector_uint16_t& dst, v | |||
| 58 | 58 | ||
| 59 | 59 | ||
| 60 | 60 | ||
| 61 | -#endif | 61 | +#endif |
| @@ -72,4 +72,4 @@ __simd_callee__ inline void asc_int322uint8_sat_v4_impl(vector_uint8_t& dst, vec | |||
| 72 | vcvt(dst, src, mask, RS_ENABLE, PART_P3, MODE_ZEROING); | 72 | vcvt(dst, src, mask, RS_ENABLE, PART_P3, MODE_ZEROING); |
| 73 | } | 73 | } |
| 74 | } | 74 | } |
| 75 | -#endif | 75 | +#endif |
| @@ -58,4 +58,4 @@ __simd_callee__ inline void asc_int4x22half_v4_impl(vector_half& dst, vector_int | |||
| 58 | 58 | ||
| 59 | 59 | ||
| 60 | 60 | ||
| 61 | -#endif | 61 | +#endif |
| @@ -43,4 +43,4 @@ __simd_callee__ inline void asc_int642float_rd_v2_impl(vector_float& dst, vector | |||
| 43 | 43 | ||
| 44 | 44 | ||
| 45 | 45 | ||
| 46 | -#endif | 46 | +#endif |
| @@ -43,4 +43,4 @@ __simd_callee__ inline void asc_int642float_rn_v2_impl(vector_float& dst, vector | |||
| 43 | 43 | ||
| 44 | 44 | ||
| 45 | 45 | ||
| 46 | -#endif | 46 | +#endif |
| @@ -43,4 +43,4 @@ __simd_callee__ inline void asc_int642float_rna_v2_impl(vector_float& dst, vecto | |||
| 43 | 43 | ||
| 44 | 44 | ||
| 45 | 45 | ||
| 46 | -#endif | 46 | +#endif |
| @@ -43,4 +43,4 @@ __simd_callee__ inline void asc_int642float_ru_v2_impl(vector_float& dst, vector | |||
| 43 | 43 | ||
| 44 | 44 | ||
| 45 | 45 | ||
| 46 | -#endif | 46 | +#endif |
| @@ -43,4 +43,4 @@ __simd_callee__ inline void asc_int642float_rz_v2_impl(vector_float& dst, vector | |||
| 43 | 43 | ||
| 44 | 44 | ||
| 45 | 45 | ||
| 46 | -#endif | 46 | +#endif |
| @@ -58,4 +58,4 @@ __simd_callee__ inline void asc_int642int32_sat_v2_impl(vector_int32_t& dst, vec | |||
| 58 | 58 | ||
| 59 | 59 | ||
| 60 | 60 | ||
| 61 | -#endif | 61 | +#endif |
| @@ -43,4 +43,4 @@ __simd_callee__ inline void asc_int82half_v2_impl(vector_half& dst, vector_int8_ | |||
| 43 | 43 | ||
| 44 | 44 | ||
| 45 | 45 | ||
| 46 | -#endif | 46 | +#endif |
| @@ -44,4 +44,4 @@ __simd_callee__ inline void asc_int82int16_v2_impl(vector_int16_t& dst, vector_i | |||
| 44 | 44 | ||
| 45 | 45 | ||
| 46 | 46 | ||
| 47 | -#endif | 47 | +#endif |
| @@ -40,4 +40,4 @@ __simd_callee__ inline void asc_int82int32_v4_impl(vector_int32_t& dst, vector_i | |||
| 40 | vcvt(dst, src, mask, PART_P3, MODE_ZEROING); | 40 | vcvt(dst, src, mask, PART_P3, MODE_ZEROING); |
| 41 | } | 41 | } |
| 42 | } | 42 | } |
| 43 | -#endif | 43 | +#endif |
| @@ -45,4 +45,4 @@ __simd_callee__ inline void asc_rint_impl(vector_float& dst, vector_float src, v | |||
| 45 | 45 | ||
| 46 | 46 | ||
| 47 | 47 | ||
| 48 | -#endif | 48 | +#endif |
| @@ -45,4 +45,4 @@ __simd_callee__ inline void asc_round_impl(vector_float& dst, vector_float src, | |||
| 45 | 45 | ||
| 46 | 46 | ||
| 47 | 47 | ||
| 48 | -#endif | 48 | +#endif |
| @@ -45,4 +45,4 @@ __simd_callee__ inline void asc_trunc_impl(vector_float& dst, vector_float src, | |||
| 45 | 45 | ||
| 46 | 46 | ||
| 47 | 47 | ||
| 48 | -#endif | 48 | +#endif |
| @@ -27,4 +27,4 @@ __simd_callee__ inline void asc_uint162uint32_v2_impl(vector_uint32_t& dst, vect | |||
| 27 | } | 27 | } |
| 28 | } | 28 | } |
| 29 | 29 | ||
| 30 | -#endif | 30 | +#endif |
| @@ -52,4 +52,4 @@ __simd_callee__ inline void asc_uint322uint16_v2_impl(vector_uint16_t& dst, vect | |||
| 52 | 52 | ||
| 53 | 53 | ||
| 54 | 54 | ||
| 55 | -#endif | 55 | +#endif |
| @@ -85,4 +85,4 @@ __simd_callee__ inline void asc_uint322uint8_sat_v4_impl(vector_uint8_t& dst, ve | |||
| 85 | 85 | ||
| 86 | 86 | ||
| 87 | 87 | ||
| 88 | -#endif | 88 | +#endif |
| @@ -27,4 +27,4 @@ __simd_callee__ inline void asc_uint82half_v2_impl(vector_half& dst, vector_uint | |||
| 27 | } | 27 | } |
| 28 | } | 28 | } |
| 29 | 29 | ||
| 30 | -#endif | 30 | +#endif |
| @@ -44,4 +44,4 @@ __simd_callee__ inline void asc_uint82uint16_v2_impl(vector_uint16_t& dst, vecto | |||
| 44 | 44 | ||
| 45 | 45 | ||
| 46 | 46 | ||
| 47 | -#endif | 47 | +#endif |
| @@ -52,4 +52,4 @@ __simd_callee__ inline void asc_uint82uint32_v4_impl(vector_uint32_t& dst, vecto | |||
| 52 | 52 | ||
| 53 | 53 | ||
| 54 | 54 | ||
| 55 | -#endif | 55 | +#endif |
| @@ -54,73 +54,73 @@ | |||
| 54 | __simd_callee__ inline void asc_storealign(__ubuf__ int8_t* dst_align32b, vector_int8_t src, | 54 | __simd_callee__ inline void asc_storealign(__ubuf__ int8_t* dst_align32b, vector_int8_t src, |
| 55 | vector_bool mask) | 55 | vector_bool mask) |
| 56 | { | 56 | { |
| 57 | - asc_storealign_impl(dst_align32b, src, mask); | 57 | + asc_storealign_impl(dst_align32b, src, mask); |
| 58 | } | 58 | } |
| 59 | 59 | ||
| 60 | __simd_callee__ inline void asc_storealign(__ubuf__ uint8_t* dst_align32b, vector_uint8_t src, | 60 | __simd_callee__ inline void asc_storealign(__ubuf__ uint8_t* dst_align32b, vector_uint8_t src, |
| 61 | vector_bool mask) | 61 | vector_bool mask) |
| 62 | { | 62 | { |
| 63 | - asc_storealign_impl(dst_align32b, src, mask); | 63 | + asc_storealign_impl(dst_align32b, src, mask); |
| 64 | } | 64 | } |
| 65 | 65 | ||
| 66 | __simd_callee__ inline void asc_storealign(__ubuf__ int16_t* dst_align32b, vector_int16_t src, | 66 | __simd_callee__ inline void asc_storealign(__ubuf__ int16_t* dst_align32b, vector_int16_t src, |
| 67 | vector_bool mask) | 67 | vector_bool mask) |
| 68 | { | 68 | { |
| 69 | - asc_storealign_impl(dst_align32b, src, mask); | 69 | + asc_storealign_impl(dst_align32b, src, mask); |
| 70 | } | 70 | } |
| 71 | 71 | ||
| 72 | __simd_callee__ inline void asc_storealign(__ubuf__ uint16_t* dst_align32b, vector_uint16_t src, | 72 | __simd_callee__ inline void asc_storealign(__ubuf__ uint16_t* dst_align32b, vector_uint16_t src, |
| 73 | vector_bool mask) | 73 | vector_bool mask) |
| 74 | { | 74 | { |
| 75 | - asc_storealign_impl(dst_align32b, src, mask); | 75 | + asc_storealign_impl(dst_align32b, src, mask); |
| 76 | } | 76 | } |
| 77 | 77 | ||
| 78 | __simd_callee__ inline void asc_storealign(__ubuf__ int32_t* dst_align32b, vector_int32_t src, | 78 | __simd_callee__ inline void asc_storealign(__ubuf__ int32_t* dst_align32b, vector_int32_t src, |
| 79 | vector_bool mask) | 79 | vector_bool mask) |
| 80 | { | 80 | { |
| 81 | - asc_storealign_impl(dst_align32b, src, mask); | 81 | + asc_storealign_impl(dst_align32b, src, mask); |
| 82 | } | 82 | } |
| 83 | 83 | ||
| 84 | __simd_callee__ inline void asc_storealign(__ubuf__ uint32_t* dst_align32b, vector_uint32_t src, | 84 | __simd_callee__ inline void asc_storealign(__ubuf__ uint32_t* dst_align32b, vector_uint32_t src, |
| 85 | vector_bool mask) | 85 | vector_bool mask) |
| 86 | { | 86 | { |
| 87 | - asc_storealign_impl(dst_align32b, src, mask); | 87 | + asc_storealign_impl(dst_align32b, src, mask); |
| 88 | } | 88 | } |
| 89 | 89 | ||
| 90 | __simd_callee__ inline void asc_storealign(__ubuf__ half* dst_align32b, vector_half src, | 90 | __simd_callee__ inline void asc_storealign(__ubuf__ half* dst_align32b, vector_half src, |
| 91 | vector_bool mask) | 91 | vector_bool mask) |
| 92 | { | 92 | { |
| 93 | - asc_storealign_impl(dst_align32b, src, mask); | 93 | + asc_storealign_impl(dst_align32b, src, mask); |
| 94 | } | 94 | } |
| 95 | 95 | ||
| 96 | __simd_callee__ inline void asc_storealign(__ubuf__ float* dst_align32b, vector_float src, | 96 | __simd_callee__ inline void asc_storealign(__ubuf__ float* dst_align32b, vector_float src, |
| 97 | vector_bool mask) | 97 | vector_bool mask) |
| 98 | { | 98 | { |
| 99 | - asc_storealign_impl(dst_align32b, src, mask); | 99 | + asc_storealign_impl(dst_align32b, src, mask); |
| 100 | } | 100 | } |
| 101 | 101 | ||
| 102 | __simd_callee__ inline void asc_storealign(__ubuf__ bfloat16_t* dst_align32b, vector_bfloat16_t src, | 102 | __simd_callee__ inline void asc_storealign(__ubuf__ bfloat16_t* dst_align32b, vector_bfloat16_t src, |
| 103 | vector_bool mask) | 103 | vector_bool mask) |
| 104 | { | 104 | { |
| 105 | - asc_storealign_impl(dst_align32b, src, mask); | 105 | + asc_storealign_impl(dst_align32b, src, mask); |
| 106 | } | 106 | } |
| 107 | 107 | ||
| 108 | __simd_callee__ inline void asc_storealign(__ubuf__ fp8_e4m3fn_t* dst_align32b, vector_fp8_e4m3fn_t src, | 108 | __simd_callee__ inline void asc_storealign(__ubuf__ fp8_e4m3fn_t* dst_align32b, vector_fp8_e4m3fn_t src, |
| 109 | vector_bool mask) | 109 | vector_bool mask) |
| 110 | { | 110 | { |
| 111 | - asc_storealign_impl(dst_align32b, src, mask); | 111 | + asc_storealign_impl(dst_align32b, src, mask); |
| 112 | } | 112 | } |
| 113 | 113 | ||
| 114 | __simd_callee__ inline void asc_storealign(__ubuf__ hifloat8_t* dst_align32b, vector_hifloat8_t src, | 114 | __simd_callee__ inline void asc_storealign(__ubuf__ hifloat8_t* dst_align32b, vector_hifloat8_t src, |
| 115 | vector_bool mask) | 115 | vector_bool mask) |
| 116 | { | 116 | { |
| 117 | - asc_storealign_impl(dst_align32b, src, mask); | 117 | + asc_storealign_impl(dst_align32b, src, mask); |
| 118 | } | 118 | } |
| 119 | 119 | ||
| 120 | __simd_callee__ inline void asc_storealign(__ubuf__ fp8_e5m2_t* dst_align32b, vector_fp8_e5m2_t src, | 120 | __simd_callee__ inline void asc_storealign(__ubuf__ fp8_e5m2_t* dst_align32b, vector_fp8_e5m2_t src, |
| 121 | vector_bool mask) | 121 | vector_bool mask) |
| 122 | { | 122 | { |
| 123 | - asc_storealign_impl(dst_align32b, src, mask); | 123 | + asc_storealign_impl(dst_align32b, src, mask); |
| 124 | } | 124 | } |
| 125 | 125 | ||
| 126 | __simd_callee__ inline void asc_storealign(__ubuf__ fp8_e8m0_t* dst_align32b, vector_fp8_e8m0_t src, | 126 | __simd_callee__ inline void asc_storealign(__ubuf__ fp8_e8m0_t* dst_align32b, vector_fp8_e8m0_t src, |
| @@ -132,7 +132,7 @@ __simd_callee__ inline void asc_storealign(__ubuf__ fp8_e8m0_t* dst_align32b, v | |||
| 132 | __simd_callee__ inline void asc_storealign(__ubuf__ fp4x2_e2m1_t* dst_align32b, vector_fp4x2_e2m1_t src, | 132 | __simd_callee__ inline void asc_storealign(__ubuf__ fp4x2_e2m1_t* dst_align32b, vector_fp4x2_e2m1_t src, |
| 133 | vector_bool mask) | 133 | vector_bool mask) |
| 134 | { | 134 | { |
| 135 | - asc_storealign_impl(dst_align32b, src, mask); | 135 | + asc_storealign_impl(dst_align32b, src, mask); |
| 136 | } | 136 | } |
| 137 | 137 | ||
| 138 | __simd_callee__ inline void asc_storealign(__ubuf__ fp4x2_e1m2_t* dst_align32b, vector_fp4x2_e1m2_t src, | 138 | __simd_callee__ inline void asc_storealign(__ubuf__ fp4x2_e1m2_t* dst_align32b, vector_fp4x2_e1m2_t src, |
| @@ -232,55 +232,55 @@ __simd_callee__ inline void asc_storealign_1st(__ubuf__ int4b_t* dst_align32b, | |||
| 232 | __simd_callee__ inline void asc_storealign_pack(__ubuf__ int16_t* dst_align32b, vector_int16_t src, | 232 | __simd_callee__ inline void asc_storealign_pack(__ubuf__ int16_t* dst_align32b, vector_int16_t src, |
| 233 | vector_bool mask) | 233 | vector_bool mask) |
| 234 | { | 234 | { |
| 235 | - asc_storealign_pack_impl(dst_align32b, src, mask); | 235 | + asc_storealign_pack_impl(dst_align32b, src, mask); |
| 236 | } | 236 | } |
| 237 | 237 | ||
| 238 | __simd_callee__ inline void asc_storealign_pack(__ubuf__ uint16_t* dst_align32b, vector_uint16_t src, | 238 | __simd_callee__ inline void asc_storealign_pack(__ubuf__ uint16_t* dst_align32b, vector_uint16_t src, |
| 239 | vector_bool mask) | 239 | vector_bool mask) |
| 240 | { | 240 | { |
| 241 | - asc_storealign_pack_impl(dst_align32b, src, mask); | 241 | + asc_storealign_pack_impl(dst_align32b, src, mask); |
| 242 | } | 242 | } |
| 243 | 243 | ||
| 244 | __simd_callee__ inline void asc_storealign_pack(__ubuf__ int32_t* dst_align32b, vector_int32_t src, | 244 | __simd_callee__ inline void asc_storealign_pack(__ubuf__ int32_t* dst_align32b, vector_int32_t src, |
| 245 | vector_bool mask) | 245 | vector_bool mask) |
| 246 | { | 246 | { |
| 247 | - asc_storealign_pack_impl(dst_align32b, src, mask); | 247 | + asc_storealign_pack_impl(dst_align32b, src, mask); |
| 248 | } | 248 | } |
| 249 | 249 | ||
| 250 | __simd_callee__ inline void asc_storealign_pack(__ubuf__ uint32_t* dst_align32b, vector_uint32_t src, | 250 | __simd_callee__ inline void asc_storealign_pack(__ubuf__ uint32_t* dst_align32b, vector_uint32_t src, |
| 251 | vector_bool mask) | 251 | vector_bool mask) |
| 252 | { | 252 | { |
| 253 | - asc_storealign_pack_impl(dst_align32b, src, mask); | 253 | + asc_storealign_pack_impl(dst_align32b, src, mask); |
| 254 | } | 254 | } |
| 255 | 255 | ||
| 256 | __simd_callee__ inline void asc_storealign_pack(__ubuf__ int64_t* dst_align32b, vector_int64_t src, | 256 | __simd_callee__ inline void asc_storealign_pack(__ubuf__ int64_t* dst_align32b, vector_int64_t src, |
| 257 | vector_bool mask) | 257 | vector_bool mask) |
| 258 | { | 258 | { |
| 259 | - asc_storealign_pack_impl(dst_align32b, src, mask); | 259 | + asc_storealign_pack_impl(dst_align32b, src, mask); |
| 260 | } | 260 | } |
| 261 | 261 | ||
| 262 | __simd_callee__ inline void asc_storealign_pack(__ubuf__ uint64_t* dst_align32b, vector_uint64_t src, | 262 | __simd_callee__ inline void asc_storealign_pack(__ubuf__ uint64_t* dst_align32b, vector_uint64_t src, |
| 263 | vector_bool mask) | 263 | vector_bool mask) |
| 264 | { | 264 | { |
| 265 | - asc_storealign_pack_impl(dst_align32b, src, mask); | 265 | + asc_storealign_pack_impl(dst_align32b, src, mask); |
| 266 | } | 266 | } |
| 267 | 267 | ||
| 268 | __simd_callee__ inline void asc_storealign_pack(__ubuf__ half* dst_align32b, vector_half src, | 268 | __simd_callee__ inline void asc_storealign_pack(__ubuf__ half* dst_align32b, vector_half src, |
| 269 | vector_bool mask) | 269 | vector_bool mask) |
| 270 | { | 270 | { |
| 271 | - asc_storealign_pack_impl(dst_align32b, src, mask); | 271 | + asc_storealign_pack_impl(dst_align32b, src, mask); |
| 272 | } | 272 | } |
| 273 | 273 | ||
| 274 | __simd_callee__ inline void asc_storealign_pack(__ubuf__ float* dst_align32b, vector_float src, | 274 | __simd_callee__ inline void asc_storealign_pack(__ubuf__ float* dst_align32b, vector_float src, |
| 275 | vector_bool mask) | 275 | vector_bool mask) |
| 276 | { | 276 | { |
| 277 | - asc_storealign_pack_impl(dst_align32b, src, mask); | 277 | + asc_storealign_pack_impl(dst_align32b, src, mask); |
| 278 | } | 278 | } |
| 279 | 279 | ||
| 280 | __simd_callee__ inline void asc_storealign_pack(__ubuf__ bfloat16_t* dst_align32b, vector_bfloat16_t src, | 280 | __simd_callee__ inline void asc_storealign_pack(__ubuf__ bfloat16_t* dst_align32b, vector_bfloat16_t src, |
| 281 | vector_bool mask) | 281 | vector_bool mask) |
| 282 | { | 282 | { |
| 283 | - asc_storealign_pack_impl(dst_align32b, src, mask); | 283 | + asc_storealign_pack_impl(dst_align32b, src, mask); |
| 284 | } | 284 | } |
| 285 | 285 | ||
| 286 | // ==========asc_storealign_pack_v2(float/u32/s32)========= | 286 | // ==========asc_storealign_pack_v2(float/u32/s32)========= |
| @@ -289,7 +289,7 @@ __simd_callee__ inline void asc_storealign_pack(__ubuf__ bfloat16_t* dst_align3 | |||
| 289 | __simd_callee__ inline void asc_storealign_pack_v2(__ubuf__ int32_t* dst_align32b, vector_int32_t src, | 289 | __simd_callee__ inline void asc_storealign_pack_v2(__ubuf__ int32_t* dst_align32b, vector_int32_t src, |
| 290 | vector_bool mask) | 290 | vector_bool mask) |
| 291 | { | 291 | { |
| 292 | - asc_storealign_pack_v2_impl(dst_align32b, src, mask); | 292 | + asc_storealign_pack_v2_impl(dst_align32b, src, mask); |
| 293 | } | 293 | } |
| 294 | 294 | ||
| 295 | [[deprecated("NOTICE: asc_storealign_pack_v2 is deprecated. " | 295 | [[deprecated("NOTICE: asc_storealign_pack_v2 is deprecated. " |
| @@ -297,7 +297,7 @@ __simd_callee__ inline void asc_storealign_pack_v2(__ubuf__ int32_t* dst_align3 | |||
| 297 | __simd_callee__ inline void asc_storealign_pack_v2(__ubuf__ uint32_t* dst_align32b, vector_uint32_t src, | 297 | __simd_callee__ inline void asc_storealign_pack_v2(__ubuf__ uint32_t* dst_align32b, vector_uint32_t src, |
| 298 | vector_bool mask) | 298 | vector_bool mask) |
| 299 | { | 299 | { |
| 300 | - asc_storealign_pack_v2_impl(dst_align32b, src, mask); | 300 | + asc_storealign_pack_v2_impl(dst_align32b, src, mask); |
| 301 | } | 301 | } |
| 302 | 302 | ||
| 303 | [[deprecated("NOTICE: asc_storealign_pack_v2 is deprecated. " | 303 | [[deprecated("NOTICE: asc_storealign_pack_v2 is deprecated. " |
| @@ -305,74 +305,74 @@ __simd_callee__ inline void asc_storealign_pack_v2(__ubuf__ uint32_t* dst_align | |||
| 305 | __simd_callee__ inline void asc_storealign_pack_v2(__ubuf__ float* dst_align32b, vector_float src, | 305 | __simd_callee__ inline void asc_storealign_pack_v2(__ubuf__ float* dst_align32b, vector_float src, |
| 306 | vector_bool mask) | 306 | vector_bool mask) |
| 307 | { | 307 | { |
| 308 | - asc_storealign_pack_v2_impl(dst_align32b, src, mask); | 308 | + asc_storealign_pack_v2_impl(dst_align32b, src, mask); |
| 309 | } | 309 | } |
| 310 | 310 | ||
| 311 | // ==========asc_storealign_intlv(u8/s8/half/u16/s16/u32/s32/bf16/e4m3/e5m2/e8m0/e2m1/e1m2)========= | 311 | // ==========asc_storealign_intlv(u8/s8/half/u16/s16/u32/s32/bf16/e4m3/e5m2/e8m0/e2m1/e1m2)========= |
| 312 | __simd_callee__ inline void asc_storealign_intlv(__ubuf__ int8_t* dst_align32b, vector_int8_t src0, | 312 | __simd_callee__ inline void asc_storealign_intlv(__ubuf__ int8_t* dst_align32b, vector_int8_t src0, |
| 313 | vector_int8_t src1) | 313 | vector_int8_t src1) |
| 314 | { | 314 | { |
| 315 | - asc_storealign_intlv_impl(dst_align32b, src0, src1); | 315 | + asc_storealign_intlv_impl(dst_align32b, src0, src1); |
| 316 | } | 316 | } |
| 317 | 317 | ||
| 318 | __simd_callee__ inline void asc_storealign_intlv(__ubuf__ uint8_t* dst_align32b, vector_uint8_t src0, | 318 | __simd_callee__ inline void asc_storealign_intlv(__ubuf__ uint8_t* dst_align32b, vector_uint8_t src0, |
| 319 | vector_uint8_t src1) | 319 | vector_uint8_t src1) |
| 320 | { | 320 | { |
| 321 | - asc_storealign_intlv_impl(dst_align32b, src0, src1); | 321 | + asc_storealign_intlv_impl(dst_align32b, src0, src1); |
| 322 | } | 322 | } |
| 323 | 323 | ||
| 324 | __simd_callee__ inline void asc_storealign_intlv(__ubuf__ int16_t* dst_align32b, vector_int16_t src0, | 324 | __simd_callee__ inline void asc_storealign_intlv(__ubuf__ int16_t* dst_align32b, vector_int16_t src0, |
| 325 | vector_int16_t src1) | 325 | vector_int16_t src1) |
| 326 | { | 326 | { |
| 327 | - asc_storealign_intlv_impl(dst_align32b, src0, src1); | 327 | + asc_storealign_intlv_impl(dst_align32b, src0, src1); |
| 328 | } | 328 | } |
| 329 | 329 | ||
| 330 | __simd_callee__ inline void asc_storealign_intlv(__ubuf__ uint16_t* dst_align32b, vector_uint16_t src0, | 330 | __simd_callee__ inline void asc_storealign_intlv(__ubuf__ uint16_t* dst_align32b, vector_uint16_t src0, |
| 331 | vector_uint16_t src1) | 331 | vector_uint16_t src1) |
| 332 | { | 332 | { |
| 333 | - asc_storealign_intlv_impl(dst_align32b, src0, src1); | 333 | + asc_storealign_intlv_impl(dst_align32b, src0, src1); |
| 334 | } | 334 | } |
| 335 | 335 | ||
| 336 | __simd_callee__ inline void asc_storealign_intlv(__ubuf__ int32_t* dst_align32b, vector_int32_t src0, | 336 | __simd_callee__ inline void asc_storealign_intlv(__ubuf__ int32_t* dst_align32b, vector_int32_t src0, |
| 337 | vector_int32_t src1) | 337 | vector_int32_t src1) |
| 338 | { | 338 | { |
| 339 | - asc_storealign_intlv_impl(dst_align32b, src0, src1); | 339 | + asc_storealign_intlv_impl(dst_align32b, src0, src1); |
| 340 | } | 340 | } |
| 341 | 341 | ||
| 342 | __simd_callee__ inline void asc_storealign_intlv(__ubuf__ uint32_t* dst_align32b, vector_uint32_t src0, | 342 | __simd_callee__ inline void asc_storealign_intlv(__ubuf__ uint32_t* dst_align32b, vector_uint32_t src0, |
| 343 | vector_uint32_t src1) | 343 | vector_uint32_t src1) |
| 344 | { | 344 | { |
| 345 | - asc_storealign_intlv_impl(dst_align32b, src0, src1); | 345 | + asc_storealign_intlv_impl(dst_align32b, src0, src1); |
| 346 | } | 346 | } |
| 347 | 347 | ||
| 348 | __simd_callee__ inline void asc_storealign_intlv(__ubuf__ half* dst_align32b, vector_half src0, | 348 | __simd_callee__ inline void asc_storealign_intlv(__ubuf__ half* dst_align32b, vector_half src0, |
| 349 | vector_half src1) | 349 | vector_half src1) |
| 350 | { | 350 | { |
| 351 | - asc_storealign_intlv_impl(dst_align32b, src0, src1); | 351 | + asc_storealign_intlv_impl(dst_align32b, src0, src1); |
| 352 | } | 352 | } |
| 353 | 353 | ||
| 354 | __simd_callee__ inline void asc_storealign_intlv(__ubuf__ bfloat16_t* dst_align32b, vector_bfloat16_t src0, | 354 | __simd_callee__ inline void asc_storealign_intlv(__ubuf__ bfloat16_t* dst_align32b, vector_bfloat16_t src0, |
| 355 | vector_bfloat16_t src1) | 355 | vector_bfloat16_t src1) |
| 356 | { | 356 | { |
| 357 | - asc_storealign_intlv_impl(dst_align32b, src0, src1); | 357 | + asc_storealign_intlv_impl(dst_align32b, src0, src1); |
| 358 | } | 358 | } |
| 359 | 359 | ||
| 360 | __simd_callee__ inline void asc_storealign_intlv(__ubuf__ fp8_e4m3fn_t* dst_align32b, vector_fp8_e4m3fn_t src0, | 360 | __simd_callee__ inline void asc_storealign_intlv(__ubuf__ fp8_e4m3fn_t* dst_align32b, vector_fp8_e4m3fn_t src0, |
| 361 | vector_fp8_e4m3fn_t src1) | 361 | vector_fp8_e4m3fn_t src1) |
| 362 | { | 362 | { |
| 363 | - asc_storealign_intlv_impl(dst_align32b, src0, src1); | 363 | + asc_storealign_intlv_impl(dst_align32b, src0, src1); |
| 364 | } | 364 | } |
| 365 | 365 | ||
| 366 | __simd_callee__ inline void asc_storealign_intlv(__ubuf__ hifloat8_t* dst_align32b, vector_hifloat8_t src0, | 366 | __simd_callee__ inline void asc_storealign_intlv(__ubuf__ hifloat8_t* dst_align32b, vector_hifloat8_t src0, |
| 367 | vector_hifloat8_t src1) | 367 | vector_hifloat8_t src1) |
| 368 | { | 368 | { |
| 369 | - asc_storealign_intlv_impl(dst_align32b, src0, src1); | 369 | + asc_storealign_intlv_impl(dst_align32b, src0, src1); |
| 370 | } | 370 | } |
| 371 | 371 | ||
| 372 | __simd_callee__ inline void asc_storealign_intlv(__ubuf__ fp8_e5m2_t* dst_align32b, vector_fp8_e5m2_t src0, | 372 | __simd_callee__ inline void asc_storealign_intlv(__ubuf__ fp8_e5m2_t* dst_align32b, vector_fp8_e5m2_t src0, |
| 373 | vector_fp8_e5m2_t src1) | 373 | vector_fp8_e5m2_t src1) |
| 374 | { | 374 | { |
| 375 | - asc_storealign_intlv_impl(dst_align32b, src0, src1); | 375 | + asc_storealign_intlv_impl(dst_align32b, src0, src1); |
| 376 | } | 376 | } |
| 377 | 377 | ||
| 378 | __simd_callee__ inline void asc_storealign_intlv(__ubuf__ fp8_e8m0_t* dst_align32b, vector_fp8_e8m0_t src0, | 378 | __simd_callee__ inline void asc_storealign_intlv(__ubuf__ fp8_e8m0_t* dst_align32b, vector_fp8_e8m0_t src0, |
| @@ -404,73 +404,73 @@ __simd_callee__ inline void asc_storealign_intlv(__ubuf__ int4b_t* dst_align32b | |||
| 404 | __simd_callee__ inline void asc_storealign(__ubuf__ int8_t* dst_align32b, vector_int8_t src, addr_reg offset, | 404 | __simd_callee__ inline void asc_storealign(__ubuf__ int8_t* dst_align32b, vector_int8_t src, addr_reg offset, |
| 405 | vector_bool mask) | 405 | vector_bool mask) |
| 406 | { | 406 | { |
| 407 | - asc_storealign_impl(dst_align32b, src, offset, mask); | 407 | + asc_storealign_impl(dst_align32b, src, offset, mask); |
| 408 | } | 408 | } |
| 409 | 409 | ||
| 410 | __simd_callee__ inline void asc_storealign(__ubuf__ uint8_t* dst_align32b, vector_uint8_t src, addr_reg offset, | 410 | __simd_callee__ inline void asc_storealign(__ubuf__ uint8_t* dst_align32b, vector_uint8_t src, addr_reg offset, |
| 411 | vector_bool mask) | 411 | vector_bool mask) |
| 412 | { | 412 | { |
| 413 | - asc_storealign_impl(dst_align32b, src, offset, mask); | 413 | + asc_storealign_impl(dst_align32b, src, offset, mask); |
| 414 | } | 414 | } |
| 415 | 415 | ||
| 416 | __simd_callee__ inline void asc_storealign(__ubuf__ int16_t* dst_align32b, vector_int16_t src, addr_reg offset, | 416 | __simd_callee__ inline void asc_storealign(__ubuf__ int16_t* dst_align32b, vector_int16_t src, addr_reg offset, |
| 417 | vector_bool mask) | 417 | vector_bool mask) |
| 418 | { | 418 | { |
| 419 | - asc_storealign_impl(dst_align32b, src, offset, mask); | 419 | + asc_storealign_impl(dst_align32b, src, offset, mask); |
| 420 | } | 420 | } |
| 421 | 421 | ||
| 422 | __simd_callee__ inline void asc_storealign(__ubuf__ uint16_t* dst_align32b, vector_uint16_t src, addr_reg offset, | 422 | __simd_callee__ inline void asc_storealign(__ubuf__ uint16_t* dst_align32b, vector_uint16_t src, addr_reg offset, |
| 423 | vector_bool mask) | 423 | vector_bool mask) |
| 424 | { | 424 | { |
| 425 | - asc_storealign_impl(dst_align32b, src, offset, mask); | 425 | + asc_storealign_impl(dst_align32b, src, offset, mask); |
| 426 | } | 426 | } |
| 427 | 427 | ||
| 428 | __simd_callee__ inline void asc_storealign(__ubuf__ int32_t* dst_align32b, vector_int32_t src, addr_reg offset, | 428 | __simd_callee__ inline void asc_storealign(__ubuf__ int32_t* dst_align32b, vector_int32_t src, addr_reg offset, |
| 429 | vector_bool mask) | 429 | vector_bool mask) |
| 430 | { | 430 | { |
| 431 | - asc_storealign_impl(dst_align32b, src, offset, mask); | 431 | + asc_storealign_impl(dst_align32b, src, offset, mask); |
| 432 | } | 432 | } |
| 433 | 433 | ||
| 434 | __simd_callee__ inline void asc_storealign(__ubuf__ uint32_t* dst_align32b, vector_uint32_t src, addr_reg offset, | 434 | __simd_callee__ inline void asc_storealign(__ubuf__ uint32_t* dst_align32b, vector_uint32_t src, addr_reg offset, |
| 435 | vector_bool mask) | 435 | vector_bool mask) |
| 436 | { | 436 | { |
| 437 | - asc_storealign_impl(dst_align32b, src, offset, mask); | 437 | + asc_storealign_impl(dst_align32b, src, offset, mask); |
| 438 | } | 438 | } |
| 439 | 439 | ||
| 440 | __simd_callee__ inline void asc_storealign(__ubuf__ half* dst_align32b, vector_half src, addr_reg offset, | 440 | __simd_callee__ inline void asc_storealign(__ubuf__ half* dst_align32b, vector_half src, addr_reg offset, |
| 441 | vector_bool mask) | 441 | vector_bool mask) |
| 442 | { | 442 | { |
| 443 | - asc_storealign_impl(dst_align32b, src, offset, mask); | 443 | + asc_storealign_impl(dst_align32b, src, offset, mask); |
| 444 | } | 444 | } |
| 445 | 445 | ||
| 446 | __simd_callee__ inline void asc_storealign(__ubuf__ float* dst_align32b, vector_float src, addr_reg offset, | 446 | __simd_callee__ inline void asc_storealign(__ubuf__ float* dst_align32b, vector_float src, addr_reg offset, |
| 447 | vector_bool mask) | 447 | vector_bool mask) |
| 448 | { | 448 | { |
| 449 | - asc_storealign_impl(dst_align32b, src, offset, mask); | 449 | + asc_storealign_impl(dst_align32b, src, offset, mask); |
| 450 | } | 450 | } |
| 451 | 451 | ||
| 452 | __simd_callee__ inline void asc_storealign(__ubuf__ bfloat16_t* dst_align32b, vector_bfloat16_t src, addr_reg offset, | 452 | __simd_callee__ inline void asc_storealign(__ubuf__ bfloat16_t* dst_align32b, vector_bfloat16_t src, addr_reg offset, |
| 453 | vector_bool mask) | 453 | vector_bool mask) |
| 454 | { | 454 | { |
| 455 | - asc_storealign_impl(dst_align32b, src, offset, mask); | 455 | + asc_storealign_impl(dst_align32b, src, offset, mask); |
| 456 | } | 456 | } |
| 457 | 457 | ||
| 458 | __simd_callee__ inline void asc_storealign(__ubuf__ fp8_e4m3fn_t* dst_align32b, vector_fp8_e4m3fn_t src, addr_reg offset, | 458 | __simd_callee__ inline void asc_storealign(__ubuf__ fp8_e4m3fn_t* dst_align32b, vector_fp8_e4m3fn_t src, addr_reg offset, |
| 459 | vector_bool mask) | 459 | vector_bool mask) |
| 460 | { | 460 | { |
| 461 | - asc_storealign_impl(dst_align32b, src, offset, mask); | 461 | + asc_storealign_impl(dst_align32b, src, offset, mask); |
| 462 | } | 462 | } |
| 463 | 463 | ||
| 464 | __simd_callee__ inline void asc_storealign(__ubuf__ hifloat8_t* dst_align32b, vector_hifloat8_t src, addr_reg offset, | 464 | __simd_callee__ inline void asc_storealign(__ubuf__ hifloat8_t* dst_align32b, vector_hifloat8_t src, addr_reg offset, |
| 465 | vector_bool mask) | 465 | vector_bool mask) |
| 466 | { | 466 | { |
| 467 | - asc_storealign_impl(dst_align32b, src, offset, mask); | 467 | + asc_storealign_impl(dst_align32b, src, offset, mask); |
| 468 | } | 468 | } |
| 469 | 469 | ||
| 470 | __simd_callee__ inline void asc_storealign(__ubuf__ fp8_e5m2_t* dst_align32b, vector_fp8_e5m2_t src, addr_reg offset, | 470 | __simd_callee__ inline void asc_storealign(__ubuf__ fp8_e5m2_t* dst_align32b, vector_fp8_e5m2_t src, addr_reg offset, |
| 471 | vector_bool mask) | 471 | vector_bool mask) |
| 472 | { | 472 | { |
| 473 | - asc_storealign_impl(dst_align32b, src, offset, mask); | 473 | + asc_storealign_impl(dst_align32b, src, offset, mask); |
| 474 | } | 474 | } |
| 475 | 475 | ||
| 476 | __simd_callee__ inline void asc_storealign(__ubuf__ fp8_e8m0_t* dst_align32b, vector_fp8_e8m0_t src, addr_reg offset, | 476 | __simd_callee__ inline void asc_storealign(__ubuf__ fp8_e8m0_t* dst_align32b, vector_fp8_e8m0_t src, addr_reg offset, |
| @@ -482,7 +482,7 @@ __simd_callee__ inline void asc_storealign(__ubuf__ fp8_e8m0_t* dst_align32b, v | |||
| 482 | __simd_callee__ inline void asc_storealign(__ubuf__ fp4x2_e2m1_t* dst_align32b, vector_fp4x2_e2m1_t src, addr_reg offset, | 482 | __simd_callee__ inline void asc_storealign(__ubuf__ fp4x2_e2m1_t* dst_align32b, vector_fp4x2_e2m1_t src, addr_reg offset, |
| 483 | vector_bool mask) | 483 | vector_bool mask) |
| 484 | { | 484 | { |
| 485 | - asc_storealign_impl(dst_align32b, src, offset, mask); | 485 | + asc_storealign_impl(dst_align32b, src, offset, mask); |
| 486 | } | 486 | } |
| 487 | 487 | ||
| 488 | __simd_callee__ inline void asc_storealign(__ubuf__ fp4x2_e1m2_t* dst_align32b, vector_fp4x2_e1m2_t src, addr_reg offset, | 488 | __simd_callee__ inline void asc_storealign(__ubuf__ fp4x2_e1m2_t* dst_align32b, vector_fp4x2_e1m2_t src, addr_reg offset, |
| @@ -582,55 +582,55 @@ __simd_callee__ inline void asc_storealign_1st(__ubuf__ int4b_t* dst_align32b, | |||
| 582 | __simd_callee__ inline void asc_storealign_pack(__ubuf__ int16_t* dst_align32b, vector_int16_t src, addr_reg offset, | 582 | __simd_callee__ inline void asc_storealign_pack(__ubuf__ int16_t* dst_align32b, vector_int16_t src, addr_reg offset, |
| 583 | vector_bool mask) | 583 | vector_bool mask) |
| 584 | { | 584 | { |
| 585 | - asc_storealign_pack_impl(dst_align32b, src, offset, mask); | 585 | + asc_storealign_pack_impl(dst_align32b, src, offset, mask); |
| 586 | } | 586 | } |
| 587 | 587 | ||
| 588 | __simd_callee__ inline void asc_storealign_pack(__ubuf__ uint16_t* dst_align32b, vector_uint16_t src, addr_reg offset, | 588 | __simd_callee__ inline void asc_storealign_pack(__ubuf__ uint16_t* dst_align32b, vector_uint16_t src, addr_reg offset, |
| 589 | vector_bool mask) | 589 | vector_bool mask) |
| 590 | { | 590 | { |
| 591 | - asc_storealign_pack_impl(dst_align32b, src, offset, mask); | 591 | + asc_storealign_pack_impl(dst_align32b, src, offset, mask); |
| 592 | } | 592 | } |
| 593 | 593 | ||
| 594 | __simd_callee__ inline void asc_storealign_pack(__ubuf__ int32_t* dst_align32b, vector_int32_t src, addr_reg offset, | 594 | __simd_callee__ inline void asc_storealign_pack(__ubuf__ int32_t* dst_align32b, vector_int32_t src, addr_reg offset, |
| 595 | vector_bool mask) | 595 | vector_bool mask) |
| 596 | { | 596 | { |
| 597 | - asc_storealign_pack_impl(dst_align32b, src, offset, mask); | 597 | + asc_storealign_pack_impl(dst_align32b, src, offset, mask); |
| 598 | } | 598 | } |
| 599 | 599 | ||
| 600 | __simd_callee__ inline void asc_storealign_pack(__ubuf__ uint32_t* dst_align32b, vector_uint32_t src, addr_reg offset, | 600 | __simd_callee__ inline void asc_storealign_pack(__ubuf__ uint32_t* dst_align32b, vector_uint32_t src, addr_reg offset, |
| 601 | vector_bool mask) | 601 | vector_bool mask) |
| 602 | { | 602 | { |
| 603 | - asc_storealign_pack_impl(dst_align32b, src, offset, mask); | 603 | + asc_storealign_pack_impl(dst_align32b, src, offset, mask); |
| 604 | } | 604 | } |
| 605 | 605 | ||
| 606 | __simd_callee__ inline void asc_storealign_pack(__ubuf__ int64_t* dst_align32b, vector_int64_t src, addr_reg offset, | 606 | __simd_callee__ inline void asc_storealign_pack(__ubuf__ int64_t* dst_align32b, vector_int64_t src, addr_reg offset, |
| 607 | vector_bool mask) | 607 | vector_bool mask) |
| 608 | { | 608 | { |
| 609 | - asc_storealign_pack_impl(dst_align32b, src, offset, mask); | 609 | + asc_storealign_pack_impl(dst_align32b, src, offset, mask); |
| 610 | } | 610 | } |
| 611 | 611 | ||
| 612 | __simd_callee__ inline void asc_storealign_pack(__ubuf__ uint64_t* dst_align32b, vector_uint64_t src, addr_reg offset, | 612 | __simd_callee__ inline void asc_storealign_pack(__ubuf__ uint64_t* dst_align32b, vector_uint64_t src, addr_reg offset, |
| 613 | vector_bool mask) | 613 | vector_bool mask) |
| 614 | { | 614 | { |
| 615 | - asc_storealign_pack_impl(dst_align32b, src, offset, mask); | 615 | + asc_storealign_pack_impl(dst_align32b, src, offset, mask); |
| 616 | } | 616 | } |
| 617 | 617 | ||
| 618 | __simd_callee__ inline void asc_storealign_pack(__ubuf__ half* dst_align32b, vector_half src, addr_reg offset, | 618 | __simd_callee__ inline void asc_storealign_pack(__ubuf__ half* dst_align32b, vector_half src, addr_reg offset, |
| 619 | vector_bool mask) | 619 | vector_bool mask) |
| 620 | { | 620 | { |
| 621 | - asc_storealign_pack_impl(dst_align32b, src, offset, mask); | 621 | + asc_storealign_pack_impl(dst_align32b, src, offset, mask); |
| 622 | } | 622 | } |
| 623 | 623 | ||
| 624 | __simd_callee__ inline void asc_storealign_pack(__ubuf__ float* dst_align32b, vector_float src, addr_reg offset, | 624 | __simd_callee__ inline void asc_storealign_pack(__ubuf__ float* dst_align32b, vector_float src, addr_reg offset, |
| 625 | vector_bool mask) | 625 | vector_bool mask) |
| 626 | { | 626 | { |
| 627 | - asc_storealign_pack_impl(dst_align32b, src, offset, mask); | 627 | + asc_storealign_pack_impl(dst_align32b, src, offset, mask); |
| 628 | } | 628 | } |
| 629 | 629 | ||
| 630 | __simd_callee__ inline void asc_storealign_pack(__ubuf__ bfloat16_t* dst_align32b, vector_bfloat16_t src, addr_reg offset, | 630 | __simd_callee__ inline void asc_storealign_pack(__ubuf__ bfloat16_t* dst_align32b, vector_bfloat16_t src, addr_reg offset, |
| 631 | vector_bool mask) | 631 | vector_bool mask) |
| 632 | { | 632 | { |
| 633 | - asc_storealign_pack_impl(dst_align32b, src, offset, mask); | 633 | + asc_storealign_pack_impl(dst_align32b, src, offset, mask); |
| 634 | } | 634 | } |
| 635 | 635 | ||
| 636 | // ==========asc_storealign_pack_v2(float/u32/s32)========= | 636 | // ==========asc_storealign_pack_v2(float/u32/s32)========= |
| @@ -639,7 +639,7 @@ __simd_callee__ inline void asc_storealign_pack(__ubuf__ bfloat16_t* dst_align3 | |||
| 639 | __simd_callee__ inline void asc_storealign_pack_v2(__ubuf__ int32_t* dst_align32b, vector_int32_t src, addr_reg offset, | 639 | __simd_callee__ inline void asc_storealign_pack_v2(__ubuf__ int32_t* dst_align32b, vector_int32_t src, addr_reg offset, |
| 640 | vector_bool mask) | 640 | vector_bool mask) |
| 641 | { | 641 | { |
| 642 | - asc_storealign_pack_v2_impl(dst_align32b, src, offset, mask); | 642 | + asc_storealign_pack_v2_impl(dst_align32b, src, offset, mask); |
| 643 | } | 643 | } |
| 644 | 644 | ||
| 645 | [[deprecated("NOTICE: asc_storealign_pack_v2 is deprecated. " | 645 | [[deprecated("NOTICE: asc_storealign_pack_v2 is deprecated. " |
| @@ -647,7 +647,7 @@ __simd_callee__ inline void asc_storealign_pack_v2(__ubuf__ int32_t* dst_align3 | |||
| 647 | __simd_callee__ inline void asc_storealign_pack_v2(__ubuf__ uint32_t* dst_align32b, vector_uint32_t src, addr_reg offset, | 647 | __simd_callee__ inline void asc_storealign_pack_v2(__ubuf__ uint32_t* dst_align32b, vector_uint32_t src, addr_reg offset, |
| 648 | vector_bool mask) | 648 | vector_bool mask) |
| 649 | { | 649 | { |
| 650 | - asc_storealign_pack_v2_impl(dst_align32b, src, offset, mask); | 650 | + asc_storealign_pack_v2_impl(dst_align32b, src, offset, mask); |
| 651 | } | 651 | } |
| 652 | 652 | ||
| 653 | [[deprecated("NOTICE: asc_storealign_pack_v2 is deprecated. " | 653 | [[deprecated("NOTICE: asc_storealign_pack_v2 is deprecated. " |
| @@ -655,74 +655,74 @@ __simd_callee__ inline void asc_storealign_pack_v2(__ubuf__ uint32_t* dst_align | |||
| 655 | __simd_callee__ inline void asc_storealign_pack_v2(__ubuf__ float* dst_align32b, vector_float src, addr_reg offset, | 655 | __simd_callee__ inline void asc_storealign_pack_v2(__ubuf__ float* dst_align32b, vector_float src, addr_reg offset, |
| 656 | vector_bool mask) | 656 | vector_bool mask) |
| 657 | { | 657 | { |
| 658 | - asc_storealign_pack_v2_impl(dst_align32b, src, offset, mask); | 658 | + asc_storealign_pack_v2_impl(dst_align32b, src, offset, mask); |
| 659 | } | 659 | } |
| 660 | 660 | ||
| 661 | // ==========asc_storealign_intlv(u8/s8/half/u16/s16/u32/s32/bf16/e4m3/e5m2/e8m0/e2m1/e1m2)========= | 661 | // ==========asc_storealign_intlv(u8/s8/half/u16/s16/u32/s32/bf16/e4m3/e5m2/e8m0/e2m1/e1m2)========= |
| 662 | __simd_callee__ inline void asc_storealign_intlv(__ubuf__ int8_t* dst_align32b, vector_int8_t src0, | 662 | __simd_callee__ inline void asc_storealign_intlv(__ubuf__ int8_t* dst_align32b, vector_int8_t src0, |
| 663 | vector_int8_t src1, addr_reg offset) | 663 | vector_int8_t src1, addr_reg offset) |
| 664 | { | 664 | { |
| 665 | - asc_storealign_intlv_impl(dst_align32b, src0, src1, offset); | 665 | + asc_storealign_intlv_impl(dst_align32b, src0, src1, offset); |
| 666 | } | 666 | } |
| 667 | 667 | ||
| 668 | __simd_callee__ inline void asc_storealign_intlv(__ubuf__ uint8_t* dst_align32b, vector_uint8_t src0, | 668 | __simd_callee__ inline void asc_storealign_intlv(__ubuf__ uint8_t* dst_align32b, vector_uint8_t src0, |
| 669 | vector_uint8_t src1, addr_reg offset) | 669 | vector_uint8_t src1, addr_reg offset) |
| 670 | { | 670 | { |
| 671 | - asc_storealign_intlv_impl(dst_align32b, src0, src1, offset); | 671 | + asc_storealign_intlv_impl(dst_align32b, src0, src1, offset); |
| 672 | } | 672 | } |
| 673 | 673 | ||
| 674 | __simd_callee__ inline void asc_storealign_intlv(__ubuf__ int16_t* dst_align32b, vector_int16_t src0, | 674 | __simd_callee__ inline void asc_storealign_intlv(__ubuf__ int16_t* dst_align32b, vector_int16_t src0, |
| 675 | vector_int16_t src1, addr_reg offset) | 675 | vector_int16_t src1, addr_reg offset) |
| 676 | { | 676 | { |
| 677 | - asc_storealign_intlv_impl(dst_align32b, src0, src1, offset); | 677 | + asc_storealign_intlv_impl(dst_align32b, src0, src1, offset); |
| 678 | } | 678 | } |
| 679 | 679 | ||
| 680 | __simd_callee__ inline void asc_storealign_intlv(__ubuf__ uint16_t* dst_align32b, vector_uint16_t src0, | 680 | __simd_callee__ inline void asc_storealign_intlv(__ubuf__ uint16_t* dst_align32b, vector_uint16_t src0, |
| 681 | vector_uint16_t src1, addr_reg offset) | 681 | vector_uint16_t src1, addr_reg offset) |
| 682 | { | 682 | { |
| 683 | - asc_storealign_intlv_impl(dst_align32b, src0, src1, offset); | 683 | + asc_storealign_intlv_impl(dst_align32b, src0, src1, offset); |
| 684 | } | 684 | } |
| 685 | 685 | ||
| 686 | __simd_callee__ inline void asc_storealign_intlv(__ubuf__ int32_t* dst_align32b, vector_int32_t src0, | 686 | __simd_callee__ inline void asc_storealign_intlv(__ubuf__ int32_t* dst_align32b, vector_int32_t src0, |
| 687 | vector_int32_t src1, addr_reg offset) | 687 | vector_int32_t src1, addr_reg offset) |
| 688 | { | 688 | { |
| 689 | - asc_storealign_intlv_impl(dst_align32b, src0, src1, offset); | 689 | + asc_storealign_intlv_impl(dst_align32b, src0, src1, offset); |
| 690 | } | 690 | } |
| 691 | 691 | ||
| 692 | __simd_callee__ inline void asc_storealign_intlv(__ubuf__ uint32_t* dst_align32b, vector_uint32_t src0, | 692 | __simd_callee__ inline void asc_storealign_intlv(__ubuf__ uint32_t* dst_align32b, vector_uint32_t src0, |
| 693 | vector_uint32_t src1, addr_reg offset) | 693 | vector_uint32_t src1, addr_reg offset) |
| 694 | { | 694 | { |
| 695 | - asc_storealign_intlv_impl(dst_align32b, src0, src1, offset); | 695 | + asc_storealign_intlv_impl(dst_align32b, src0, src1, offset); |
| 696 | } | 696 | } |
| 697 | 697 | ||
| 698 | __simd_callee__ inline void asc_storealign_intlv(__ubuf__ half* dst_align32b, vector_half src0, | 698 | __simd_callee__ inline void asc_storealign_intlv(__ubuf__ half* dst_align32b, vector_half src0, |
| 699 | vector_half src1, addr_reg offset) | 699 | vector_half src1, addr_reg offset) |
| 700 | { | 700 | { |
| 701 | - asc_storealign_intlv_impl(dst_align32b, src0, src1, offset); | 701 | + asc_storealign_intlv_impl(dst_align32b, src0, src1, offset); |
| 702 | } | 702 | } |
| 703 | 703 | ||
| 704 | __simd_callee__ inline void asc_storealign_intlv(__ubuf__ bfloat16_t* dst_align32b, vector_bfloat16_t src0, | 704 | __simd_callee__ inline void asc_storealign_intlv(__ubuf__ bfloat16_t* dst_align32b, vector_bfloat16_t src0, |
| 705 | vector_bfloat16_t src1, addr_reg offset) | 705 | vector_bfloat16_t src1, addr_reg offset) |
| 706 | { | 706 | { |
| 707 | - asc_storealign_intlv_impl(dst_align32b, src0, src1, offset); | 707 | + asc_storealign_intlv_impl(dst_align32b, src0, src1, offset); |
| 708 | } | 708 | } |
| 709 | 709 | ||
| 710 | __simd_callee__ inline void asc_storealign_intlv(__ubuf__ fp8_e4m3fn_t* dst_align32b, vector_fp8_e4m3fn_t src0, | 710 | __simd_callee__ inline void asc_storealign_intlv(__ubuf__ fp8_e4m3fn_t* dst_align32b, vector_fp8_e4m3fn_t src0, |
| 711 | vector_fp8_e4m3fn_t src1, addr_reg offset) | 711 | vector_fp8_e4m3fn_t src1, addr_reg offset) |
| 712 | { | 712 | { |
| 713 | - asc_storealign_intlv_impl(dst_align32b, src0, src1, offset); | 713 | + asc_storealign_intlv_impl(dst_align32b, src0, src1, offset); |
| 714 | } | 714 | } |
| 715 | 715 | ||
| 716 | __simd_callee__ inline void asc_storealign_intlv(__ubuf__ hifloat8_t* dst_align32b, vector_hifloat8_t src0, | 716 | __simd_callee__ inline void asc_storealign_intlv(__ubuf__ hifloat8_t* dst_align32b, vector_hifloat8_t src0, |
| 717 | vector_hifloat8_t src1, addr_reg offset) | 717 | vector_hifloat8_t src1, addr_reg offset) |
| 718 | { | 718 | { |
| 719 | - asc_storealign_intlv_impl(dst_align32b, src0, src1, offset); | 719 | + asc_storealign_intlv_impl(dst_align32b, src0, src1, offset); |
| 720 | } | 720 | } |
| 721 | 721 | ||
| 722 | __simd_callee__ inline void asc_storealign_intlv(__ubuf__ fp8_e5m2_t* dst_align32b, vector_fp8_e5m2_t src0, | 722 | __simd_callee__ inline void asc_storealign_intlv(__ubuf__ fp8_e5m2_t* dst_align32b, vector_fp8_e5m2_t src0, |
| 723 | vector_fp8_e5m2_t src1, addr_reg offset) | 723 | vector_fp8_e5m2_t src1, addr_reg offset) |
| 724 | { | 724 | { |
| 725 | - asc_storealign_intlv_impl(dst_align32b, src0, src1, offset); | 725 | + asc_storealign_intlv_impl(dst_align32b, src0, src1, offset); |
| 726 | } | 726 | } |
| 727 | 727 | ||
| 728 | __simd_callee__ inline void asc_storealign_intlv(__ubuf__ fp8_e8m0_t* dst_align32b, vector_fp8_e8m0_t src0, | 728 | __simd_callee__ inline void asc_storealign_intlv(__ubuf__ fp8_e8m0_t* dst_align32b, vector_fp8_e8m0_t src0, |
| @@ -734,7 +734,7 @@ __simd_callee__ inline void asc_storealign_intlv(__ubuf__ fp8_e8m0_t* dst_align | |||
| 734 | __simd_callee__ inline void asc_storealign_intlv(__ubuf__ fp4x2_e2m1_t* dst_align32b, vector_fp4x2_e2m1_t src0, | 734 | __simd_callee__ inline void asc_storealign_intlv(__ubuf__ fp4x2_e2m1_t* dst_align32b, vector_fp4x2_e2m1_t src0, |
| 735 | vector_fp4x2_e2m1_t src1, addr_reg offset) | 735 | vector_fp4x2_e2m1_t src1, addr_reg offset) |
| 736 | { | 736 | { |
| 737 | - asc_storealign_intlv_impl(dst_align32b, src0, src1, offset); | 737 | + asc_storealign_intlv_impl(dst_align32b, src0, src1, offset); |
| 738 | } | 738 | } |
| 739 | 739 | ||
| 740 | __simd_callee__ inline void asc_storealign_intlv(__ubuf__ fp4x2_e1m2_t* dst_align32b, vector_fp4x2_e1m2_t src0, | 740 | __simd_callee__ inline void asc_storealign_intlv(__ubuf__ fp4x2_e1m2_t* dst_align32b, vector_fp4x2_e1m2_t src0, |
| @@ -1419,7 +1419,7 @@ __simd_callee__ inline void asc_storeunalign_postupdate(__ubuf__ uint32_t*& dst | |||
| 1419 | { | 1419 | { |
| 1420 | asc_storeunalign_postupdate_impl(dst, src0, src1, count); | 1420 | asc_storeunalign_postupdate_impl(dst, src0, src1, count); |
| 1421 | } | 1421 | } |
| 1422 | - | 1422 | + |
| 1423 | __simd_callee__ inline void asc_storeunalign_postupdate(__ubuf__ int64_t*& dst, vector_store_unalign& src0, | 1423 | __simd_callee__ inline void asc_storeunalign_postupdate(__ubuf__ int64_t*& dst, vector_store_unalign& src0, |
| 1424 | vector_int64_t src1, uint32_t count) | 1424 | vector_int64_t src1, uint32_t count) |
| 1425 | { | 1425 | { |
| @@ -48,4 +48,4 @@ __aicore__ inline void asc_copy_ub2l1_sync_impl(__cbuf__ void* dst, __ubuf__ voi | |||
| 48 | 48 | ||
| 49 | 49 | ||
| 50 | 50 | ||
| 51 | -#endif | 51 | +#endif |
| @@ -48,4 +48,4 @@ __aicore__ inline void asc_copy_ub2ub_sync_impl(__ubuf__ void* dst, __ubuf__ voi | |||
| 48 | 48 | ||
| 49 | 49 | ||
| 50 | 50 | ||
| 51 | -#endif | 51 | +#endif |
| @@ -40,4 +40,4 @@ __simd_callee__ inline vector_bool asc_get_mask_spr_b32_impl() | |||
| 40 | 40 | ||
| 41 | 41 | ||
| 42 | 42 | ||
| 43 | -#endif | 43 | +#endif |
| @@ -36,4 +36,4 @@ __aicore__ inline void asc_ndim_copy_dci_impl() | |||
| 36 | 36 | ||
| 37 | 37 | ||
| 38 | 38 | ||
| 39 | -#endif | 39 | +#endif |
| @@ -158,4 +158,4 @@ __aicore__ inline void asc_ndim_copy_gm2ub_impl(__ubuf__ float* dst, __gm__ floa | |||
| 158 | } | 158 | } |
| 159 | } | 159 | } |
| 160 | 160 | ||
| 161 | -#endif | 161 | +#endif |
| @@ -94,4 +94,4 @@ __aicore__ inline void asc_set_copy_pad_val_impl(float pad_value) | |||
| 94 | 94 | ||
| 95 | 95 | ||
| 96 | 96 | ||
| 97 | -#endif | 97 | +#endif |
| @@ -70,4 +70,4 @@ __aicore__ inline void asc_set_ndim_loop4_stride_impl(uint64_t dst_stride, uint6 | |||
| 70 | 70 | ||
| 71 | 71 | ||
| 72 | 72 | ||
| 73 | -#endif | 73 | +#endif |
| @@ -24,4 +24,4 @@ __aicore__ inline void asc_set_ndim_pad_count_impl(asc_ndim_pad_count_config& co | |||
| 24 | } | 24 | } |
| 25 | } | 25 | } |
| 26 | 26 | ||
| 27 | -#endif | 27 | +#endif |
| @@ -81,4 +81,4 @@ __aicore__ inline void asc_set_ndim_pad_value_impl(float pad_value) | |||
| 81 | } | 81 | } |
| 82 | } | 82 | } |
| 83 | 83 | ||
| 84 | -#endif | 84 | +#endif |
| @@ -29,9 +29,9 @@ __aicore__ inline void asc_set_ub2gm_loop1_stride_impl(uint64_t loop1_src_stride | |||
| 29 | { | 29 | { |
| 30 | if ASC_IS_AIV { | 30 | if ASC_IS_AIV { |
| 31 | uint64_t config = loop1_src_stride << 40; | 31 | uint64_t config = loop1_src_stride << 40; |
| 32 | - config |= loop1_dst_stride; | 32 | + config |= loop1_dst_stride; |
| 33 | set_loop1_stride_ubtoout(config); | 33 | set_loop1_stride_ubtoout(config); |
| 34 | } | 34 | } |
| 35 | } | 35 | } |
| 36 | 36 | ||
| 37 | -#endif | 37 | +#endif |
| @@ -29,9 +29,9 @@ __aicore__ inline void asc_set_ub2gm_loop2_stride_impl(uint64_t loop2_src_stride | |||
| 29 | { | 29 | { |
| 30 | if ASC_IS_AIV { | 30 | if ASC_IS_AIV { |
| 31 | uint64_t config = loop2_src_stride << 40; | 31 | uint64_t config = loop2_src_stride << 40; |
| 32 | - config |= loop2_dst_stride; | 32 | + config |= loop2_dst_stride; |
| 33 | set_loop2_stride_ubtoout(config); | 33 | set_loop2_stride_ubtoout(config); |
| 34 | } | 34 | } |
| 35 | } | 35 | } |
| 36 | 36 | ||
| 37 | -#endif | 37 | +#endif |
| @@ -29,9 +29,9 @@ __aicore__ inline void asc_set_ub2gm_loop_size_impl(uint32_t loop1_size, uint32_ | |||
| 29 | { | 29 | { |
| 30 | if ASC_IS_AIV { | 30 | if ASC_IS_AIV { |
| 31 | uint64_t config = static_cast<uint64_t>(loop2_size) << 21; | 31 | uint64_t config = static_cast<uint64_t>(loop2_size) << 21; |
| 32 | - config |= static_cast<uint64_t>(loop1_size); | 32 | + config |= static_cast<uint64_t>(loop1_size); |
| 33 | set_loop_size_ubtoout(config); | 33 | set_loop_size_ubtoout(config); |
| 34 | } | 34 | } |
| 35 | } | 35 | } |
| 36 | 36 | ||
| 37 | -#endif | 37 | +#endif |
| @@ -318,7 +318,7 @@ __simd_callee__ inline void asc_gather_datablock_impl(vector_int4x2_t& dst, __ub | |||
| 318 | } | 318 | } |
| 319 | } | 319 | } |
| 320 | 320 | ||
| 321 | -__simd_callee__ inline void asc_gather_datablock_impl(vector_fp8_e8m0_t& dst, __ubuf__ fp8_e8m0_t* src, | 321 | +__simd_callee__ inline void asc_gather_datablock_impl(vector_fp8_e8m0_t& dst, __ubuf__ fp8_e8m0_t* src, |
| 322 | vector_uint32_t index) | 322 | vector_uint32_t index) |
| 323 | { | 323 | { |
| 324 | if ASC_IS_AIV { | 324 | if ASC_IS_AIV { |
| @@ -256,4 +256,4 @@ __simd_callee__ inline void asc_gather_impl(vector_fp8_e8m0_t& dst, vector_fp8_e | |||
| 256 | } | 256 | } |
| 257 | } | 257 | } |
| 258 | 258 | ||
| 259 | -#endif | 259 | +#endif |
| @@ -142,4 +142,4 @@ __simd_callee__ inline void asc_loadunalign_impl(vector_int4x2_t& dst, vector_lo | |||
| 142 | } | 142 | } |
| 143 | } | 143 | } |
| 144 | 144 | ||
| 145 | -#endif | 145 | +#endif |
Mimpl/c_api/instr_impl/npu_arch_3510/vector_datamove_impl/reg_load/asc_loadunalign_postupdate_impl.h+1-1
| @@ -268,4 +268,4 @@ __simd_callee__ inline void asc_loadunalign_postupdate_impl(vector_fp8_e8m0_t& d | |||
| 268 | 268 | ||
| 269 | 269 | ||
| 270 | 270 | ||
| 271 | -#endif | 271 | +#endif |
| @@ -280,4 +280,4 @@ __simd_callee__ inline void asc_loadunalign_pre_impl(vector_load_unalign& dst, _ | |||
| 280 | 280 | ||
| 281 | 281 | ||
| 282 | 282 | ||
| 283 | -#endif | 283 | +#endif |
| @@ -42,7 +42,7 @@ __simd_callee__ inline void asc_store_impl(__ubuf__ uint8_t* dst, vector_uint8_ | |||
| 42 | } | 42 | } |
| 43 | } | 43 | } |
| 44 | 44 | ||
| 45 | -__simd_callee__ inline void asc_store_impl(__ubuf__ int16_t* dst, vector_int16_t src) | 45 | +__simd_callee__ inline void asc_store_impl(__ubuf__ int16_t* dst, vector_int16_t src) |
| 46 | { | 46 | { |
| 47 | if ASC_IS_AIV { | 47 | if ASC_IS_AIV { |
| 48 | vector_store_unalign ureg; | 48 | vector_store_unalign ureg; |
| @@ -346,4 +346,4 @@ __simd_callee__ inline void asc_store_impl(__ubuf__ int4b_t* dst, vector_int4x2_ | |||
| 346 | } | 346 | } |
| 347 | } | 347 | } |
| 348 | 348 | ||
| 349 | -#endif | 349 | +#endif |
| @@ -536,7 +536,7 @@ __simd_callee__ inline void asc_storealign_intlv_impl(__ubuf__ int4b_t* dst_ali | |||
| 536 | if ASC_IS_AIV { | 536 | if ASC_IS_AIV { |
| 537 | vector_bool mask; | 537 | vector_bool mask; |
| 538 | __ubuf__ float4_e1m2x2_t* dst_align32b_tmp = reinterpret_cast<__ubuf__ float4_e1m2x2_t*>(dst_align32b); | 538 | __ubuf__ float4_e1m2x2_t* dst_align32b_tmp = reinterpret_cast<__ubuf__ float4_e1m2x2_t*>(dst_align32b); |
| 539 | - vsts(*reinterpret_cast<vector_fp4x2_e1m2_t*>(&src0), *reinterpret_cast<vector_fp4x2_e1m2_t*>(&src1), | 539 | + vsts(*reinterpret_cast<vector_fp4x2_e1m2_t*>(&src0), *reinterpret_cast<vector_fp4x2_e1m2_t*>(&src1), |
| 540 | dst_align32b_tmp, 0, INTLV_B8, mask); | 540 | dst_align32b_tmp, 0, INTLV_B8, mask); |
| 541 | } | 541 | } |
| 542 | } | 542 | } |
Mimpl/c_api/instr_impl/npu_arch_3510/vector_datamove_impl/reg_store/asc_storeunalign_post_impl.h+1-1
| @@ -386,4 +386,4 @@ __simd_callee__ inline void asc_storeunalign_post_impl(__ubuf__ int4b_t* dst, ve | |||
| 386 | } | 386 | } |
| 387 | } | 387 | } |
| 388 | 388 | ||
| 389 | -#endif | 389 | +#endif |
| @@ -143,4 +143,4 @@ __simd_callee__ inline void asc_storeunalign_post_postupdate_impl(__ubuf__ int4b | |||
| 143 | } | 143 | } |
| 144 | } | 144 | } |
| 145 | 145 | ||
| 146 | -#endif | 146 | +#endif |
| @@ -44,4 +44,4 @@ void GetGeGLUMaxMinTmpSize( | |||
| 44 | */ | 44 | */ |
| 45 | void GetGeGLUTmpBufferFactorSize(const uint32_t typeSize, uint32_t& maxLiveNodeCount, uint32_t& extraBuf); | 45 | void GetGeGLUTmpBufferFactorSize(const uint32_t typeSize, uint32_t& maxLiveNodeCount, uint32_t& extraBuf); |
| 46 | } // namespace AscendC | 46 | } // namespace AscendC |
| 47 | -#endif // LIB_ACTIVATION_GEGLU_TILING_H | 47 | +#endif // LIB_ACTIVATION_GEGLU_TILING_H |
| @@ -21,4 +21,4 @@ namespace AscendC { | |||
| 21 | typedef void UsingDeprecatedHeader; | 21 | typedef void UsingDeprecatedHeader; |
| 22 | using LibTilingGegluTilingInterface = UsingDeprecatedHeader; | 22 | using LibTilingGegluTilingInterface = UsingDeprecatedHeader; |
| 23 | } // namespace AscendC | 23 | } // namespace AscendC |
| 24 | -#endif // LIB_ACTIVATION_GEGLU_TILING_INTF_H | 24 | +#endif // LIB_ACTIVATION_GEGLU_TILING_INTF_H |
| @@ -43,4 +43,4 @@ uint32_t GetGeluMaxTmpSize(const ge::Shape& srcShape, const uint32_t typeSize); | |||
| 43 | */ | 43 | */ |
| 44 | void GetGeluMaxMinTmpSize(const ge::Shape& srcShape, const uint32_t typeSize, uint32_t& maxValue, uint32_t& minValue); | 44 | void GetGeluMaxMinTmpSize(const ge::Shape& srcShape, const uint32_t typeSize, uint32_t& maxValue, uint32_t& minValue); |
| 45 | } // namespace AscendC | 45 | } // namespace AscendC |
| 46 | -#endif // TILING_GELU_TILING_H | 46 | +#endif // TILING_GELU_TILING_H |
| @@ -21,4 +21,4 @@ namespace AscendC { | |||
| 21 | typedef void UsingDeprecatedHeader; | 21 | typedef void UsingDeprecatedHeader; |
| 22 | using LibTilingGeluTilingInterface = UsingDeprecatedHeader; | 22 | using LibTilingGeluTilingInterface = UsingDeprecatedHeader; |
| 23 | } // namespace AscendC | 23 | } // namespace AscendC |
| 24 | -#endif // TILING_GELU_TILING_INTF_H | 24 | +#endif // TILING_GELU_TILING_INTF_H |
| @@ -32,4 +32,4 @@ using ASCENDC_MODULE_OPERATOR_GEGLU_INTERFACE = using_deprecated_header_h; | |||
| 32 | 32 | ||
| 33 | 33 | ||
| 34 | 34 | ||
| 35 | -#endif | 35 | +#endif |
| @@ -31,4 +31,4 @@ using AscendCModuleGeluInterface = GeluDeprecatedHeader; | |||
| 31 | 31 | ||
| 32 | 32 | ||
| 33 | 33 | ||
| 34 | -#endif | 34 | +#endif |
| @@ -31,4 +31,4 @@ using ASCENDC_MODULE_OPERATOR_LOGSOFTMAX_INTERFACE = using_deprecated_header_h; | |||
| 31 | 31 | ||
| 32 | 32 | ||
| 33 | 33 | ||
| 34 | -#endif | 34 | +#endif |
| @@ -31,4 +31,4 @@ using LIB_REGLU_REGLU_KERNEL_OPERATOR_REGLU_INTF = using_deprecated_header_h; | |||
| 31 | 31 | ||
| 32 | 32 | ||
| 33 | 33 | ||
| 34 | -#endif | 34 | +#endif |
| @@ -31,4 +31,4 @@ using AscendCModuleSigmoidInterface = SigmoidDeprecatedHeader; | |||
| 31 | 31 | ||
| 32 | 32 | ||
| 33 | 33 | ||
| 34 | -#endif | 34 | +#endif |
| @@ -31,4 +31,4 @@ using LIB_MATH_KERNEL_OPERATOR_SILU_INTF = using_deprecated_header_h; | |||
| 31 | 31 | ||
| 32 | 32 | ||
| 33 | 33 | ||
| 34 | -#endif | 34 | +#endif |
| @@ -31,4 +31,4 @@ using ASCENDC_MODULE_OPERATOR_SIMPLE_SOFTMAX_INTERFACE = using_deprecated_header | |||
| 31 | 31 | ||
| 32 | 32 | ||
| 33 | 33 | ||
| 34 | -#endif | 34 | +#endif |
| @@ -31,4 +31,4 @@ using AscendCModuleOperatorSoftmaxflashInterface = using_deprecated_header_h; | |||
| 31 | 31 | ||
| 32 | 32 | ||
| 33 | 33 | ||
| 34 | -#endif | 34 | +#endif |
| @@ -30,4 +30,4 @@ using ASCENDC_MODULE_OPERATOR_SOFTMAX_FLASHV2_INTERFACE = using_deprecated_heade | |||
| 30 | 30 | ||
| 31 | 31 | ||
| 32 | 32 | ||
| 33 | -#endif | 33 | +#endif |
| @@ -31,4 +31,4 @@ using ASCENDC_MODULE_OPERATOR_SOFTMAX_GRAD_INTERFACE = using_deprecated_header_h | |||
| 31 | 31 | ||
| 32 | 32 | ||
| 33 | 33 | ||
| 34 | -#endif | 34 | +#endif |
| @@ -31,4 +31,4 @@ using ASCENDC_MODULE_OPERATOR_SOFTMAX_INTERFACE = using_deprecated_header_h; | |||
| 31 | 31 | ||
| 32 | 32 | ||
| 33 | 33 | ||
| 34 | -#endif | 34 | +#endif |
| @@ -33,4 +33,4 @@ using ASCENDC_MODULE_OPERATOR_SWIGLU_INTERFACE = using_deprecated_header_h; | |||
| 33 | 33 | ||
| 34 | 34 | ||
| 35 | 35 | ||
| 36 | -#endif | 36 | +#endif |
| @@ -31,4 +31,4 @@ using LIB_SWISH_SWISH_KERNEL_OPERATOR_SWISH_INTF = using_deprecated_header_h; | |||
| 31 | 31 | ||
| 32 | 32 | ||
| 33 | 33 | ||
| 34 | -#endif | 34 | +#endif |
| @@ -53,4 +53,4 @@ void LogSoftMaxTilingFunc( | |||
| 53 | const ge::Shape srcShape, const uint32_t dataTypeSize, const uint32_t localWorkSpaceSize, | 53 | const ge::Shape srcShape, const uint32_t dataTypeSize, const uint32_t localWorkSpaceSize, |
| 54 | AscendC::tiling::LogSoftMaxTiling& softmaxTiling); | 54 | AscendC::tiling::LogSoftMaxTiling& softmaxTiling); |
| 55 | } // namespace AscendC | 55 | } // namespace AscendC |
| 56 | -#endif // LIB_ACTIVATION_LOGSOFTMAX_TILING_H | 56 | +#endif // LIB_ACTIVATION_LOGSOFTMAX_TILING_H |
| @@ -21,4 +21,4 @@ namespace AscendC { | |||
| 21 | typedef void UsingDeprecatedHeader; | 21 | typedef void UsingDeprecatedHeader; |
| 22 | using LibLogSoftMaxTilingIntf = UsingDeprecatedHeader; | 22 | using LibLogSoftMaxTilingIntf = UsingDeprecatedHeader; |
| 23 | } // namespace AscendC | 23 | } // namespace AscendC |
| 24 | -#endif // LIB_ACTIVATION_LOGSOFTMAX_TILING_INTF_H | 24 | +#endif // LIB_ACTIVATION_LOGSOFTMAX_TILING_INTF_H |
| @@ -37,4 +37,4 @@ TILING_DATA_FIELD_DEF(uint32_t, tailSplitSize); | |||
| 37 | TILING_DATA_FIELD_DEF(uint32_t, tailReduceSize); | 37 | TILING_DATA_FIELD_DEF(uint32_t, tailReduceSize); |
| 38 | END_TILING_DATA_DEF; | 38 | END_TILING_DATA_DEF; |
| 39 | } // namespace optiling | 39 | } // namespace optiling |
| 40 | -#endif // __ASCENDC_TIKCFW_TILING_LOGSOFTMAX_TILINGDATA_H__ | 40 | +#endif // __ASCENDC_TIKCFW_TILING_LOGSOFTMAX_TILINGDATA_H__ |
| @@ -33,4 +33,4 @@ void GetReGluMaxMinTmpSize( | |||
| 33 | const ge::Shape& srcShape, const uint32_t typeSize, const bool isReuseSource, uint32_t& maxValue, | 33 | const ge::Shape& srcShape, const uint32_t typeSize, const bool isReuseSource, uint32_t& maxValue, |
| 34 | uint32_t& minValue); | 34 | uint32_t& minValue); |
| 35 | } // namespace AscendC | 35 | } // namespace AscendC |
| 36 | -#endif // LIB_REGLU_REGLU_TILING_H | 36 | +#endif // LIB_REGLU_REGLU_TILING_H |
| @@ -22,4 +22,4 @@ namespace AscendC { | |||
| 22 | using LIB_REGLU_REGLU_TILING_INTF = using_deprecated_header_h; | 22 | using LIB_REGLU_REGLU_TILING_INTF = using_deprecated_header_h; |
| 23 | } // namespace AscendC | 23 | } // namespace AscendC |
| 24 | 24 | ||
| 25 | -#endif // LIB_REGLU_REGLU_TILING_INTF_H | 25 | +#endif // LIB_REGLU_REGLU_TILING_INTF_H |
| @@ -33,4 +33,4 @@ void GetSigmoidMaxMinTmpSize( | |||
| 33 | const ge::Shape& srcShape, const uint32_t typeSize, bool isReuseSource, uint32_t& maxValue, uint32_t& minValue); | 33 | const ge::Shape& srcShape, const uint32_t typeSize, bool isReuseSource, uint32_t& maxValue, uint32_t& minValue); |
| 34 | 34 | ||
| 35 | } // namespace AscendC | 35 | } // namespace AscendC |
| 36 | -#endif // TILING_ACTIVATION_SIGMOID_TILING_H | 36 | +#endif // TILING_ACTIVATION_SIGMOID_TILING_H |
| @@ -21,4 +21,4 @@ namespace AscendC { | |||
| 21 | typedef void SigmoidTilingDeprecatedHeader; | 21 | typedef void SigmoidTilingDeprecatedHeader; |
| 22 | using LibSigmoidTilingInterface = SigmoidTilingDeprecatedHeader; | 22 | using LibSigmoidTilingInterface = SigmoidTilingDeprecatedHeader; |
| 23 | } // namespace AscendC | 23 | } // namespace AscendC |
| 24 | -#endif // TILING_MATH_SIGMOID_TILING_INTF_H | 24 | +#endif // TILING_MATH_SIGMOID_TILING_INTF_H |
| @@ -31,4 +31,4 @@ void GetSiluTmpSize( | |||
| 31 | const ge::Shape& srcShape, const uint32_t typeSize, const bool isReuseSource, uint32_t& maxValue, | 31 | const ge::Shape& srcShape, const uint32_t typeSize, const bool isReuseSource, uint32_t& maxValue, |
| 32 | uint32_t& minValue); | 32 | uint32_t& minValue); |
| 33 | } // namespace AscendC | 33 | } // namespace AscendC |
| 34 | -#endif | 34 | +#endif |
| @@ -20,4 +20,4 @@ namespace AscendC { | |||
| 20 | typedef void SiluTilingDeprecatedHeader; | 20 | typedef void SiluTilingDeprecatedHeader; |
| 21 | using LibSiluTilingInterface = SiluTilingDeprecatedHeader; | 21 | using LibSiluTilingInterface = SiluTilingDeprecatedHeader; |
| 22 | } // namespace AscendC | 22 | } // namespace AscendC |
| 23 | -#endif | 23 | +#endif |
| @@ -22,4 +22,4 @@ namespace AscendC { | |||
| 22 | using LIB_SOFTMAX_SOFTMAX_TILING_INTF = using_deprecated_header_h; | 22 | using LIB_SOFTMAX_SOFTMAX_TILING_INTF = using_deprecated_header_h; |
| 23 | } // namespace AscendC | 23 | } // namespace AscendC |
| 24 | 24 | ||
| 25 | -#endif // LIB_SOFTMAX_SOFTMAX_TILING_INTF_H | 25 | +#endif // LIB_SOFTMAX_SOFTMAX_TILING_INTF_H |
| @@ -37,4 +37,4 @@ TILING_DATA_FIELD_DEF(uint32_t, tailSplitSize); | |||
| 37 | TILING_DATA_FIELD_DEF(uint32_t, tailReduceSize); | 37 | TILING_DATA_FIELD_DEF(uint32_t, tailReduceSize); |
| 38 | END_TILING_DATA_DEF; | 38 | END_TILING_DATA_DEF; |
| 39 | } // namespace optiling | 39 | } // namespace optiling |
| 40 | -#endif // LIB_SOFTMAX_SOFTMAX_TILINGDATA_H | 40 | +#endif // LIB_SOFTMAX_SOFTMAX_TILINGDATA_H |
| @@ -45,4 +45,4 @@ void GetSwiGLUMaxMinTmpSize( | |||
| 45 | */ | 45 | */ |
| 46 | void GetSwiGLUTmpBufferFactorSize(const uint32_t typeSize, uint32_t& maxLiveNodeCount, uint32_t& extraBuffer); | 46 | void GetSwiGLUTmpBufferFactorSize(const uint32_t typeSize, uint32_t& maxLiveNodeCount, uint32_t& extraBuffer); |
| 47 | } // namespace AscendC | 47 | } // namespace AscendC |
| 48 | -#endif // LIB_ACTIVATION_SWIGLU_TILING_H | 48 | +#endif // LIB_ACTIVATION_SWIGLU_TILING_H |
| @@ -22,4 +22,4 @@ namespace AscendC { | |||
| 22 | typedef void SwigluTilingDeprecatedHeader; | 22 | typedef void SwigluTilingDeprecatedHeader; |
| 23 | using LibSwigluTilingInterface = SwigluTilingDeprecatedHeader; | 23 | using LibSwigluTilingInterface = SwigluTilingDeprecatedHeader; |
| 24 | } // namespace AscendC | 24 | } // namespace AscendC |
| 25 | -#endif // LIB_ACTIVATION_SWIGLU_TILING_INTF_H | 25 | +#endif // LIB_ACTIVATION_SWIGLU_TILING_INTF_H |
| @@ -32,4 +32,4 @@ void GetSwishTmpSize( | |||
| 32 | const ge::Shape& srcShape, const uint32_t typeSize, const bool isReuseSource, uint32_t& maxValue, | 32 | const ge::Shape& srcShape, const uint32_t typeSize, const bool isReuseSource, uint32_t& maxValue, |
| 33 | uint32_t& minValue); | 33 | uint32_t& minValue); |
| 34 | } // namespace AscendC | 34 | } // namespace AscendC |
| 35 | -#endif | 35 | +#endif |